Lines Matching refs:sclk_frequency
148 sclk_voltage_mapping_table->entries[n].sclk_frequency = in sumo_construct_sclk_voltage_mapping_table()
823 if (table->entries[i].sclk_frequency == pi->boot_pl.sclk) in kv_program_bootup_state()
1192 if (kv_get_clock_difference(table->entries[i].sclk_frequency, 40000) < 200) in kv_calculate_dfs_bypass_settings()
1194 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 30000) < 200) in kv_calculate_dfs_bypass_settings()
1196 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 26600) < 200) in kv_calculate_dfs_bypass_settings()
1198 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 20000) < 200) in kv_calculate_dfs_bypass_settings()
1200 else if (kv_get_clock_difference(table->entries[i].sclk_frequency, 10000) < 200) in kv_calculate_dfs_bypass_settings()
1797 if (table->entries[i].sclk_frequency >= new_ps->levels[0].sclk || in kv_set_valid_clock_range()
1805 if (table->entries[i].sclk_frequency <= in kv_set_valid_clock_range()
1813 table->entries[pi->highest_valid].sclk_frequency) > in kv_set_valid_clock_range()
1814 (table->entries[pi->lowest_valid].sclk_frequency - in kv_set_valid_clock_range()
2028 pi->sys_info.sclk_voltage_mapping_table.entries[idx].sclk_frequency; in kv_construct_max_power_limits_table()
2263 ps->levels[i].sclk = table->entries[limit].sclk_frequency; in kv_apply_state_adjust_rules()
2437 kv_set_divider_value(adev, i, table->entries[i].sclk_frequency); in kv_init_graphics_levels()