Lines Matching refs:amdgpu_device

31 int nbio_v6_1_init(struct amdgpu_device *adev);
32 u32 nbio_v6_1_get_atombios_scratch_regs(struct amdgpu_device *adev,
34 void nbio_v6_1_set_atombios_scratch_regs(struct amdgpu_device *adev,
36 void nbio_v6_1_mc_access_enable(struct amdgpu_device *adev, bool enable);
37 void nbio_v6_1_hdp_flush(struct amdgpu_device *adev);
38 u32 nbio_v6_1_get_memsize(struct amdgpu_device *adev);
39 void nbio_v6_1_sdma_doorbell_range(struct amdgpu_device *adev, int instance,
41 void nbio_v6_1_enable_doorbell_aperture(struct amdgpu_device *adev,
43 void nbio_v6_1_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
45 void nbio_v6_1_ih_doorbell_range(struct amdgpu_device *adev,
47 void nbio_v6_1_ih_control(struct amdgpu_device *adev);
48 u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev);
49 void nbio_v6_1_update_medium_grain_clock_gating(struct amdgpu_device *adev, bool enable);
50 void nbio_v6_1_update_medium_grain_light_sleep(struct amdgpu_device *adev, bool enable);
51 void nbio_v6_1_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
52 void nbio_v6_1_detect_hw_virt(struct amdgpu_device *adev);
53 void nbio_v6_1_init_registers(struct amdgpu_device *adev);