3146 	struct si_ps *new_ps = si_get_ps(rps);  in ni_update_current_ps()  local
3151 	ni_pi->current_ps = *new_ps;  in ni_update_current_ps()
3159 	struct si_ps *new_ps = si_get_ps(rps);  in ni_update_requested_ps()  local
3164 	ni_pi->requested_ps = *new_ps;  in ni_update_requested_ps()
3170 					   struct amdgpu_ps *new_ps,  in ni_set_uvd_clock_before_set_eng_clock()  argument
3173 	struct si_ps *new_state = si_get_ps(new_ps);  in ni_set_uvd_clock_before_set_eng_clock()
3176 	if ((new_ps->vclk == old_ps->vclk) &&  in ni_set_uvd_clock_before_set_eng_clock()
3177 	    (new_ps->dclk == old_ps->dclk))  in ni_set_uvd_clock_before_set_eng_clock()
3184 	amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);  in ni_set_uvd_clock_before_set_eng_clock()
3188 					  struct amdgpu_ps *new_ps,  in ni_set_uvd_clock_after_set_eng_clock()  argument
3191 	struct si_ps *new_state = si_get_ps(new_ps);  in ni_set_uvd_clock_after_set_eng_clock()
3194 	if ((new_ps->vclk == old_ps->vclk) &&  in ni_set_uvd_clock_after_set_eng_clock()
3195 	    (new_ps->dclk == old_ps->dclk))  in ni_set_uvd_clock_after_set_eng_clock()
3202 	amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);  in ni_set_uvd_clock_after_set_eng_clock()
6936 	struct amdgpu_ps *new_ps = &requested_ps;  in si_dpm_pre_set_power_state()  local
6938 	ni_update_requested_ps(adev, new_ps);  in si_dpm_pre_set_power_state()
6946 	struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;  in si_power_control_set_level()  local
6955 	ret = si_populate_smc_tdp_limits(adev, new_ps);  in si_power_control_set_level()
6958 	ret = si_populate_smc_tdp_limits_2(adev, new_ps);  in si_power_control_set_level()
6973 	struct amdgpu_ps *new_ps = &eg_pi->requested_rps;  in si_dpm_set_power_state()  local
6988 		si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);  in si_dpm_set_power_state()
6989 	ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);  in si_dpm_set_power_state()
6990 	ret = si_enable_power_containment(adev, new_ps, false);  in si_dpm_set_power_state()
6995 	ret = si_enable_smc_cac(adev, new_ps, false);  in si_dpm_set_power_state()
7005 	ret = si_upload_sw_state(adev, new_ps);  in si_dpm_set_power_state()
7021 		ret = si_upload_mc_reg_table(adev, new_ps);  in si_dpm_set_power_state()
7027 	ret = si_program_memory_timing_parameters(adev, new_ps);  in si_dpm_set_power_state()
7032 	si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);  in si_dpm_set_power_state()
7044 	ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);  in si_dpm_set_power_state()
7046 		si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);  in si_dpm_set_power_state()
7047 	ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);  in si_dpm_set_power_state()
7052 	ret = si_enable_smc_cac(adev, new_ps, true);  in si_dpm_set_power_state()
7057 	ret = si_enable_power_containment(adev, new_ps, true);  in si_dpm_set_power_state()
7075 	struct amdgpu_ps *new_ps = &eg_pi->requested_rps;  in si_dpm_post_set_power_state()  local
7077 	ni_update_current_ps(adev, new_ps);  in si_dpm_post_set_power_state()