518 		tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,  in uvd_v7_0_hw_init()
523 		tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,  in uvd_v7_0_hw_init()
528 		tmp = PACKET0(SOC15_REG_OFFSET(UVD, 0,  in uvd_v7_0_hw_init()
534 		amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,  in uvd_v7_0_hw_init()
538 		amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0,  in uvd_v7_0_hw_init()
1098 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));  in uvd_v7_0_ring_emit_fence()
1101 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_ring_emit_fence()
1104 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_ring_emit_fence()
1107 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_ring_emit_fence()
1111 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_ring_emit_fence()
1114 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_ring_emit_fence()
1117 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_ring_emit_fence()
1150 	amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(NBIF, 0,  in uvd_v7_0_ring_emit_hdp_flush()
1164 	amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 0));  in uvd_v7_0_ring_emit_hdp_invalidate()
1190 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));  in uvd_v7_0_ring_test_ring()
1224 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));  in uvd_v7_0_ring_emit_ib()
1228 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));  in uvd_v7_0_ring_emit_ib()
1231 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));  in uvd_v7_0_ring_emit_ib()
1234 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));  in uvd_v7_0_ring_emit_ib()
1260 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_vm_reg_write()
1263 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_vm_reg_write()
1266 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_vm_reg_write()
1274 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));  in uvd_v7_0_vm_reg_wait()
1277 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));  in uvd_v7_0_vm_reg_wait()
1280 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));  in uvd_v7_0_vm_reg_wait()
1283 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in uvd_v7_0_vm_reg_wait()
1690 	.nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),