1257 				uint32_t data0, uint32_t data1)  in uvd_v7_0_vm_reg_write()  argument
1261 	amdgpu_ring_write(ring, data0);  in uvd_v7_0_vm_reg_write()
1271 				uint32_t data0, uint32_t data1, uint32_t mask)  in uvd_v7_0_vm_reg_wait()  argument
1275 	amdgpu_ring_write(ring, data0);  in uvd_v7_0_vm_reg_wait()
1292 	uint32_t data0, data1, mask;  in uvd_v7_0_ring_emit_vm_flush()  local
1298 	data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;  in uvd_v7_0_ring_emit_vm_flush()
1300 	uvd_v7_0_vm_reg_write(ring, data0, data1);  in uvd_v7_0_ring_emit_vm_flush()
1302 	data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;  in uvd_v7_0_ring_emit_vm_flush()
1304 	uvd_v7_0_vm_reg_write(ring, data0, data1);  in uvd_v7_0_ring_emit_vm_flush()
1306 	data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;  in uvd_v7_0_ring_emit_vm_flush()
1309 	uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);  in uvd_v7_0_ring_emit_vm_flush()
1312 	data0 = (hub->vm_inv_eng0_req + eng) << 2;  in uvd_v7_0_ring_emit_vm_flush()
1314 	uvd_v7_0_vm_reg_write(ring, data0, data1);  in uvd_v7_0_ring_emit_vm_flush()
1317 	data0 = (hub->vm_inv_eng0_ack + eng) << 2;  in uvd_v7_0_ring_emit_vm_flush()
1320 	uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);  in uvd_v7_0_ring_emit_vm_flush()