154 	uint64_t addr = table->gpu_addr;  in vce_v4_0_mmsch_start()
232 					    lower_32_bits(ring->gpu_addr));  in vce_v4_0_sriov_start()
234 					    upper_32_bits(ring->gpu_addr));  in vce_v4_0_sriov_start()
254 						adev->vce.gpu_addr >> 8);  in vce_v4_0_sriov_start()
256 						adev->vce.gpu_addr >> 8);  in vce_v4_0_sriov_start()
258 						adev->vce.gpu_addr >> 8);  in vce_v4_0_sriov_start()
325 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO), ring->gpu_addr);  in vce_v4_0_start()
326 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI), upper_32_bits(ring->gpu_addr));  in vce_v4_0_start()
333 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO2), ring->gpu_addr);  in vce_v4_0_start()
334 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI2), upper_32_bits(ring->gpu_addr));  in vce_v4_0_start()
341 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_LO3), ring->gpu_addr);  in vce_v4_0_start()
342 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_BASE_HI3), upper_32_bits(ring->gpu_addr));  in vce_v4_0_start()
603 			(adev->vce.gpu_addr >> 8));  in vce_v4_0_mc_resume()
605 			(adev->vce.gpu_addr >> 40) & 0xff);  in vce_v4_0_mc_resume()
613 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR1), (adev->vce.gpu_addr >> 8));  in vce_v4_0_mc_resume()
614 …WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR1), (adev->vce.gpu_addr >> 40) & 0xf…  in vce_v4_0_mc_resume()
620 	WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_40BIT_BAR2), (adev->vce.gpu_addr >> 8));  in vce_v4_0_mc_resume()
621 …WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_LMI_VCPU_CACHE_64BIT_BAR2), (adev->vce.gpu_addr >> 40) & 0xf…  in vce_v4_0_mc_resume()
934 	amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));  in vce_v4_0_ring_emit_ib()
935 	amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));  in vce_v4_0_ring_emit_ib()