770 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));  in vcn_v1_0_dec_ring_insert_start()
773 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in vcn_v1_0_dec_ring_insert_start()
787 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in vcn_v1_0_dec_ring_insert_end()
805 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));  in vcn_v1_0_dec_ring_emit_fence()
808 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));  in vcn_v1_0_dec_ring_emit_fence()
811 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));  in vcn_v1_0_dec_ring_emit_fence()
814 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in vcn_v1_0_dec_ring_emit_fence()
818 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));  in vcn_v1_0_dec_ring_emit_fence()
821 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));  in vcn_v1_0_dec_ring_emit_fence()
824 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in vcn_v1_0_dec_ring_emit_fence()
837 	amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(HDP, 0, mmHDP_DEBUG0), 0));  in vcn_v1_0_dec_ring_emit_hdp_invalidate()
854 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));  in vcn_v1_0_dec_ring_emit_ib()
858 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));  in vcn_v1_0_dec_ring_emit_ib()
861 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));  in vcn_v1_0_dec_ring_emit_ib()
864 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));  in vcn_v1_0_dec_ring_emit_ib()
872 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));  in vcn_v1_0_dec_vm_reg_write()
875 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));  in vcn_v1_0_dec_vm_reg_write()
878 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in vcn_v1_0_dec_vm_reg_write()
886 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));  in vcn_v1_0_dec_vm_reg_wait()
889 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));  in vcn_v1_0_dec_vm_reg_wait()
892 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));  in vcn_v1_0_dec_vm_reg_wait()
895 		PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));  in vcn_v1_0_dec_vm_reg_wait()
1125 	.nop = PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0),