Lines Matching refs:REG_WRITE
134 REG_WRITE(pipeconf_reg, BIT(31)); in dsi_set_pipe_plane_enable_state()
141 REG_WRITE(dspcntr_reg, dspcntr); in dsi_set_pipe_plane_enable_state()
157 REG_WRITE(dspbase_reg, REG_READ(dspbase_reg)); in dsi_set_pipe_plane_enable_state()
243 REG_WRITE(gen_data_reg, 0x00008036); in mdfld_dsi_tpo_ic_init()
245 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x02 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
249 REG_WRITE(gen_data_reg, 0x005a5af0); in mdfld_dsi_tpo_ic_init()
251 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
255 REG_WRITE(gen_data_reg, 0x005a5af1); in mdfld_dsi_tpo_ic_init()
257 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
261 REG_WRITE(gen_data_reg, 0x005a5afc); in mdfld_dsi_tpo_ic_init()
263 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
267 REG_WRITE(gen_data_reg, 0x770000b7); in mdfld_dsi_tpo_ic_init()
269 REG_WRITE(gen_data_reg, 0x00000044); in mdfld_dsi_tpo_ic_init()
271 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x05 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
275 REG_WRITE(gen_data_reg, 0x000a0ab6); in mdfld_dsi_tpo_ic_init()
277 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
281 REG_WRITE(gen_data_reg, 0x081010f2); in mdfld_dsi_tpo_ic_init()
283 REG_WRITE(gen_data_reg, 0x4a070708); in mdfld_dsi_tpo_ic_init()
285 REG_WRITE(gen_data_reg, 0x000000c5); in mdfld_dsi_tpo_ic_init()
287 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x09 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
291 REG_WRITE(gen_data_reg, 0x024003f8); in mdfld_dsi_tpo_ic_init()
293 REG_WRITE(gen_data_reg, 0x01030a04); in mdfld_dsi_tpo_ic_init()
295 REG_WRITE(gen_data_reg, 0x0e020220); in mdfld_dsi_tpo_ic_init()
297 REG_WRITE(gen_data_reg, 0x00000004); in mdfld_dsi_tpo_ic_init()
299 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x0d << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
303 REG_WRITE(gen_data_reg, 0x398fc3e2); in mdfld_dsi_tpo_ic_init()
305 REG_WRITE(gen_data_reg, 0x0000916f); in mdfld_dsi_tpo_ic_init()
307 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x06 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
311 REG_WRITE(gen_data_reg, 0x000000b0); in mdfld_dsi_tpo_ic_init()
313 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x02 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
317 REG_WRITE(gen_data_reg, 0x240242f4); in mdfld_dsi_tpo_ic_init()
319 REG_WRITE(gen_data_reg, 0x78ee2002); in mdfld_dsi_tpo_ic_init()
321 REG_WRITE(gen_data_reg, 0x2a071050); in mdfld_dsi_tpo_ic_init()
323 REG_WRITE(gen_data_reg, 0x507fee10); in mdfld_dsi_tpo_ic_init()
325 REG_WRITE(gen_data_reg, 0x10300710); in mdfld_dsi_tpo_ic_init()
327 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x14 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
331 REG_WRITE(gen_data_reg, 0x19fe07ba); in mdfld_dsi_tpo_ic_init()
333 REG_WRITE(gen_data_reg, 0x101c0a31); in mdfld_dsi_tpo_ic_init()
335 REG_WRITE(gen_data_reg, 0x00000010); in mdfld_dsi_tpo_ic_init()
337 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x09 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
341 REG_WRITE(gen_data_reg, 0x28ff07bb); in mdfld_dsi_tpo_ic_init()
343 REG_WRITE(gen_data_reg, 0x24280a31); in mdfld_dsi_tpo_ic_init()
345 REG_WRITE(gen_data_reg, 0x00000034); in mdfld_dsi_tpo_ic_init()
347 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x09 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
351 REG_WRITE(gen_data_reg, 0x535d05fb); in mdfld_dsi_tpo_ic_init()
353 REG_WRITE(gen_data_reg, 0x1b1a2130); in mdfld_dsi_tpo_ic_init()
355 REG_WRITE(gen_data_reg, 0x221e180e); in mdfld_dsi_tpo_ic_init()
357 REG_WRITE(gen_data_reg, 0x131d2120); in mdfld_dsi_tpo_ic_init()
359 REG_WRITE(gen_data_reg, 0x535d0508); in mdfld_dsi_tpo_ic_init()
361 REG_WRITE(gen_data_reg, 0x1c1a2131); in mdfld_dsi_tpo_ic_init()
363 REG_WRITE(gen_data_reg, 0x231f160d); in mdfld_dsi_tpo_ic_init()
365 REG_WRITE(gen_data_reg, 0x111b2220); in mdfld_dsi_tpo_ic_init()
367 REG_WRITE(gen_data_reg, 0x535c2008); in mdfld_dsi_tpo_ic_init()
369 REG_WRITE(gen_data_reg, 0x1f1d2433); in mdfld_dsi_tpo_ic_init()
371 REG_WRITE(gen_data_reg, 0x2c251a10); in mdfld_dsi_tpo_ic_init()
373 REG_WRITE(gen_data_reg, 0x2c34372d); in mdfld_dsi_tpo_ic_init()
375 REG_WRITE(gen_data_reg, 0x00000023); in mdfld_dsi_tpo_ic_init()
377 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x31 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
381 REG_WRITE(gen_data_reg, 0x525c0bfa); in mdfld_dsi_tpo_ic_init()
383 REG_WRITE(gen_data_reg, 0x1c1c232f); in mdfld_dsi_tpo_ic_init()
385 REG_WRITE(gen_data_reg, 0x2623190e); in mdfld_dsi_tpo_ic_init()
387 REG_WRITE(gen_data_reg, 0x18212625); in mdfld_dsi_tpo_ic_init()
389 REG_WRITE(gen_data_reg, 0x545d0d0e); in mdfld_dsi_tpo_ic_init()
391 REG_WRITE(gen_data_reg, 0x1e1d2333); in mdfld_dsi_tpo_ic_init()
393 REG_WRITE(gen_data_reg, 0x26231a10); in mdfld_dsi_tpo_ic_init()
395 REG_WRITE(gen_data_reg, 0x1a222725); in mdfld_dsi_tpo_ic_init()
397 REG_WRITE(gen_data_reg, 0x545d280f); in mdfld_dsi_tpo_ic_init()
399 REG_WRITE(gen_data_reg, 0x21202635); in mdfld_dsi_tpo_ic_init()
401 REG_WRITE(gen_data_reg, 0x31292013); in mdfld_dsi_tpo_ic_init()
403 REG_WRITE(gen_data_reg, 0x31393d33); in mdfld_dsi_tpo_ic_init()
405 REG_WRITE(gen_data_reg, 0x00000029); in mdfld_dsi_tpo_ic_init()
407 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x31 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
411 REG_WRITE(gen_data_reg, 0x000100f7); in mdfld_dsi_tpo_ic_init()
413 REG_WRITE(gen_ctrl_reg, gen_ctrl_val | (0x03 << WORD_COUNTS_POS)); in mdfld_dsi_tpo_ic_init()
479 REG_WRITE(MIPI_CTRL_REG(pipe), 0x00000018); in mdfld_dsi_dpi_controller_init()
482 REG_WRITE(MIPI_INTR_EN_REG(pipe), 0xffffffff); in mdfld_dsi_dpi_controller_init()
502 REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), val); in mdfld_dsi_dpi_controller_init()
504 REG_WRITE(MIPI_HS_TX_TIMEOUT_REG(pipe), in mdfld_dsi_dpi_controller_init()
507 REG_WRITE(MIPI_LP_RX_TIMEOUT_REG(pipe), in mdfld_dsi_dpi_controller_init()
511 REG_WRITE(MIPI_TURN_AROUND_TIMEOUT_REG(pipe), in mdfld_dsi_dpi_controller_init()
515 REG_WRITE(MIPI_DEVICE_RESET_TIMER_REG(pipe), in mdfld_dsi_dpi_controller_init()
518 REG_WRITE(MIPI_DPI_RESOLUTION_REG(pipe), in mdfld_dsi_dpi_controller_init()
525 REG_WRITE(MIPI_HSYNC_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
527 REG_WRITE(MIPI_HBP_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
529 REG_WRITE(MIPI_HFP_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
531 REG_WRITE(MIPI_HACTIVE_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
533 REG_WRITE(MIPI_VSYNC_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
535 REG_WRITE(MIPI_VBP_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
537 REG_WRITE(MIPI_VFP_COUNT_REG(pipe), in mdfld_dsi_dpi_controller_init()
540 REG_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe), 0x46); in mdfld_dsi_dpi_controller_init()
543 REG_WRITE(MIPI_INIT_COUNT_REG(pipe), 0x000007d0); in mdfld_dsi_dpi_controller_init()
547 REG_WRITE(MIPI_VIDEO_MODE_FORMAT_REG(pipe), val); in mdfld_dsi_dpi_controller_init()
549 REG_WRITE(MIPI_EOT_DISABLE_REG(pipe), 0x00000000); in mdfld_dsi_dpi_controller_init()
551 REG_WRITE(MIPI_LP_BYTECLK_REG(pipe), 0x00000004); in mdfld_dsi_dpi_controller_init()
555 REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x2A0c6008); in mdfld_dsi_dpi_controller_init()
557 REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x150c3408); in mdfld_dsi_dpi_controller_init()
559 REG_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe), (0xa << 16) | 0x14); in mdfld_dsi_dpi_controller_init()
574 REG_WRITE(MIPI_INTR_STAT_REG(pipe), in mdfld_dsi_dpi_turn_on()
578 REG_WRITE(MIPI_DPI_CONTROL_REG(pipe), DSI_DPI_CTRL_HS_TURN_ON); in mdfld_dsi_dpi_turn_on()
584 REG_WRITE(MIPI_INTR_STAT_REG(pipe), in mdfld_dsi_dpi_turn_on()
613 REG_WRITE(MIPI_INTR_STAT_REG(pipe), in mdfld_dsi_dpi_shut_down()
619 REG_WRITE(MIPI_DPI_CONTROL_REG(pipe), DSI_DPI_CTRL_HS_SHUTDOWN); in mdfld_dsi_dpi_shut_down()
655 REG_WRITE(MIPI_PORT_CONTROL(pipe), in mdfld_dsi_dpi_set_power()
672 REG_WRITE(MIPI_PORT_CONTROL(pipe), in mdfld_dsi_dpi_set_power()
727 REG_WRITE(MIPI_CTRL_REG(pipe), 0x00000018); in mipi_set_properties()
728 REG_WRITE(MIPI_INTR_EN_REG(pipe), 0xffffffff); in mipi_set_properties()
729 REG_WRITE(MIPI_HS_TX_TIMEOUT_REG(pipe), 0xffffff); in mipi_set_properties()
730 REG_WRITE(MIPI_LP_RX_TIMEOUT_REG(pipe), 0xffffff); in mipi_set_properties()
731 REG_WRITE(MIPI_TURN_AROUND_TIMEOUT_REG(pipe), 0x14); in mipi_set_properties()
732 REG_WRITE(MIPI_DEVICE_RESET_TIMER_REG(pipe), 0xff); in mipi_set_properties()
733 REG_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT_REG(pipe), 0x25); in mipi_set_properties()
734 REG_WRITE(MIPI_INIT_COUNT_REG(pipe), 0xf0); in mipi_set_properties()
735 REG_WRITE(MIPI_EOT_DISABLE_REG(pipe), 0x00000000); in mipi_set_properties()
736 REG_WRITE(MIPI_LP_BYTECLK_REG(pipe), 0x00000004); in mipi_set_properties()
737 REG_WRITE(MIPI_DBI_BW_CTRL_REG(pipe), 0x00000820); in mipi_set_properties()
738 REG_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT_REG(pipe), (0xa << 16) | 0x14); in mipi_set_properties()
752 REG_WRITE(MIPI_DPI_RESOLUTION_REG(pipe), in mdfld_mipi_set_video_timing()
754 REG_WRITE(MIPI_HSYNC_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
756 REG_WRITE(MIPI_HBP_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
758 REG_WRITE(MIPI_HFP_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
760 REG_WRITE(MIPI_HACTIVE_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
762 REG_WRITE(MIPI_VSYNC_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
764 REG_WRITE(MIPI_VBP_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
766 REG_WRITE(MIPI_VFP_COUNT_REG(pipe), in mdfld_mipi_set_video_timing()
776 REG_WRITE(MIPI_PORT_CONTROL(0), 0x00000002); in mdfld_mipi_config()
777 REG_WRITE(MIPI_PORT_CONTROL(2), 0x80000000); in mdfld_mipi_config()
779 REG_WRITE(MIPI_PORT_CONTROL(0), 0x80010000); in mdfld_mipi_config()
780 REG_WRITE(MIPI_PORT_CONTROL(2), 0x00); in mdfld_mipi_config()
783 REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x150A600F); in mdfld_mipi_config()
784 REG_WRITE(MIPI_VIDEO_MODE_FORMAT_REG(pipe), 0x0000000F); in mdfld_mipi_config()
787 REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), 0x00000200 | lane_count); in mdfld_mipi_config()
797 REG_WRITE(HTOTAL_A, ((mode->htotal - 1) << 16) | (mode->hdisplay - 1)); in mdfld_set_pipe_timing()
798 REG_WRITE(HBLANK_A, ((mode->htotal - 1) << 16) | (mode->hdisplay - 1)); in mdfld_set_pipe_timing()
799 REG_WRITE(HSYNC_A, in mdfld_set_pipe_timing()
802 REG_WRITE(VTOTAL_A, ((mode->vtotal - 1) << 16) | (mode->vdisplay - 1)); in mdfld_set_pipe_timing()
803 REG_WRITE(VBLANK_A, ((mode->vtotal - 1) << 16) | (mode->vdisplay - 1)); in mdfld_set_pipe_timing()
804 REG_WRITE(VSYNC_A, in mdfld_set_pipe_timing()
807 REG_WRITE(PIPEASRC, in mdfld_set_pipe_timing()
859 REG_WRITE(MRST_DPLL_A, 0x00); in mdfld_dsi_dpi_mode_set()
860 REG_WRITE(MRST_FPA0, 0xC1); in mdfld_dsi_dpi_mode_set()
861 REG_WRITE(MRST_DPLL_A, 0x00800000); in mdfld_dsi_dpi_mode_set()
863 REG_WRITE(MRST_DPLL_A, 0x80800000); in mdfld_dsi_dpi_mode_set()
869 REG_WRITE(MIPI_DPHY_PARAM_REG(pipe), 0x2A0c6008); in mdfld_dsi_dpi_mode_set()
875 REG_WRITE(DSPABASE, 0x00); in mdfld_dsi_dpi_mode_set()
876 REG_WRITE(DSPASIZE, in mdfld_dsi_dpi_mode_set()
879 REG_WRITE(DSPACNTR, 0x98000000); in mdfld_dsi_dpi_mode_set()
880 REG_WRITE(DSPASURF, 0x00); in mdfld_dsi_dpi_mode_set()
882 REG_WRITE(VGACNTRL, 0x80000000); in mdfld_dsi_dpi_mode_set()
883 REG_WRITE(DEVICE_READY_REG, 0x00000001); in mdfld_dsi_dpi_mode_set()
885 REG_WRITE(MIPI_PORT_CONTROL(pipe), 0x80810000); in mdfld_dsi_dpi_mode_set()
888 REG_WRITE(MIPI_PORT_CONTROL(pipe), mipi); in mdfld_dsi_dpi_mode_set()
907 REG_WRITE(pipeconf_reg, pipeconf); in mdfld_dsi_dpi_mode_set()
911 REG_WRITE(dspcntr_reg, dspcntr); in mdfld_dsi_dpi_mode_set()