Lines Matching refs:REG_WRITE
143 REG_WRITE(dspcntr_reg, dspcntr); in mdfld__intel_plane_set_alpha()
202 REG_WRITE(map->stride, fb->pitches[0]); in mdfld__intel_pipe_set_base()
221 REG_WRITE(map->cntr, dspcntr); in mdfld__intel_pipe_set_base()
225 REG_WRITE(map->linoff, offset); in mdfld__intel_pipe_set_base()
227 REG_WRITE(map->surf, start); in mdfld__intel_pipe_set_base()
255 REG_WRITE(map->cntr, in mdfld_disable_crtc()
258 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_disable_crtc()
269 REG_WRITE(map->conf, temp); in mdfld_disable_crtc()
282 REG_WRITE(map->dpll, temp); in mdfld_disable_crtc()
290 REG_WRITE(map->dpll, temp | MDFLD_PWR_GATE_EN); in mdfld_disable_crtc()
339 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
344 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
349 REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE); in mdfld_crtc_dpms()
367 REG_WRITE(map->cntr, in mdfld_crtc_dpms()
370 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_crtc_dpms()
376 REG_WRITE(map->conf, pipeconf); in mdfld_crtc_dpms()
385 REG_WRITE(map->status, REG_READ(map->status)); in mdfld_crtc_dpms()
393 REG_WRITE(map->cntr, in mdfld_crtc_dpms()
395 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_crtc_dpms()
397 REG_WRITE(0xb048, 1); in mdfld_crtc_dpms()
401 REG_WRITE(map->conf, temp); in mdfld_crtc_dpms()
403 REG_WRITE(MIPI_DEVICE_READY_REG(pipe), 0); in mdfld_crtc_dpms()
405 REG_WRITE(0xb004, REG_READ(0xb004)); in mdfld_crtc_dpms()
407 REG_WRITE(MIPI_DEVICE_READY_REG(pipe), 1); in mdfld_crtc_dpms()
409 REG_WRITE(map->cntr, in mdfld_crtc_dpms()
411 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_crtc_dpms()
413 REG_WRITE(0xb048, 2); in mdfld_crtc_dpms()
417 REG_WRITE(map->conf, temp); in mdfld_crtc_dpms()
438 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); in mdfld_crtc_dpms()
443 REG_WRITE(map->cntr, in mdfld_crtc_dpms()
446 REG_WRITE(map->base, REG_READ(map->base)); in mdfld_crtc_dpms()
455 REG_WRITE(map->conf, temp); in mdfld_crtc_dpms()
468 REG_WRITE(map->dpll, temp); in mdfld_crtc_dpms()
763 REG_WRITE(VGACNTRL, VGA_DISP_DISABLE); in mdfld_crtc_mode_set()
767 REG_WRITE(PFIT_CONTROL, 0); in mdfld_crtc_mode_set()
784 REG_WRITE(map->size, ((min(mode->crtc_vdisplay, adjusted_mode->crtc_vdisplay) - 1) << 16) in mdfld_crtc_mode_set()
787 REG_WRITE(map->src, ((mode->crtc_hdisplay - 1) << 16) in mdfld_crtc_mode_set()
790 REG_WRITE(map->size, in mdfld_crtc_mode_set()
793 REG_WRITE(map->src, in mdfld_crtc_mode_set()
798 REG_WRITE(map->pos, 0); in mdfld_crtc_mode_set()
816 REG_WRITE(map->htotal, (mode->crtc_hdisplay - 1) | in mdfld_crtc_mode_set()
818 REG_WRITE(map->vtotal, (mode->crtc_vdisplay - 1) | in mdfld_crtc_mode_set()
820 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - in mdfld_crtc_mode_set()
823 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - in mdfld_crtc_mode_set()
826 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - in mdfld_crtc_mode_set()
829 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - in mdfld_crtc_mode_set()
833 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | in mdfld_crtc_mode_set()
835 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | in mdfld_crtc_mode_set()
837 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | in mdfld_crtc_mode_set()
839 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in mdfld_crtc_mode_set()
841 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | in mdfld_crtc_mode_set()
843 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | in mdfld_crtc_mode_set()
929 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
937 REG_WRITE(map->fp0, 0); in mdfld_crtc_mode_set()
939 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
948 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
989 REG_WRITE(map->fp0, fp); in mdfld_crtc_mode_set()
990 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
995 REG_WRITE(map->dpll, dpll); in mdfld_crtc_mode_set()
1010 REG_WRITE(map->conf, dev_priv->pipeconf[pipe]); in mdfld_crtc_mode_set()
1014 REG_WRITE(map->cntr, dev_priv->dspcntr[pipe]); in mdfld_crtc_mode_set()