288 	REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);  in oaktrail_crtc_hdmi_mode_set()
293 		REG_WRITE(DPLL_CTRL, dpll | (DPLL_PWRDN | DPLL_RESET));  in oaktrail_crtc_hdmi_mode_set()
294 		REG_WRITE(DPLL_DIV_CTRL, 0x00000000);  in oaktrail_crtc_hdmi_mode_set()
295 		REG_WRITE(DPLL_STATUS, 0x1);  in oaktrail_crtc_hdmi_mode_set()
310 	REG_WRITE(DPLL_CTRL, 0x00000008);  in oaktrail_crtc_hdmi_mode_set()
311 	REG_WRITE(DPLL_DIV_CTRL, ((clock.nf << 6) | clock.nr));  in oaktrail_crtc_hdmi_mode_set()
312 	REG_WRITE(DPLL_ADJUST, ((clock.nf >> 14) - 1));  in oaktrail_crtc_hdmi_mode_set()
313 	REG_WRITE(DPLL_CTRL, (dpll | (clock.np << DPLL_PDIV_SHIFT) | DPLL_ENSTAT | DPLL_DITHEN));  in oaktrail_crtc_hdmi_mode_set()
314 	REG_WRITE(DPLL_UPDATE, 0x80000000);  in oaktrail_crtc_hdmi_mode_set()
315 	REG_WRITE(DPLL_CLK_ENABLE, 0x80050102);  in oaktrail_crtc_hdmi_mode_set()
326 	REG_WRITE(htot_reg, temp);  in oaktrail_crtc_hdmi_mode_set()
327 …REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end - …  in oaktrail_crtc_hdmi_mode_set()
328 …REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1) …  in oaktrail_crtc_hdmi_mode_set()
329 	REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << 16));  in oaktrail_crtc_hdmi_mode_set()
330 …REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end - …  in oaktrail_crtc_hdmi_mode_set()
331 …REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) …  in oaktrail_crtc_hdmi_mode_set()
332 	REG_WRITE(pipesrc_reg, ((mode->crtc_hdisplay - 1) << 16) |  (mode->crtc_vdisplay - 1));  in oaktrail_crtc_hdmi_mode_set()
334 …REG_WRITE(PCH_HTOTAL_B, (adjusted_mode->crtc_hdisplay - 1) | ((adjusted_mode->crtc_htotal - 1) << …  in oaktrail_crtc_hdmi_mode_set()
335 …REG_WRITE(PCH_HBLANK_B, (adjusted_mode->crtc_hblank_start - 1) | ((adjusted_mode->crtc_hblank_end …  in oaktrail_crtc_hdmi_mode_set()
336 …REG_WRITE(PCH_HSYNC_B, (adjusted_mode->crtc_hsync_start - 1) | ((adjusted_mode->crtc_hsync_end - 1…  in oaktrail_crtc_hdmi_mode_set()
337 …REG_WRITE(PCH_VTOTAL_B, (adjusted_mode->crtc_vdisplay - 1) | ((adjusted_mode->crtc_vtotal - 1) << …  in oaktrail_crtc_hdmi_mode_set()
338 …REG_WRITE(PCH_VBLANK_B, (adjusted_mode->crtc_vblank_start - 1) | ((adjusted_mode->crtc_vblank_end …  in oaktrail_crtc_hdmi_mode_set()
339 …REG_WRITE(PCH_VSYNC_B, (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1…  in oaktrail_crtc_hdmi_mode_set()
340 	REG_WRITE(PCH_PIPEBSRC, ((mode->crtc_hdisplay - 1) << 16) |  (mode->crtc_vdisplay - 1));  in oaktrail_crtc_hdmi_mode_set()
345 	REG_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1));  in oaktrail_crtc_hdmi_mode_set()
346 	REG_WRITE(dsppos_reg, 0);  in oaktrail_crtc_hdmi_mode_set()
364 	REG_WRITE(pipeconf_reg, pipeconf);  in oaktrail_crtc_hdmi_mode_set()
367 	REG_WRITE(PCH_PIPEBCONF, pipeconf);  in oaktrail_crtc_hdmi_mode_set()
371 	REG_WRITE(dspcntr_reg, dspcntr);  in oaktrail_crtc_hdmi_mode_set()
388 		REG_WRITE(VGACNTRL, 0x80000000);  in oaktrail_crtc_hdmi_dpms()
393 			REG_WRITE(DSPBCNTR, temp & ~DISPLAY_PLANE_ENABLE);  in oaktrail_crtc_hdmi_dpms()
396 			REG_WRITE(DSPBSURF, REG_READ(DSPBSURF));  in oaktrail_crtc_hdmi_dpms()
403 			REG_WRITE(PIPEBCONF, temp & ~PIPEACONF_ENABLE);  in oaktrail_crtc_hdmi_dpms()
410 			REG_WRITE(PCH_PIPEBCONF, temp & ~PIPEACONF_ENABLE);  in oaktrail_crtc_hdmi_dpms()
420 			REG_WRITE(DPLL_CTRL, temp | (DPLL_PWRDN | DPLL_RESET));  in oaktrail_crtc_hdmi_dpms()
421 			REG_WRITE(DPLL_STATUS, 0x1);  in oaktrail_crtc_hdmi_dpms()
434 			REG_WRITE(DPLL_CTRL, temp & ~(DPLL_PWRDN | DPLL_RESET));  in oaktrail_crtc_hdmi_dpms()
436 			REG_WRITE(DPLL_CLK_ENABLE, temp | DPLL_EN_DISP | DPLL_SEL_HDMI | DPLL_EN_HDMI);  in oaktrail_crtc_hdmi_dpms()
445 			REG_WRITE(PIPEBCONF, temp | PIPEACONF_ENABLE);  in oaktrail_crtc_hdmi_dpms()
452 			REG_WRITE(PCH_PIPEBCONF, temp | PIPEACONF_ENABLE);  in oaktrail_crtc_hdmi_dpms()
461 			REG_WRITE(DSPBCNTR, temp | DISPLAY_PLANE_ENABLE);  in oaktrail_crtc_hdmi_dpms()
463 			REG_WRITE(DSPBSURF, REG_READ(DSPBSURF));  in oaktrail_crtc_hdmi_dpms()
471 	REG_WRITE(DSPARB, 0x00003fbf);  in oaktrail_crtc_hdmi_dpms()
474 	REG_WRITE(0x70034, 0x3f880a0a);  in oaktrail_crtc_hdmi_dpms()
477 	REG_WRITE(0x70038, 0x0b060808);  in oaktrail_crtc_hdmi_dpms()
480 	REG_WRITE(0x70050, 0x08030404);  in oaktrail_crtc_hdmi_dpms()
483 	REG_WRITE(0x70054, 0x04040404);  in oaktrail_crtc_hdmi_dpms()
486 	REG_WRITE(0x70400, 0x4000);  in oaktrail_crtc_hdmi_dpms()