Lines Matching refs:REG_WRITE
219 REG_WRITE(PFIT_CONTROL, 0); in psb_intel_crtc_mode_set()
224 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
225 REG_WRITE(map->dpll, dpll & ~DPLL_VCO_ENABLE); in psb_intel_crtc_mode_set()
255 REG_WRITE(LVDS, lvds); in psb_intel_crtc_mode_set()
259 REG_WRITE(map->fp0, fp); in psb_intel_crtc_mode_set()
260 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
266 REG_WRITE(map->dpll, dpll); in psb_intel_crtc_mode_set()
272 REG_WRITE(map->htotal, (adjusted_mode->crtc_hdisplay - 1) | in psb_intel_crtc_mode_set()
274 REG_WRITE(map->hblank, (adjusted_mode->crtc_hblank_start - 1) | in psb_intel_crtc_mode_set()
276 REG_WRITE(map->hsync, (adjusted_mode->crtc_hsync_start - 1) | in psb_intel_crtc_mode_set()
278 REG_WRITE(map->vtotal, (adjusted_mode->crtc_vdisplay - 1) | in psb_intel_crtc_mode_set()
280 REG_WRITE(map->vblank, (adjusted_mode->crtc_vblank_start - 1) | in psb_intel_crtc_mode_set()
282 REG_WRITE(map->vsync, (adjusted_mode->crtc_vsync_start - 1) | in psb_intel_crtc_mode_set()
287 REG_WRITE(map->size, in psb_intel_crtc_mode_set()
289 REG_WRITE(map->pos, 0); in psb_intel_crtc_mode_set()
290 REG_WRITE(map->src, in psb_intel_crtc_mode_set()
292 REG_WRITE(map->conf, pipeconf); in psb_intel_crtc_mode_set()
297 REG_WRITE(map->cntr, dspcntr); in psb_intel_crtc_mode_set()
484 REG_WRITE(control[gma_crtc->pipe], 0); in psb_intel_cursor_init()
485 REG_WRITE(base[gma_crtc->pipe], 0); in psb_intel_cursor_init()