888 	i915_reg_t ctl, cfgcr1, cfgcr2;  member
902 		.cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
908 		.cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
914 		.cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
941 	I915_WRITE(regs[pll->id].cfgcr2, pll->state.hw_state.cfgcr2);  in skl_ddi_pll_enable()
943 	POSTING_READ(regs[pll->id].cfgcr2);  in skl_ddi_pll_enable()
1002 		hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);  in skl_ddi_pll_get_hw_state()
1291 	uint32_t ctrl1, cfgcr1, cfgcr2;  in skl_ddi_hdmi_pll_dividers()  local
1309 	cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |  in skl_ddi_hdmi_pll_dividers()
1320 	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;  in skl_ddi_hdmi_pll_dividers()
1414 		      hw_state->cfgcr2);  in skl_dump_hw_state()