111 		u32 val = I915_READ(reg);  in read_data()
265 	if (cmd == I915_READ(MIPI_DPI_CONTROL(port)))  in dpi_send_cmd()
362 		tmp = I915_READ(MIPI_CTRL(port));  in glk_dsi_enable_io()
367 	tmp = I915_READ(MIPI_CTRL(PORT_A));  in glk_dsi_enable_io()
373 		tmp = I915_READ(MIPI_CTRL(port));  in glk_dsi_enable_io()
374 		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))  in glk_dsi_enable_io()
391 		cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) &  in glk_dsi_enable_io()
414 	val = I915_READ(MIPI_CTRL(PORT_A));  in glk_dsi_device_ready()
419 		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) {  in glk_dsi_device_ready()
420 			val = I915_READ(MIPI_DEVICE_READY(port));  in glk_dsi_device_ready()
427 			val = I915_READ(MIPI_DEVICE_READY(port));  in glk_dsi_device_ready()
438 			val = I915_READ(MIPI_DEVICE_READY(port));  in glk_dsi_device_ready()
444 			val = I915_READ(MIPI_DEVICE_READY(port));  in glk_dsi_device_ready()
449 			val = I915_READ(MIPI_CTRL(port));  in glk_dsi_device_ready()
483 		val = I915_READ(BXT_MIPI_PORT_CTRL(port));  in bxt_dsi_device_ready()
490 		val = I915_READ(MIPI_DEVICE_READY(port));  in bxt_dsi_device_ready()
526 		val = I915_READ(MIPI_PORT_CTRL(PORT_A));  in vlv_dsi_device_ready()
559 		val = I915_READ(MIPI_DEVICE_READY(port));  in glk_dsi_enter_low_power_mode()
590 	tmp = I915_READ(MIPI_CTRL(PORT_A));  in glk_dsi_disable_mipi_io()
604 		tmp = I915_READ(MIPI_CTRL(port));  in glk_dsi_disable_mipi_io()
652 		val = I915_READ(port_ctrl);  in vlv_dsi_clear_device_ready()
673 				temp = I915_READ(MIPI_CTRL(port));  in intel_dsi_port_enable()
680 			temp = I915_READ(VLV_CHICKEN_3);  in intel_dsi_port_enable()
693 		temp = I915_READ(port_ctrl);  in intel_dsi_port_enable()
727 		temp = I915_READ(port_ctrl);  in intel_dsi_port_disable()
806 		val = I915_READ(BXT_P_CR_GT_DISP_PWRON);  in intel_dsi_pre_enable()
819 		val = I915_READ(DSPCLK_GATE_D);  in intel_dsi_pre_enable()
965 		val = I915_READ(BXT_P_CR_GT_DISP_PWRON);  in intel_dsi_post_disable()
975 		val = I915_READ(DSPCLK_GATE_D);  in intel_dsi_post_disable()
1022 		bool enabled = I915_READ(ctrl_reg) & DPI_ENABLE;  in intel_dsi_get_hw_state()
1031 			enabled = I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;  in intel_dsi_get_hw_state()
1035 			u32 tmp = I915_READ(MIPI_DSI_FUNC_PRG(port));  in intel_dsi_get_hw_state()
1042 		if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY))  in intel_dsi_get_hw_state()
1046 			u32 tmp = I915_READ(MIPI_CTRL(port));  in intel_dsi_get_hw_state()
1095 		if (I915_READ(BXT_MIPI_PORT_CTRL(port)) & DPI_ENABLE)  in bxt_dsi_get_pipe_config()
1099 	fmt = I915_READ(MIPI_DSI_FUNC_PRG(port)) & VID_MODE_FORMAT_MASK;  in bxt_dsi_get_pipe_config()
1107 				I915_READ(BXT_MIPI_TRANS_HACTIVE(port));  in bxt_dsi_get_pipe_config()
1109 				I915_READ(BXT_MIPI_TRANS_VACTIVE(port));  in bxt_dsi_get_pipe_config()
1111 				I915_READ(BXT_MIPI_TRANS_VTOTAL(port));  in bxt_dsi_get_pipe_config()
1114 	hfp = I915_READ(MIPI_HFP_COUNT(port));  in bxt_dsi_get_pipe_config()
1120 	hsync = I915_READ(MIPI_HSYNC_PADDING_COUNT(port));  in bxt_dsi_get_pipe_config()
1121 	hbp = I915_READ(MIPI_HBP_COUNT(port));  in bxt_dsi_get_pipe_config()
1138 	vfp = I915_READ(MIPI_VFP_COUNT(port));  in bxt_dsi_get_pipe_config()
1139 	vsync = I915_READ(MIPI_VSYNC_PADDING_COUNT(port));  in bxt_dsi_get_pipe_config()
1140 	vbp = I915_READ(MIPI_VBP_COUNT(port));  in bxt_dsi_get_pipe_config()
1402 			tmp = I915_READ(MIPI_CTRL(PORT_A));  in intel_dsi_prepare()
1408 			tmp = I915_READ(MIPI_CTRL(port));  in intel_dsi_prepare()
1415 			tmp = I915_READ(MIPI_CTRL(port));  in intel_dsi_prepare()
1581 			val = I915_READ(MIPI_DSI_FUNC_PRG(port));  in intel_dsi_unprepare()