Lines Matching refs:I915_READ
63 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); in gen9_init_clock_gating()
77 I915_READ(CHICKEN_PAR1_1) & ~SKL_RC_HASH_OUTSIDE); in gen9_init_clock_gating()
80 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); in gen9_init_clock_gating()
84 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); in gen9_init_clock_gating()
88 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | in gen9_init_clock_gating()
93 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | in gen9_init_clock_gating()
98 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) in gen9_init_clock_gating()
108 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
115 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
122 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | in bxt_init_clock_gating()
143 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | in glk_init_clock_gating()
148 u32 val = I915_READ(CHICKEN_MISC_2); in glk_init_clock_gating()
161 tmp = I915_READ(CLKCFG); in i915_pineview_get_mem_freq()
191 tmp = I915_READ(CSHRDDR3CTL); in i915_pineview_get_mem_freq()
371 was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; in _intel_set_memory_cxsr()
375 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; in _intel_set_memory_cxsr()
379 val = I915_READ(DSPFW3); in _intel_set_memory_cxsr()
388 was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; in _intel_set_memory_cxsr()
399 was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; in _intel_set_memory_cxsr()
499 dsparb = I915_READ(DSPARB); in vlv_get_fifo_size()
500 dsparb2 = I915_READ(DSPARB2); in vlv_get_fifo_size()
505 dsparb = I915_READ(DSPARB); in vlv_get_fifo_size()
506 dsparb2 = I915_READ(DSPARB2); in vlv_get_fifo_size()
511 dsparb2 = I915_READ(DSPARB2); in vlv_get_fifo_size()
512 dsparb3 = I915_READ(DSPARB3); in vlv_get_fifo_size()
529 uint32_t dsparb = I915_READ(DSPARB); in i9xx_get_fifo_size()
544 uint32_t dsparb = I915_READ(DSPARB); in i830_get_fifo_size()
560 uint32_t dsparb = I915_READ(DSPARB); in i845_get_fifo_size()
884 reg = I915_READ(DSPFW1); in pineview_update_wm()
894 reg = I915_READ(DSPFW3); in pineview_update_wm()
903 reg = I915_READ(DSPFW3); in pineview_update_wm()
912 reg = I915_READ(DSPFW3); in pineview_update_wm()
2409 fwater_lo = I915_READ(FW_BLC) & ~0xfff; in i845_update_wm()
2884 uint32_t sskpd = I915_READ(MCH_SSKPD); in intel_read_wm_latency()
2891 uint32_t mltr = I915_READ(MLTR_ILK); in intel_read_wm_latency()
3540 val = I915_READ(WM_MISC); in ilk_write_wm_values()
3547 val = I915_READ(DISP_ARB_CTL2); in ilk_write_wm_values()
3557 val = I915_READ(DISP_ARB_CTL); in ilk_write_wm_values()
3863 val = I915_READ(PLANE_BUF_CFG(pipe, plane_id)); in skl_ddb_get_hw_state()
3865 val = I915_READ(CUR_BUF_CFG(pipe)); in skl_ddb_get_hw_state()
5222 val = I915_READ(PLANE_WM(pipe, plane_id, level)); in skl_pipe_wm_get_hw_state()
5224 val = I915_READ(CUR_WM(pipe, level)); in skl_pipe_wm_get_hw_state()
5230 val = I915_READ(PLANE_WM_TRANS(pipe, plane_id)); in skl_pipe_wm_get_hw_state()
5232 val = I915_READ(CUR_WM_TRANS(pipe)); in skl_pipe_wm_get_hw_state()
5240 out->linetime = I915_READ(PIPE_WM_LINETIME(pipe)); in skl_pipe_wm_get_hw_state()
5287 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); in ilk_pipe_wm_get_hw_state()
5289 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); in ilk_pipe_wm_get_hw_state()
5334 tmp = I915_READ(DSPFW1); in g4x_read_wm_values()
5340 tmp = I915_READ(DSPFW2); in g4x_read_wm_values()
5348 tmp = I915_READ(DSPFW3); in g4x_read_wm_values()
5362 tmp = I915_READ(VLV_DDL(pipe)); in vlv_read_wm_values()
5374 tmp = I915_READ(DSPFW1); in vlv_read_wm_values()
5380 tmp = I915_READ(DSPFW2); in vlv_read_wm_values()
5385 tmp = I915_READ(DSPFW3); in vlv_read_wm_values()
5389 tmp = I915_READ(DSPFW7_CHV); in vlv_read_wm_values()
5393 tmp = I915_READ(DSPFW8_CHV); in vlv_read_wm_values()
5397 tmp = I915_READ(DSPFW9_CHV); in vlv_read_wm_values()
5401 tmp = I915_READ(DSPHOWM); in vlv_read_wm_values()
5413 tmp = I915_READ(DSPFW7); in vlv_read_wm_values()
5417 tmp = I915_READ(DSPHOWM); in vlv_read_wm_values()
5439 wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; in g4x_wm_get_hw_state()
5581 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; in vlv_wm_get_hw_state()
5725 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); in ilk_init_lp_watermarks()
5726 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); in ilk_init_lp_watermarks()
5727 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); in ilk_init_lp_watermarks()
5746 hw->wm_lp[0] = I915_READ(WM1_LP_ILK); in ilk_wm_get_hw_state()
5747 hw->wm_lp[1] = I915_READ(WM2_LP_ILK); in ilk_wm_get_hw_state()
5748 hw->wm_lp[2] = I915_READ(WM3_LP_ILK); in ilk_wm_get_hw_state()
5750 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); in ilk_wm_get_hw_state()
5752 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); in ilk_wm_get_hw_state()
5753 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); in ilk_wm_get_hw_state()
5757 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? in ilk_wm_get_hw_state()
5760 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? in ilk_wm_get_hw_state()
5764 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); in ilk_wm_get_hw_state()
5846 rgvmodectl = I915_READ(MEMMODECTL); in ironlake_enable_drps()
5849 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); in ironlake_enable_drps()
5850 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); in ironlake_enable_drps()
5868 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >> in ironlake_enable_drps()
5893 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) in ironlake_enable_drps()
5899 dev_priv->ips.last_count1 = I915_READ(DMIEC) + in ironlake_enable_drps()
5900 I915_READ(DDREC) + I915_READ(CSIEC); in ironlake_enable_drps()
5902 dev_priv->ips.last_count2 = I915_READ(GFXEC); in ironlake_enable_drps()
5917 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); in ironlake_disable_drps()
5919 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); in ironlake_disable_drps()
5921 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); in ironlake_disable_drps()
6340 rc_ctl = I915_READ(GEN6_RC_CONTROL); in bxt_check_bios_rc6_setup()
6341 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >> in bxt_check_bios_rc6_setup()
6349 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) { in bxt_check_bios_rc6_setup()
6358 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK; in bxt_check_bios_rc6_setup()
6366 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) && in bxt_check_bios_rc6_setup()
6367 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) && in bxt_check_bios_rc6_setup()
6368 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) && in bxt_check_bios_rc6_setup()
6369 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) { in bxt_check_bios_rc6_setup()
6374 if (!I915_READ(GEN8_PUSHBUS_CONTROL) || in bxt_check_bios_rc6_setup()
6375 !I915_READ(GEN8_PUSHBUS_ENABLE) || in bxt_check_bios_rc6_setup()
6376 !I915_READ(GEN8_PUSHBUS_SHIFT)) { in bxt_check_bios_rc6_setup()
6381 if (!I915_READ(GEN6_GFXPAUSE)) { in bxt_check_bios_rc6_setup()
6386 if (!I915_READ(GEN8_MISC_CTRL0)) { in bxt_check_bios_rc6_setup()
6438 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP); in gen6_init_rps_frequencies()
6443 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); in gen6_init_rps_frequencies()
6671 gtfifodbg = I915_READ(GTFIFODBG); in gen6_enable_rps()
6770 min_ring_freq = I915_READ(DCLK) & 0xf; in gen6_update_ring_freq()
6941 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; in valleyview_check_pctx()
6951 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; in cherryview_check_pctx()
6963 pcbr = I915_READ(VLV_PCBR); in cherryview_setup_pctx()
6973 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); in cherryview_setup_pctx()
6983 pcbr = I915_READ(VLV_PCBR); in valleyview_setup_pctx()
7016 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); in valleyview_setup_pctx()
7148 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV | in cherryview_enable_rps()
7184 pcbr = I915_READ(VLV_PCBR); in cherryview_enable_rps()
7239 gtfifodbg = I915_READ(GTFIFODBG); in valleyview_enable_rps()
7359 count1 = I915_READ(DMIEC); in __i915_chipset_val()
7360 count2 = I915_READ(DDREC); in __i915_chipset_val()
7361 count3 = I915_READ(CSIEC); in __i915_chipset_val()
7415 tsfs = I915_READ(TSFS); in i915_mch_val()
7462 count = I915_READ(GFXEC); in __i915_update_gfx_val()
7499 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq)); in __i915_gfx_val()
7737 u32 pxvidfreq = I915_READ(PXVFREQ(i)); in intel_init_emon()
7779 lcfuse = I915_READ(LCFUSE02); in intel_init_emon()
7786 return !I915_READ(GEN8_RC6_CTX_INFO); in i915_rc6_ctx_corrupted()
8138 I915_READ(DSPCNTR(pipe)) | in g4x_disable_trickle_feed()
8141 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); in g4x_disable_trickle_feed()
8172 (I915_READ(ILK_DISPLAY_CHICKEN2) | in ironlake_init_clock_gating()
8176 (I915_READ(DISP_ARB_CTL) | in ironlake_init_clock_gating()
8189 I915_READ(ILK_DISPLAY_CHICKEN1) | in ironlake_init_clock_gating()
8192 I915_READ(ILK_DISPLAY_CHICKEN2) | in ironlake_init_clock_gating()
8199 I915_READ(ILK_DISPLAY_CHICKEN2) | in ironlake_init_clock_gating()
8230 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | in cpt_init_clock_gating()
8236 val = I915_READ(TRANS_CHICKEN2(pipe)); in cpt_init_clock_gating()
8257 tmp = I915_READ(MCH_SSKPD); in gen6_check_mch_setup()
8270 I915_READ(ILK_DISPLAY_CHICKEN2) | in gen6_init_clock_gating()
8295 I915_READ(GEN6_UCGCTL1) | in gen6_init_clock_gating()
8340 I915_READ(ILK_DISPLAY_CHICKEN1) | in gen6_init_clock_gating()
8343 I915_READ(ILK_DISPLAY_CHICKEN2) | in gen6_init_clock_gating()
8346 I915_READ(ILK_DSPCLK_GATE_D) | in gen6_init_clock_gating()
8359 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); in gen7_setup_fixed_func_scheduler()
8383 I915_READ(SOUTH_DSPCLK_GATE_D) | in lpt_init_clock_gating()
8388 I915_READ(TRANS_CHICKEN1(PIPE_A)) | in lpt_init_clock_gating()
8395 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); in lpt_suspend_hw()
8410 misccpctl = I915_READ(GEN7_MISCCPCTL); in gen8_set_l3sqc_credits()
8413 val = I915_READ(GEN8_L3SQCREG1); in gen8_set_l3sqc_credits()
8434 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in kabylake_init_clock_gating()
8439 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | in kabylake_init_clock_gating()
8443 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | in kabylake_init_clock_gating()
8452 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) | in skylake_init_clock_gating()
8456 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | in skylake_init_clock_gating()
8465 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); in broadwell_init_clock_gating()
8469 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); in broadwell_init_clock_gating()
8474 I915_READ(CHICKEN_PIPESL_1(pipe)) | in broadwell_init_clock_gating()
8481 I915_READ(GEN7_FF_THREAD_MODE) & in broadwell_init_clock_gating()
8488 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in broadwell_init_clock_gating()
8502 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1) in broadwell_init_clock_gating()
8513 I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); in broadwell_init_clock_gating()
8525 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | in haswell_init_clock_gating()
8530 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); in haswell_init_clock_gating()
8559 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); in haswell_init_clock_gating()
8608 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & in ivybridge_init_clock_gating()
8620 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | in ivybridge_init_clock_gating()
8648 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); in ivybridge_init_clock_gating()
8680 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & in valleyview_init_clock_gating()
8689 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | in valleyview_init_clock_gating()
8705 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); in valleyview_init_clock_gating()
8744 I915_READ(GEN7_FF_THREAD_MODE) & in cherryview_init_clock_gating()
8752 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | in cherryview_init_clock_gating()
8756 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in cherryview_init_clock_gating()
8830 u32 dstate = I915_READ(D_STATE); in gen3_init_clock_gating()
9401 time_hw = I915_READ(reg); in intel_rc6_residency_us()
9406 time_hw = I915_READ(reg); in intel_rc6_residency_us()