322 	ret = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)) & req_mask ? 1 : 0;  in hsw_power_well_requesters()
323 	ret |= I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & req_mask ? 2 : 0;  in hsw_power_well_requesters()
324 	ret |= I915_READ(HSW_PWR_WELL_CTL_KVMR) & req_mask ? 4 : 0;  in hsw_power_well_requesters()
325 	ret |= I915_READ(HSW_PWR_WELL_CTL_DEBUG(id)) & req_mask ? 8 : 0;  in hsw_power_well_requesters()
346 	wait_for((disabled = !(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) &  in hsw_wait_for_power_well_disable()
387 	val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));  in hsw_power_well_enable()
406 	val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));  in hsw_power_well_disable()
423 	return (I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & mask) == mask;  in hsw_power_well_enabled()
430 	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),  in assert_can_enable_dc9()
432 	WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,  in assert_can_enable_dc9()
434 	WARN_ONCE(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) &  in assert_can_enable_dc9()
453 	WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,  in assert_can_disable_dc9()
480 		v = I915_READ(DC_STATE_EN);  in gen9_write_dc_state()
519 	val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);  in gen9_sanitize_dc_state()
534 	val = I915_READ(DC_STATE_EN);  in gen9_set_dc_state()
575 	WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),  in assert_csr_loaded()
577 	WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");  in assert_csr_loaded()
578 	WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");  in assert_csr_loaded()
588 	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),  in assert_can_enable_dc5()
603 		I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |  in gen9_enable_dc5()
611 	WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,  in assert_can_enable_dc6()
613 	WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),  in assert_can_enable_dc6()
627 		I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) |  in skl_enable_dc6()
645 	u32 bios_req = I915_READ(HSW_PWR_WELL_CTL_BIOS(id));  in hsw_power_well_sync_hw()
649 		u32 drv_req = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id));  in hsw_power_well_sync_hw()
697 	return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;  in gen9_dc_off_power_well_enabled()
702 	u32 tmp = I915_READ(DBUF_CTL);  in gen9_assert_dbuf_enabled()
756 	if ((I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)  in i830_pipes_power_well_enable()
758 	if ((I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)  in i830_pipes_power_well_enable()
772 	return I915_READ(PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&  in i830_pipes_power_well_enabled()
773 		I915_READ(PIPECONF(PIPE_B)) & PIPECONF_ENABLE;  in i830_pipes_power_well_enabled()
879 	val = I915_READ(DSPCLK_GATE_D);  in vlv_init_display_clock_gating()
910 		u32 val = I915_READ(DPLL(pipe));  in vlv_display_power_well_init()
1002 	I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);  in vlv_dpio_cmn_power_well_enable()
1016 	I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);  in vlv_dpio_cmn_power_well_disable()
1096 		    (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)  in assert_chv_phy_status()
1145 			  I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask,  in assert_chv_phy_status()
2576 	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);  in gen9_dbuf_enable()
2581 	if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))  in gen9_dbuf_enable()
2587 	I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);  in gen9_dbuf_disable()
2592 	if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)  in gen9_dbuf_disable()
2606 	val = I915_READ(HSW_NDE_RSTWRN_OPT);  in skl_display_core_init()
2673 	val = I915_READ(HSW_NDE_RSTWRN_OPT);  in bxt_display_core_init()
2751 	val = I915_READ(HSW_NDE_RSTWRN_OPT);  in cnl_display_core_init()
2756 	val = I915_READ(CHICKEN_MISC_2);  in cnl_display_core_init()
2760 	val = I915_READ(CNL_PORT_COMP_DW3);  in cnl_display_core_init()
2765 	val = I915_READ(CNL_PORT_COMP_DW1);  in cnl_display_core_init()
2773 	val = I915_READ(CNL_PORT_COMP_DW0);  in cnl_display_core_init()
2778 	val = I915_READ(CNL_PORT_CL1CM_DW5);  in cnl_display_core_init()
2833 	val = I915_READ(CHICKEN_MISC_2);  in cnl_display_core_uninit()
2867 		uint32_t status = I915_READ(DPLL(PIPE_A));  in chv_phy_control_init()
2898 		uint32_t status = I915_READ(DPIO_PHY_STATUS);  in chv_phy_control_init()
2935 	    I915_READ(DPIO_CTL) & DPIO_CMNRST)  in vlv_cmnlane_wa()