52 	const u32 soff = nv50_ior_base(sor);  in g94_sor_dp_audio_sym()  local
53 	nvkm_mask(device, 0x61c1e8 + soff, 0x0000ffff, h);  in g94_sor_dp_audio_sym()
54 	nvkm_mask(device, 0x61c1ec + soff, 0x00ffffff, v);  in g94_sor_dp_audio_sym()
87 	const u32 soff = nv50_ior_base(sor);  in g94_sor_dp_power()  local
95 	nvkm_mask(device, 0x61c034 + soff, 0x80000000, 0x80000000);  in g94_sor_dp_power()
97 		if (!(nvkm_rd32(device, 0x61c034 + soff) & 0x80000000))  in g94_sor_dp_power()
106 	const u32 soff = nv50_ior_base(sor);  in g94_sor_dp_links()  local
117 	nvkm_mask(device, 0x614300 + soff, 0x000c0000, clksor);  in g94_sor_dp_links()
126 	const u32 soff = nv50_ior_base(sor);  in g94_sor_war_needed()  local
128 		switch (nvkm_rd32(device, 0x614300 + soff) & 0x00030000) {  in g94_sor_war_needed()
172 	const u32 soff = nv50_ior_base(sor);  in g94_sor_war_3()  local
178 	sorpwr = nvkm_rd32(device, 0x61c004 + soff);  in g94_sor_war_3()
180 		u32 seqctl = nvkm_rd32(device, 0x61c030 + soff);  in g94_sor_war_3()
184 		nvkm_wr32(device, 0x61c040 + soff + pd_pc * 4, 0x1f008000);  in g94_sor_war_3()
187 			if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000))  in g94_sor_war_3()
190 		nvkm_mask(device, 0x61c004 + soff, 0x80000001, 0x80000000);  in g94_sor_war_3()
192 			if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000))  in g94_sor_war_3()
196 		nvkm_wr32(device, 0x61c040 + soff + pd_pc * 4, 0x00002000);  in g94_sor_war_3()
197 		nvkm_wr32(device, 0x61c040 + soff + pu_pc * 4, 0x1f000000);  in g94_sor_war_3()
200 	nvkm_mask(device, 0x61c10c + soff, 0x00000001, 0x00000000);  in g94_sor_war_3()
201 	nvkm_mask(device, 0x614300 + soff, 0x03000000, 0x00000000);  in g94_sor_war_3()
204 		nvkm_mask(device, 0x61c004 + soff, 0x80000001, 0x80000001);  in g94_sor_war_3()
214 	const u32 soff = nv50_ior_base(sor);  in g94_sor_war_2()  local
220 	nvkm_mask(device, 0x614300 + soff, 0x03000000, 0x03000000);  in g94_sor_war_2()
221 	nvkm_mask(device, 0x61c10c + soff, 0x00000001, 0x00000001);  in g94_sor_war_2()
223 	nvkm_mask(device, 0x61c00c + soff, 0x0f000000, 0x00000000);  in g94_sor_war_2()
224 	nvkm_mask(device, 0x61c008 + soff, 0xff000000, 0x14000000);  in g94_sor_war_2()
226 	nvkm_mask(device, 0x61c008 + soff, 0xff000000, 0x00000000);  in g94_sor_war_2()
227 	nvkm_mask(device, 0x61c00c + soff, 0x0f000000, 0x01000000);  in g94_sor_war_2()
229 	if (nvkm_rd32(device, 0x61c004 + soff) & 0x00000001) {  in g94_sor_war_2()
230 		u32 seqctl = nvkm_rd32(device, 0x61c030 + soff);  in g94_sor_war_2()
232 		nvkm_wr32(device, 0x61c040 + soff + pu_pc * 4, 0x1f008000);  in g94_sor_war_2()