Lines Matching refs:device
52 struct nvkm_device *device = fifo->base.engine.subdev.device; in nv04_fifo_pause() local
58 nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000000); in nv04_fifo_pause()
59 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000000); in nv04_fifo_pause()
70 nvkm_msec(device, 2000, in nv04_fifo_pause()
71 u32 tmp = nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0); in nv04_fifo_pause()
76 if (nvkm_rd32(device, NV04_PFIFO_CACHE1_PULL0) & in nv04_fifo_pause()
78 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); in nv04_fifo_pause()
80 nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0x00000000); in nv04_fifo_pause()
88 struct nvkm_device *device = fifo->base.engine.subdev.device; in nv04_fifo_start() local
91 nvkm_mask(device, NV04_PFIFO_CACHE1_PULL0, 0x00000001, 0x00000001); in nv04_fifo_start()
92 nvkm_wr32(device, NV03_PFIFO_CACHES, 0x00000001); in nv04_fifo_start()
108 nv04_fifo_swmthd(struct nvkm_device *device, u32 chid, u32 addr, u32 data) in nv04_fifo_swmthd() argument
110 struct nvkm_sw *sw = device->sw; in nv04_fifo_swmthd()
114 u32 engine = nvkm_rd32(device, 0x003280); in nv04_fifo_swmthd()
119 nvkm_wr32(device, 0x003280, (engine &= ~mask)); in nv04_fifo_swmthd()
121 data = nvkm_rd32(device, 0x003258) & 0x0000ffff; in nv04_fifo_swmthd()
138 struct nvkm_device *device = subdev->device; in nv04_fifo_cache_error() local
141 u32 pull0 = nvkm_rd32(device, 0x003250); in nv04_fifo_cache_error()
152 if (device->card_type < NV_40) { in nv04_fifo_cache_error()
153 mthd = nvkm_rd32(device, NV04_PFIFO_CACHE1_METHOD(ptr)); in nv04_fifo_cache_error()
154 data = nvkm_rd32(device, NV04_PFIFO_CACHE1_DATA(ptr)); in nv04_fifo_cache_error()
156 mthd = nvkm_rd32(device, NV40_PFIFO_CACHE1_METHOD(ptr)); in nv04_fifo_cache_error()
157 data = nvkm_rd32(device, NV40_PFIFO_CACHE1_DATA(ptr)); in nv04_fifo_cache_error()
161 !nv04_fifo_swmthd(device, chid, mthd, data)) { in nv04_fifo_cache_error()
170 nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH, 0); in nv04_fifo_cache_error()
171 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_CACHE_ERROR); in nv04_fifo_cache_error()
173 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, in nv04_fifo_cache_error()
174 nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH0) & ~1); in nv04_fifo_cache_error()
175 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4); in nv04_fifo_cache_error()
176 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, in nv04_fifo_cache_error()
177 nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH0) | 1); in nv04_fifo_cache_error()
178 nvkm_wr32(device, NV04_PFIFO_CACHE1_HASH, 0); in nv04_fifo_cache_error()
180 nvkm_wr32(device, NV04_PFIFO_CACHE1_DMA_PUSH, in nv04_fifo_cache_error()
181 nvkm_rd32(device, NV04_PFIFO_CACHE1_DMA_PUSH) | 1); in nv04_fifo_cache_error()
182 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_cache_error()
189 struct nvkm_device *device = subdev->device; in nv04_fifo_dma_pusher() local
190 u32 dma_get = nvkm_rd32(device, 0x003244); in nv04_fifo_dma_pusher()
191 u32 dma_put = nvkm_rd32(device, 0x003240); in nv04_fifo_dma_pusher()
192 u32 push = nvkm_rd32(device, 0x003220); in nv04_fifo_dma_pusher()
193 u32 state = nvkm_rd32(device, 0x003228); in nv04_fifo_dma_pusher()
200 if (device->card_type == NV_50) { in nv04_fifo_dma_pusher()
201 u32 ho_get = nvkm_rd32(device, 0x003328); in nv04_fifo_dma_pusher()
202 u32 ho_put = nvkm_rd32(device, 0x003320); in nv04_fifo_dma_pusher()
203 u32 ib_get = nvkm_rd32(device, 0x003334); in nv04_fifo_dma_pusher()
204 u32 ib_put = nvkm_rd32(device, 0x003330); in nv04_fifo_dma_pusher()
214 nvkm_wr32(device, 0x003364, 0x00000000); in nv04_fifo_dma_pusher()
216 nvkm_wr32(device, 0x003244, dma_put); in nv04_fifo_dma_pusher()
217 nvkm_wr32(device, 0x003328, ho_put); in nv04_fifo_dma_pusher()
220 nvkm_wr32(device, 0x003334, ib_put); in nv04_fifo_dma_pusher()
228 nvkm_wr32(device, 0x003244, dma_put); in nv04_fifo_dma_pusher()
232 nvkm_wr32(device, 0x003228, 0x00000000); in nv04_fifo_dma_pusher()
233 nvkm_wr32(device, 0x003220, 0x00000001); in nv04_fifo_dma_pusher()
234 nvkm_wr32(device, 0x002100, NV_PFIFO_INTR_DMA_PUSHER); in nv04_fifo_dma_pusher()
242 struct nvkm_device *device = subdev->device; in nv04_fifo_intr() local
243 u32 mask = nvkm_rd32(device, NV03_PFIFO_INTR_EN_0); in nv04_fifo_intr()
244 u32 stat = nvkm_rd32(device, NV03_PFIFO_INTR_0) & mask; in nv04_fifo_intr()
247 reassign = nvkm_rd32(device, NV03_PFIFO_CACHES) & 1; in nv04_fifo_intr()
248 nvkm_wr32(device, NV03_PFIFO_CACHES, 0); in nv04_fifo_intr()
250 chid = nvkm_rd32(device, NV03_PFIFO_CACHE1_PUSH1) & (fifo->base.nr - 1); in nv04_fifo_intr()
251 get = nvkm_rd32(device, NV03_PFIFO_CACHE1_GET); in nv04_fifo_intr()
265 nvkm_wr32(device, NV03_PFIFO_INTR_0, NV_PFIFO_INTR_SEMAPHORE); in nv04_fifo_intr()
267 sem = nvkm_rd32(device, NV10_PFIFO_CACHE1_SEMAPHORE); in nv04_fifo_intr()
268 nvkm_wr32(device, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1); in nv04_fifo_intr()
270 nvkm_wr32(device, NV03_PFIFO_CACHE1_GET, get + 4); in nv04_fifo_intr()
271 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_intr()
274 if (device->card_type == NV_50) { in nv04_fifo_intr()
277 nvkm_wr32(device, 0x002100, 0x00000010); in nv04_fifo_intr()
281 nvkm_wr32(device, 0x002100, 0x40000000); in nv04_fifo_intr()
289 nvkm_mask(device, NV03_PFIFO_INTR_EN_0, stat, 0x00000000); in nv04_fifo_intr()
290 nvkm_wr32(device, NV03_PFIFO_INTR_0, stat); in nv04_fifo_intr()
293 nvkm_wr32(device, NV03_PFIFO_CACHES, reassign); in nv04_fifo_intr()
300 struct nvkm_device *device = fifo->base.engine.subdev.device; in nv04_fifo_init() local
301 struct nvkm_instmem *imem = device->imem; in nv04_fifo_init()
306 nvkm_wr32(device, NV04_PFIFO_DELAY_0, 0x000000ff); in nv04_fifo_init()
307 nvkm_wr32(device, NV04_PFIFO_DMA_TIMESLICE, 0x0101ffff); in nv04_fifo_init()
309 nvkm_wr32(device, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | in nv04_fifo_init()
312 nvkm_wr32(device, NV03_PFIFO_RAMRO, nvkm_memory_addr(ramro) >> 8); in nv04_fifo_init()
313 nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8); in nv04_fifo_init()
315 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH1, fifo->base.nr - 1); in nv04_fifo_init()
317 nvkm_wr32(device, NV03_PFIFO_INTR_0, 0xffffffff); in nv04_fifo_init()
318 nvkm_wr32(device, NV03_PFIFO_INTR_EN_0, 0xffffffff); in nv04_fifo_init()
320 nvkm_wr32(device, NV03_PFIFO_CACHE1_PUSH0, 1); in nv04_fifo_init()
321 nvkm_wr32(device, NV04_PFIFO_CACHE1_PULL0, 1); in nv04_fifo_init()
322 nvkm_wr32(device, NV03_PFIFO_CACHES, 1); in nv04_fifo_init()
326 nv04_fifo_new_(const struct nvkm_fifo_func *func, struct nvkm_device *device, in nv04_fifo_new_() argument
338 ret = nvkm_fifo_ctor(func, device, index, nr, &fifo->base); in nv04_fifo_new_()
359 nv04_fifo_new(struct nvkm_device *device, int index, struct nvkm_fifo **pfifo) in nv04_fifo_new() argument
361 return nv04_fifo_new_(&nv04_fifo, device, index, 16, in nv04_fifo_new()