Lines Matching refs:rdev
39 void r420_pm_init_profile(struct radeon_device *rdev) in r420_pm_init_profile() argument
42 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
43 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
44 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
45 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
47 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
48 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0; in r420_pm_init_profile()
49 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
50 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
52 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
53 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1; in r420_pm_init_profile()
54 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
55 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
57 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
58 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
59 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
60 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
62 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
63 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
64 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
65 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
67 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
68 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
69 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
70 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
72 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0; in r420_pm_init_profile()
73 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index; in r420_pm_init_profile()
74 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0; in r420_pm_init_profile()
75 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0; in r420_pm_init_profile()
78 static void r420_set_reg_safe(struct radeon_device *rdev) in r420_set_reg_safe() argument
80 rdev->config.r300.reg_safe_bm = r420_reg_safe_bm; in r420_set_reg_safe()
81 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r420_reg_safe_bm); in r420_set_reg_safe()
84 void r420_pipes_init(struct radeon_device *rdev) in r420_pipes_init() argument
94 if (r100_gui_wait_for_idle(rdev)) { in r420_pipes_init()
102 if ((rdev->pdev->device == 0x5e4c) || in r420_pipes_init()
103 (rdev->pdev->device == 0x5e4f)) in r420_pipes_init()
106 rdev->num_gb_pipes = num_pipes; in r420_pipes_init()
129 if (r100_gui_wait_for_idle(rdev)) { in r420_pipes_init()
141 if (r100_gui_wait_for_idle(rdev)) { in r420_pipes_init()
145 if (rdev->family == CHIP_RV530) { in r420_pipes_init()
148 rdev->num_z_pipes = 2; in r420_pipes_init()
150 rdev->num_z_pipes = 1; in r420_pipes_init()
152 rdev->num_z_pipes = 1; in r420_pipes_init()
155 rdev->num_gb_pipes, rdev->num_z_pipes); in r420_pipes_init()
158 u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg) in r420_mc_rreg() argument
163 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in r420_mc_rreg()
166 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in r420_mc_rreg()
170 void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v) in r420_mc_wreg() argument
174 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in r420_mc_wreg()
178 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in r420_mc_wreg()
181 static void r420_debugfs(struct radeon_device *rdev) in r420_debugfs() argument
183 if (r100_debugfs_rbbm_init(rdev)) { in r420_debugfs()
186 if (r420_debugfs_pipes_info_init(rdev)) { in r420_debugfs()
191 static void r420_clock_resume(struct radeon_device *rdev) in r420_clock_resume() argument
196 radeon_atom_set_clock_gating(rdev, 1); in r420_clock_resume()
199 if (rdev->family == CHIP_R420) in r420_clock_resume()
204 static void r420_cp_errata_init(struct radeon_device *rdev) in r420_cp_errata_init() argument
207 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r420_cp_errata_init()
215 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); in r420_cp_errata_init()
216 r = radeon_ring_lock(rdev, ring, 8); in r420_cp_errata_init()
219 radeon_ring_write(ring, rdev->config.r300.resync_scratch); in r420_cp_errata_init()
221 radeon_ring_unlock_commit(rdev, ring, false); in r420_cp_errata_init()
224 static void r420_cp_errata_fini(struct radeon_device *rdev) in r420_cp_errata_fini() argument
227 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; in r420_cp_errata_fini()
232 r = radeon_ring_lock(rdev, ring, 8); in r420_cp_errata_fini()
236 radeon_ring_unlock_commit(rdev, ring, false); in r420_cp_errata_fini()
237 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); in r420_cp_errata_fini()
240 static int r420_startup(struct radeon_device *rdev) in r420_startup() argument
245 r100_set_common_regs(rdev); in r420_startup()
247 r300_mc_program(rdev); in r420_startup()
249 r420_clock_resume(rdev); in r420_startup()
252 if (rdev->flags & RADEON_IS_PCIE) { in r420_startup()
253 r = rv370_pcie_gart_enable(rdev); in r420_startup()
257 if (rdev->flags & RADEON_IS_PCI) { in r420_startup()
258 r = r100_pci_gart_enable(rdev); in r420_startup()
262 r420_pipes_init(rdev); in r420_startup()
265 r = radeon_wb_init(rdev); in r420_startup()
269 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in r420_startup()
271 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in r420_startup()
276 if (!rdev->irq.installed) { in r420_startup()
277 r = radeon_irq_kms_init(rdev); in r420_startup()
282 r100_irq_set(rdev); in r420_startup()
283 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in r420_startup()
285 r = r100_cp_init(rdev, 1024 * 1024); in r420_startup()
287 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); in r420_startup()
290 r420_cp_errata_init(rdev); in r420_startup()
292 r = radeon_ib_pool_init(rdev); in r420_startup()
294 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in r420_startup()
301 int r420_resume(struct radeon_device *rdev) in r420_resume() argument
306 if (rdev->flags & RADEON_IS_PCIE) in r420_resume()
307 rv370_pcie_gart_disable(rdev); in r420_resume()
308 if (rdev->flags & RADEON_IS_PCI) in r420_resume()
309 r100_pci_gart_disable(rdev); in r420_resume()
311 r420_clock_resume(rdev); in r420_resume()
313 if (radeon_asic_reset(rdev)) { in r420_resume()
314 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in r420_resume()
319 if (rdev->is_atom_bios) { in r420_resume()
320 atom_asic_init(rdev->mode_info.atom_context); in r420_resume()
322 radeon_combios_asic_init(rdev->ddev); in r420_resume()
325 r420_clock_resume(rdev); in r420_resume()
327 radeon_surface_init(rdev); in r420_resume()
329 rdev->accel_working = true; in r420_resume()
330 r = r420_startup(rdev); in r420_resume()
332 rdev->accel_working = false; in r420_resume()
337 int r420_suspend(struct radeon_device *rdev) in r420_suspend() argument
339 radeon_pm_suspend(rdev); in r420_suspend()
340 r420_cp_errata_fini(rdev); in r420_suspend()
341 r100_cp_disable(rdev); in r420_suspend()
342 radeon_wb_disable(rdev); in r420_suspend()
343 r100_irq_disable(rdev); in r420_suspend()
344 if (rdev->flags & RADEON_IS_PCIE) in r420_suspend()
345 rv370_pcie_gart_disable(rdev); in r420_suspend()
346 if (rdev->flags & RADEON_IS_PCI) in r420_suspend()
347 r100_pci_gart_disable(rdev); in r420_suspend()
351 void r420_fini(struct radeon_device *rdev) in r420_fini() argument
353 radeon_pm_fini(rdev); in r420_fini()
354 r100_cp_fini(rdev); in r420_fini()
355 radeon_wb_fini(rdev); in r420_fini()
356 radeon_ib_pool_fini(rdev); in r420_fini()
357 radeon_gem_fini(rdev); in r420_fini()
358 if (rdev->flags & RADEON_IS_PCIE) in r420_fini()
359 rv370_pcie_gart_fini(rdev); in r420_fini()
360 if (rdev->flags & RADEON_IS_PCI) in r420_fini()
361 r100_pci_gart_fini(rdev); in r420_fini()
362 radeon_agp_fini(rdev); in r420_fini()
363 radeon_irq_kms_fini(rdev); in r420_fini()
364 radeon_fence_driver_fini(rdev); in r420_fini()
365 radeon_bo_fini(rdev); in r420_fini()
366 if (rdev->is_atom_bios) { in r420_fini()
367 radeon_atombios_fini(rdev); in r420_fini()
369 radeon_combios_fini(rdev); in r420_fini()
371 kfree(rdev->bios); in r420_fini()
372 rdev->bios = NULL; in r420_fini()
375 int r420_init(struct radeon_device *rdev) in r420_init() argument
380 radeon_scratch_init(rdev); in r420_init()
382 radeon_surface_init(rdev); in r420_init()
385 r100_restore_sanity(rdev); in r420_init()
387 if (!radeon_get_bios(rdev)) { in r420_init()
388 if (ASIC_IS_AVIVO(rdev)) in r420_init()
391 if (rdev->is_atom_bios) { in r420_init()
392 r = radeon_atombios_init(rdev); in r420_init()
397 r = radeon_combios_init(rdev); in r420_init()
403 if (radeon_asic_reset(rdev)) { in r420_init()
404 dev_warn(rdev->dev, in r420_init()
410 if (radeon_boot_test_post_card(rdev) == false) in r420_init()
414 radeon_get_clock_info(rdev->ddev); in r420_init()
416 if (rdev->flags & RADEON_IS_AGP) { in r420_init()
417 r = radeon_agp_init(rdev); in r420_init()
419 radeon_agp_disable(rdev); in r420_init()
423 r300_mc_init(rdev); in r420_init()
424 r420_debugfs(rdev); in r420_init()
426 r = radeon_fence_driver_init(rdev); in r420_init()
431 r = radeon_bo_init(rdev); in r420_init()
435 if (rdev->family == CHIP_R420) in r420_init()
436 r100_enable_bm(rdev); in r420_init()
438 if (rdev->flags & RADEON_IS_PCIE) { in r420_init()
439 r = rv370_pcie_gart_init(rdev); in r420_init()
443 if (rdev->flags & RADEON_IS_PCI) { in r420_init()
444 r = r100_pci_gart_init(rdev); in r420_init()
448 r420_set_reg_safe(rdev); in r420_init()
451 radeon_pm_init(rdev); in r420_init()
453 rdev->accel_working = true; in r420_init()
454 r = r420_startup(rdev); in r420_init()
457 dev_err(rdev->dev, "Disabling GPU acceleration\n"); in r420_init()
458 r100_cp_fini(rdev); in r420_init()
459 radeon_wb_fini(rdev); in r420_init()
460 radeon_ib_pool_fini(rdev); in r420_init()
461 radeon_irq_kms_fini(rdev); in r420_init()
462 if (rdev->flags & RADEON_IS_PCIE) in r420_init()
463 rv370_pcie_gart_fini(rdev); in r420_init()
464 if (rdev->flags & RADEON_IS_PCI) in r420_init()
465 r100_pci_gart_fini(rdev); in r420_init()
466 radeon_agp_fini(rdev); in r420_init()
467 rdev->accel_working = false; in r420_init()
480 struct radeon_device *rdev = dev->dev_private; in r420_debugfs_pipes_info() local
497 int r420_debugfs_pipes_info_init(struct radeon_device *rdev) in r420_debugfs_pipes_info_init() argument
500 return radeon_debugfs_add_files(rdev, r420_pipes_info_list, 1); in r420_debugfs_pipes_info_init()