Lines Matching refs:r600
1999 rdev->config.r600.tiling_group_size = 256; in r600_gpu_init()
2002 rdev->config.r600.max_pipes = 4; in r600_gpu_init()
2003 rdev->config.r600.max_tile_pipes = 8; in r600_gpu_init()
2004 rdev->config.r600.max_simds = 4; in r600_gpu_init()
2005 rdev->config.r600.max_backends = 4; in r600_gpu_init()
2006 rdev->config.r600.max_gprs = 256; in r600_gpu_init()
2007 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2008 rdev->config.r600.max_stack_entries = 256; in r600_gpu_init()
2009 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
2010 rdev->config.r600.max_gs_threads = 16; in r600_gpu_init()
2011 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2012 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2013 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2014 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
2018 rdev->config.r600.max_pipes = 2; in r600_gpu_init()
2019 rdev->config.r600.max_tile_pipes = 2; in r600_gpu_init()
2020 rdev->config.r600.max_simds = 3; in r600_gpu_init()
2021 rdev->config.r600.max_backends = 1; in r600_gpu_init()
2022 rdev->config.r600.max_gprs = 128; in r600_gpu_init()
2023 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2024 rdev->config.r600.max_stack_entries = 128; in r600_gpu_init()
2025 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
2026 rdev->config.r600.max_gs_threads = 4; in r600_gpu_init()
2027 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2028 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2029 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2030 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
2036 rdev->config.r600.max_pipes = 1; in r600_gpu_init()
2037 rdev->config.r600.max_tile_pipes = 1; in r600_gpu_init()
2038 rdev->config.r600.max_simds = 2; in r600_gpu_init()
2039 rdev->config.r600.max_backends = 1; in r600_gpu_init()
2040 rdev->config.r600.max_gprs = 128; in r600_gpu_init()
2041 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2042 rdev->config.r600.max_stack_entries = 128; in r600_gpu_init()
2043 rdev->config.r600.max_hw_contexts = 4; in r600_gpu_init()
2044 rdev->config.r600.max_gs_threads = 4; in r600_gpu_init()
2045 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2046 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2047 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2048 rdev->config.r600.sq_num_cf_insts = 1; in r600_gpu_init()
2051 rdev->config.r600.max_pipes = 4; in r600_gpu_init()
2052 rdev->config.r600.max_tile_pipes = 4; in r600_gpu_init()
2053 rdev->config.r600.max_simds = 4; in r600_gpu_init()
2054 rdev->config.r600.max_backends = 4; in r600_gpu_init()
2055 rdev->config.r600.max_gprs = 192; in r600_gpu_init()
2056 rdev->config.r600.max_threads = 192; in r600_gpu_init()
2057 rdev->config.r600.max_stack_entries = 256; in r600_gpu_init()
2058 rdev->config.r600.max_hw_contexts = 8; in r600_gpu_init()
2059 rdev->config.r600.max_gs_threads = 16; in r600_gpu_init()
2060 rdev->config.r600.sx_max_export_size = 128; in r600_gpu_init()
2061 rdev->config.r600.sx_max_export_pos_size = 16; in r600_gpu_init()
2062 rdev->config.r600.sx_max_export_smx_size = 128; in r600_gpu_init()
2063 rdev->config.r600.sq_num_cf_insts = 2; in r600_gpu_init()
2083 switch (rdev->config.r600.max_tile_pipes) { in r600_gpu_init()
2099 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; in r600_gpu_init()
2100 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); in r600_gpu_init()
2115 tmp = rdev->config.r600.max_simds - in r600_gpu_init()
2117 rdev->config.r600.active_simds = tmp; in r600_gpu_init()
2121 for (i = 0; i < rdev->config.r600.max_backends; i++) in r600_gpu_init()
2125 for (i = 0; i < rdev->config.r600.max_backends; i++) in r600_gpu_init()
2129 tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.r600.max_backends, in r600_gpu_init()
2132 rdev->config.r600.backend_map = tmp; in r600_gpu_init()
2134 rdev->config.r600.tile_config = tiling_config; in r600_gpu_init()
2308 tmp = rdev->config.r600.max_pipes * 16; in r600_gpu_init()
2697 radeon_ring_write(ring, rdev->config.r600.max_hw_contexts - 1); in r600_cp_start()
3914 rdev->irq.stat_regs.r600.disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS); in r600_irq_ack()
3915 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3916 rdev->irq.stat_regs.r600.disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2); in r600_irq_ack()
3918 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET0); in r600_irq_ack()
3919 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(AFMT_STATUS + DCE3_HDMI_OFFSET1); in r600_irq_ack()
3921 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3922 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(DCE3_HDMI1_STATUS); in r600_irq_ack()
3925 rdev->irq.stat_regs.r600.disp_int = RREG32(DISP_INTERRUPT_STATUS); in r600_irq_ack()
3926 rdev->irq.stat_regs.r600.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); in r600_irq_ack()
3927 rdev->irq.stat_regs.r600.disp_int_cont2 = 0; in r600_irq_ack()
3928 rdev->irq.stat_regs.r600.hdmi0_status = RREG32(HDMI0_STATUS); in r600_irq_ack()
3929 rdev->irq.stat_regs.r600.hdmi1_status = RREG32(HDMI1_STATUS); in r600_irq_ack()
3931 rdev->irq.stat_regs.r600.d1grph_int = RREG32(D1GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3932 rdev->irq.stat_regs.r600.d2grph_int = RREG32(D2GRPH_INTERRUPT_STATUS); in r600_irq_ack()
3934 if (rdev->irq.stat_regs.r600.d1grph_int & DxGRPH_PFLIP_INT_OCCURRED) in r600_irq_ack()
3936 if (rdev->irq.stat_regs.r600.d2grph_int & DxGRPH_PFLIP_INT_OCCURRED) in r600_irq_ack()
3938 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT) in r600_irq_ack()
3940 if (rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT) in r600_irq_ack()
3942 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT) in r600_irq_ack()
3944 if (rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT) in r600_irq_ack()
3946 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT) { in r600_irq_ack()
3957 if (rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT) { in r600_irq_ack()
3968 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT) { in r600_irq_ack()
3979 if (rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT) { in r600_irq_ack()
3985 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT) { in r600_irq_ack()
3990 if (rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT) { in r600_irq_ack()
3995 if (rdev->irq.stat_regs.r600.hdmi0_status & AFMT_AZ_FORMAT_WTRIG) { in r600_irq_ack()
4000 if (rdev->irq.stat_regs.r600.hdmi1_status & AFMT_AZ_FORMAT_WTRIG) { in r600_irq_ack()
4006 if (rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG) { in r600_irq_ack()
4011 if (rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG) { in r600_irq_ack()
4132 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VBLANK_INTERRUPT)) in r600_irq_process()
4142 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT; in r600_irq_process()
4147 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D1_VLINE_INTERRUPT)) in r600_irq_process()
4150 rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VLINE_INTERRUPT; in r600_irq_process()
4162 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VBLANK_INTERRUPT)) in r600_irq_process()
4172 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT; in r600_irq_process()
4177 if (!(rdev->irq.stat_regs.r600.disp_int & LB_D2_VLINE_INTERRUPT)) in r600_irq_process()
4180 rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VLINE_INTERRUPT; in r600_irq_process()
4202 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD1_INTERRUPT)) in r600_irq_process()
4205 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD1_INTERRUPT; in r600_irq_process()
4210 if (!(rdev->irq.stat_regs.r600.disp_int & DC_HPD2_INTERRUPT)) in r600_irq_process()
4213 rdev->irq.stat_regs.r600.disp_int &= ~DC_HPD2_INTERRUPT; in r600_irq_process()
4218 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD3_INTERRUPT)) in r600_irq_process()
4221 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD3_INTERRUPT; in r600_irq_process()
4226 if (!(rdev->irq.stat_regs.r600.disp_int_cont & DC_HPD4_INTERRUPT)) in r600_irq_process()
4229 rdev->irq.stat_regs.r600.disp_int_cont &= ~DC_HPD4_INTERRUPT; in r600_irq_process()
4234 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD5_INTERRUPT)) in r600_irq_process()
4237 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD5_INTERRUPT; in r600_irq_process()
4242 if (!(rdev->irq.stat_regs.r600.disp_int_cont2 & DC_HPD6_INTERRUPT)) in r600_irq_process()
4245 rdev->irq.stat_regs.r600.disp_int_cont2 &= ~DC_HPD6_INTERRUPT; in r600_irq_process()
4258 if (!(rdev->irq.stat_regs.r600.hdmi0_status & HDMI0_AZ_FORMAT_WTRIG)) in r600_irq_process()
4261 rdev->irq.stat_regs.r600.hdmi0_status &= ~HDMI0_AZ_FORMAT_WTRIG; in r600_irq_process()
4267 if (!(rdev->irq.stat_regs.r600.hdmi1_status & HDMI0_AZ_FORMAT_WTRIG)) in r600_irq_process()
4270 rdev->irq.stat_regs.r600.hdmi1_status &= ~HDMI0_AZ_FORMAT_WTRIG; in r600_irq_process()