Lines Matching refs:uvd
72 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler); in radeon_uvd_init()
137 rdev->uvd.fw_header_present = false; in radeon_uvd_init()
138 rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES; in radeon_uvd_init()
153 rdev->uvd.fw_header_present = true; in radeon_uvd_init()
166 rdev->uvd.max_handles = RADEON_MAX_UVD_HANDLES; in radeon_uvd_init()
186 RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles; in radeon_uvd_init()
189 NULL, &rdev->uvd.vcpu_bo); in radeon_uvd_init()
195 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); in radeon_uvd_init()
197 radeon_bo_unref(&rdev->uvd.vcpu_bo); in radeon_uvd_init()
202 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM, in radeon_uvd_init()
203 &rdev->uvd.gpu_addr); in radeon_uvd_init()
205 radeon_bo_unreserve(rdev->uvd.vcpu_bo); in radeon_uvd_init()
206 radeon_bo_unref(&rdev->uvd.vcpu_bo); in radeon_uvd_init()
211 r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr); in radeon_uvd_init()
217 radeon_bo_unreserve(rdev->uvd.vcpu_bo); in radeon_uvd_init()
219 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_init()
220 atomic_set(&rdev->uvd.handles[i], 0); in radeon_uvd_init()
221 rdev->uvd.filp[i] = NULL; in radeon_uvd_init()
222 rdev->uvd.img_size[i] = 0; in radeon_uvd_init()
232 if (rdev->uvd.vcpu_bo == NULL) in radeon_uvd_fini()
235 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); in radeon_uvd_fini()
237 radeon_bo_kunmap(rdev->uvd.vcpu_bo); in radeon_uvd_fini()
238 radeon_bo_unpin(rdev->uvd.vcpu_bo); in radeon_uvd_fini()
239 radeon_bo_unreserve(rdev->uvd.vcpu_bo); in radeon_uvd_fini()
242 radeon_bo_unref(&rdev->uvd.vcpu_bo); in radeon_uvd_fini()
253 if (rdev->uvd.vcpu_bo == NULL) in radeon_uvd_suspend()
256 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_suspend()
257 uint32_t handle = atomic_read(&rdev->uvd.handles[i]); in radeon_uvd_suspend()
273 rdev->uvd.filp[i] = NULL; in radeon_uvd_suspend()
274 atomic_set(&rdev->uvd.handles[i], 0); in radeon_uvd_suspend()
286 if (rdev->uvd.vcpu_bo == NULL) in radeon_uvd_resume()
289 memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size); in radeon_uvd_resume()
291 size = radeon_bo_size(rdev->uvd.vcpu_bo); in radeon_uvd_resume()
294 ptr = rdev->uvd.cpu_addr; in radeon_uvd_resume()
331 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_free_handles()
332 uint32_t handle = atomic_read(&rdev->uvd.handles[i]); in radeon_uvd_free_handles()
333 if (handle != 0 && rdev->uvd.filp[i] == filp) { in radeon_uvd_free_handles()
348 rdev->uvd.filp[i] = NULL; in radeon_uvd_free_handles()
349 atomic_set(&rdev->uvd.handles[i], 0); in radeon_uvd_free_handles()
516 for (i = 0; i < p->rdev->uvd.max_handles; ++i) { in radeon_uvd_cs_msg()
517 if (atomic_read(&p->rdev->uvd.handles[i]) == handle) { in radeon_uvd_cs_msg()
522 if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) { in radeon_uvd_cs_msg()
523 p->rdev->uvd.filp[i] = p->filp; in radeon_uvd_cs_msg()
524 p->rdev->uvd.img_size[i] = img_size; in radeon_uvd_cs_msg()
542 for (i = 0; i < p->rdev->uvd.max_handles; ++i) { in radeon_uvd_cs_msg()
543 if (atomic_read(&p->rdev->uvd.handles[i]) == handle) { in radeon_uvd_cs_msg()
544 if (p->rdev->uvd.filp[i] != p->filp) { in radeon_uvd_cs_msg()
557 for (i = 0; i < p->rdev->uvd.max_handles; ++i) in radeon_uvd_cs_msg()
558 atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0); in radeon_uvd_cs_msg()
625 (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) { in radeon_uvd_cs_reloc()
781 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) - in radeon_uvd_get_create_msg()
784 uint32_t *msg = rdev->uvd.cpu_addr + offs; in radeon_uvd_get_create_msg()
785 uint64_t addr = rdev->uvd.gpu_addr + offs; in radeon_uvd_get_create_msg()
789 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true); in radeon_uvd_get_create_msg()
809 radeon_bo_unreserve(rdev->uvd.vcpu_bo); in radeon_uvd_get_create_msg()
817 uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) - in radeon_uvd_get_destroy_msg()
820 uint32_t *msg = rdev->uvd.cpu_addr + offs; in radeon_uvd_get_destroy_msg()
821 uint64_t addr = rdev->uvd.gpu_addr + offs; in radeon_uvd_get_destroy_msg()
825 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true); in radeon_uvd_get_destroy_msg()
838 radeon_bo_unreserve(rdev->uvd.vcpu_bo); in radeon_uvd_get_destroy_msg()
859 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_count_handles()
860 if (!atomic_read(&rdev->uvd.handles[i])) in radeon_uvd_count_handles()
863 if (rdev->uvd.img_size[i] >= 720*576) in radeon_uvd_count_handles()
873 container_of(work, struct radeon_device, uvd.idle_work.work); in radeon_uvd_idle_work_handler()
884 schedule_delayed_work(&rdev->uvd.idle_work, in radeon_uvd_idle_work_handler()
892 bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work); in radeon_uvd_note_usage()
893 set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work, in radeon_uvd_note_usage()