Lines Matching refs:rdev
36 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
38 void rs400_gart_adjust_size(struct radeon_device *rdev) in rs400_gart_adjust_size() argument
41 switch (rdev->mc.gtt_size/(1024*1024)) { in rs400_gart_adjust_size()
52 (unsigned)(rdev->mc.gtt_size >> 20)); in rs400_gart_adjust_size()
55 rdev->mc.gtt_size = 32 * 1024 * 1024; in rs400_gart_adjust_size()
60 void rs400_gart_tlb_flush(struct radeon_device *rdev) in rs400_gart_tlb_flush() argument
63 unsigned int timeout = rdev->usec_timeout; in rs400_gart_tlb_flush()
76 int rs400_gart_init(struct radeon_device *rdev) in rs400_gart_init() argument
80 if (rdev->gart.ptr) { in rs400_gart_init()
85 switch(rdev->mc.gtt_size / (1024 * 1024)) { in rs400_gart_init()
98 r = radeon_gart_init(rdev); in rs400_gart_init()
101 if (rs400_debugfs_pcie_gart_info_init(rdev)) in rs400_gart_init()
103 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in rs400_gart_init()
104 return radeon_gart_table_ram_alloc(rdev); in rs400_gart_init()
107 int rs400_gart_enable(struct radeon_device *rdev) in rs400_gart_enable() argument
116 switch(rdev->mc.gtt_size / (1024 * 1024)) { in rs400_gart_enable()
142 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { in rs400_gart_enable()
149 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); in rs400_gart_enable()
150 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); in rs400_gart_enable()
151 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { in rs400_gart_enable()
161 tmp = (u32)rdev->gart.table_addr & 0xfffff000; in rs400_gart_enable()
162 tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; in rs400_gart_enable()
175 if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { in rs400_gart_enable()
186 rs400_gart_tlb_flush(rdev); in rs400_gart_enable()
188 (unsigned)(rdev->mc.gtt_size >> 20), in rs400_gart_enable()
189 (unsigned long long)rdev->gart.table_addr); in rs400_gart_enable()
190 rdev->gart.ready = true; in rs400_gart_enable()
194 void rs400_gart_disable(struct radeon_device *rdev) in rs400_gart_disable() argument
204 void rs400_gart_fini(struct radeon_device *rdev) in rs400_gart_fini() argument
206 radeon_gart_fini(rdev); in rs400_gart_fini()
207 rs400_gart_disable(rdev); in rs400_gart_fini()
208 radeon_gart_table_ram_free(rdev); in rs400_gart_fini()
230 void rs400_gart_set_page(struct radeon_device *rdev, unsigned i, in rs400_gart_set_page() argument
233 u32 *gtt = rdev->gart.ptr; in rs400_gart_set_page()
237 int rs400_mc_wait_for_idle(struct radeon_device *rdev) in rs400_mc_wait_for_idle() argument
242 for (i = 0; i < rdev->usec_timeout; i++) { in rs400_mc_wait_for_idle()
253 static void rs400_gpu_init(struct radeon_device *rdev) in rs400_gpu_init() argument
256 r420_pipes_init(rdev); in rs400_gpu_init()
257 if (rs400_mc_wait_for_idle(rdev)) { in rs400_gpu_init()
263 static void rs400_mc_init(struct radeon_device *rdev) in rs400_mc_init() argument
267 rs400_gart_adjust_size(rdev); in rs400_mc_init()
268 rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev); in rs400_mc_init()
270 rdev->mc.vram_is_ddr = true; in rs400_mc_init()
271 rdev->mc.vram_width = 128; in rs400_mc_init()
272 r100_vram_init_sizes(rdev); in rs400_mc_init()
274 radeon_vram_location(rdev, &rdev->mc, base); in rs400_mc_init()
275 rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; in rs400_mc_init()
276 radeon_gtt_location(rdev, &rdev->mc); in rs400_mc_init()
277 radeon_update_bandwidth_info(rdev); in rs400_mc_init()
280 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) in rs400_mc_rreg() argument
285 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs400_mc_rreg()
289 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs400_mc_rreg()
293 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) in rs400_mc_wreg() argument
297 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs400_mc_wreg()
301 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs400_mc_wreg()
309 struct radeon_device *rdev = dev->dev_private; in rs400_debugfs_gart_info() local
318 if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { in rs400_debugfs_gart_info()
379 static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) in rs400_debugfs_pcie_gart_info_init() argument
382 return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); in rs400_debugfs_pcie_gart_info_init()
388 static void rs400_mc_program(struct radeon_device *rdev) in rs400_mc_program() argument
393 r100_mc_stop(rdev, &save); in rs400_mc_program()
396 if (rs400_mc_wait_for_idle(rdev)) in rs400_mc_program()
397 dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n"); in rs400_mc_program()
399 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | in rs400_mc_program()
400 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); in rs400_mc_program()
402 r100_mc_resume(rdev, &save); in rs400_mc_program()
405 static int rs400_startup(struct radeon_device *rdev) in rs400_startup() argument
409 r100_set_common_regs(rdev); in rs400_startup()
411 rs400_mc_program(rdev); in rs400_startup()
413 r300_clock_startup(rdev); in rs400_startup()
415 rs400_gpu_init(rdev); in rs400_startup()
416 r100_enable_bm(rdev); in rs400_startup()
419 r = rs400_gart_enable(rdev); in rs400_startup()
424 r = radeon_wb_init(rdev); in rs400_startup()
428 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in rs400_startup()
430 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in rs400_startup()
435 if (!rdev->irq.installed) { in rs400_startup()
436 r = radeon_irq_kms_init(rdev); in rs400_startup()
441 r100_irq_set(rdev); in rs400_startup()
442 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in rs400_startup()
444 r = r100_cp_init(rdev, 1024 * 1024); in rs400_startup()
446 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); in rs400_startup()
450 r = radeon_ib_pool_init(rdev); in rs400_startup()
452 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in rs400_startup()
459 int rs400_resume(struct radeon_device *rdev) in rs400_resume() argument
464 rs400_gart_disable(rdev); in rs400_resume()
466 r300_clock_startup(rdev); in rs400_resume()
468 rs400_mc_program(rdev); in rs400_resume()
470 if (radeon_asic_reset(rdev)) { in rs400_resume()
471 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in rs400_resume()
476 radeon_combios_asic_init(rdev->ddev); in rs400_resume()
478 r300_clock_startup(rdev); in rs400_resume()
480 radeon_surface_init(rdev); in rs400_resume()
482 rdev->accel_working = true; in rs400_resume()
483 r = rs400_startup(rdev); in rs400_resume()
485 rdev->accel_working = false; in rs400_resume()
490 int rs400_suspend(struct radeon_device *rdev) in rs400_suspend() argument
492 radeon_pm_suspend(rdev); in rs400_suspend()
493 r100_cp_disable(rdev); in rs400_suspend()
494 radeon_wb_disable(rdev); in rs400_suspend()
495 r100_irq_disable(rdev); in rs400_suspend()
496 rs400_gart_disable(rdev); in rs400_suspend()
500 void rs400_fini(struct radeon_device *rdev) in rs400_fini() argument
502 radeon_pm_fini(rdev); in rs400_fini()
503 r100_cp_fini(rdev); in rs400_fini()
504 radeon_wb_fini(rdev); in rs400_fini()
505 radeon_ib_pool_fini(rdev); in rs400_fini()
506 radeon_gem_fini(rdev); in rs400_fini()
507 rs400_gart_fini(rdev); in rs400_fini()
508 radeon_irq_kms_fini(rdev); in rs400_fini()
509 radeon_fence_driver_fini(rdev); in rs400_fini()
510 radeon_bo_fini(rdev); in rs400_fini()
511 radeon_atombios_fini(rdev); in rs400_fini()
512 kfree(rdev->bios); in rs400_fini()
513 rdev->bios = NULL; in rs400_fini()
516 int rs400_init(struct radeon_device *rdev) in rs400_init() argument
521 r100_vga_render_disable(rdev); in rs400_init()
523 radeon_scratch_init(rdev); in rs400_init()
525 radeon_surface_init(rdev); in rs400_init()
528 r100_restore_sanity(rdev); in rs400_init()
530 if (!radeon_get_bios(rdev)) { in rs400_init()
531 if (ASIC_IS_AVIVO(rdev)) in rs400_init()
534 if (rdev->is_atom_bios) { in rs400_init()
535 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); in rs400_init()
538 r = radeon_combios_init(rdev); in rs400_init()
543 if (radeon_asic_reset(rdev)) { in rs400_init()
544 dev_warn(rdev->dev, in rs400_init()
550 if (radeon_boot_test_post_card(rdev) == false) in rs400_init()
554 radeon_get_clock_info(rdev->ddev); in rs400_init()
556 rs400_mc_init(rdev); in rs400_init()
558 r = radeon_fence_driver_init(rdev); in rs400_init()
562 r = radeon_bo_init(rdev); in rs400_init()
565 r = rs400_gart_init(rdev); in rs400_init()
568 r300_set_reg_safe(rdev); in rs400_init()
571 radeon_pm_init(rdev); in rs400_init()
573 rdev->accel_working = true; in rs400_init()
574 r = rs400_startup(rdev); in rs400_init()
577 dev_err(rdev->dev, "Disabling GPU acceleration\n"); in rs400_init()
578 r100_cp_fini(rdev); in rs400_init()
579 radeon_wb_fini(rdev); in rs400_init()
580 radeon_ib_pool_fini(rdev); in rs400_init()
581 rs400_gart_fini(rdev); in rs400_init()
582 radeon_irq_kms_fini(rdev); in rs400_init()
583 rdev->accel_working = false; in rs400_init()