Lines Matching refs:rdev
47 static void rs600_gpu_init(struct radeon_device *rdev);
48 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
56 static bool avivo_is_in_vblank(struct radeon_device *rdev, int crtc) in avivo_is_in_vblank() argument
64 static bool avivo_is_counter_moving(struct radeon_device *rdev, int crtc) in avivo_is_counter_moving() argument
85 void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc) in avivo_wait_for_vblank() argument
89 if (crtc >= rdev->num_crtc) in avivo_wait_for_vblank()
98 while (avivo_is_in_vblank(rdev, crtc)) { in avivo_wait_for_vblank()
100 if (!avivo_is_counter_moving(rdev, crtc)) in avivo_wait_for_vblank()
105 while (!avivo_is_in_vblank(rdev, crtc)) { in avivo_wait_for_vblank()
107 if (!avivo_is_counter_moving(rdev, crtc)) in avivo_wait_for_vblank()
113 void rs600_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base, bool async) in rs600_page_flip() argument
115 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip()
132 for (i = 0; i < rdev->usec_timeout; i++) { in rs600_page_flip()
144 bool rs600_page_flip_pending(struct radeon_device *rdev, int crtc_id) in rs600_page_flip_pending() argument
146 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id]; in rs600_page_flip_pending()
156 struct radeon_device *rdev = dev->dev_private; in avivo_program_fmt() local
217 void rs600_pm_misc(struct radeon_device *rdev) in rs600_pm_misc() argument
219 int requested_index = rdev->pm.requested_power_state_index; in rs600_pm_misc()
220 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index]; in rs600_pm_misc()
246 radeon_atom_set_voltage(rdev, voltage->vddc_id, SET_VOLTAGE_TYPE_ASIC_VDDC); in rs600_pm_misc()
300 if ((rdev->flags & RADEON_IS_PCIE) && in rs600_pm_misc()
301 !(rdev->flags & RADEON_IS_IGP) && in rs600_pm_misc()
302 rdev->asic->pm.set_pcie_lanes && in rs600_pm_misc()
304 rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) { in rs600_pm_misc()
305 radeon_set_pcie_lanes(rdev, in rs600_pm_misc()
311 void rs600_pm_prepare(struct radeon_device *rdev) in rs600_pm_prepare() argument
313 struct drm_device *ddev = rdev->ddev; in rs600_pm_prepare()
329 void rs600_pm_finish(struct radeon_device *rdev) in rs600_pm_finish() argument
331 struct drm_device *ddev = rdev->ddev; in rs600_pm_finish()
348 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd) in rs600_hpd_sense() argument
370 void rs600_hpd_set_polarity(struct radeon_device *rdev, in rs600_hpd_set_polarity() argument
374 bool connected = rs600_hpd_sense(rdev, hpd); in rs600_hpd_set_polarity()
398 void rs600_hpd_init(struct radeon_device *rdev) in rs600_hpd_init() argument
400 struct drm_device *dev = rdev->ddev; in rs600_hpd_init()
420 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd); in rs600_hpd_init()
422 radeon_irq_kms_enable_hpd(rdev, enable); in rs600_hpd_init()
425 void rs600_hpd_fini(struct radeon_device *rdev) in rs600_hpd_fini() argument
427 struct drm_device *dev = rdev->ddev; in rs600_hpd_fini()
448 radeon_irq_kms_disable_hpd(rdev, disable); in rs600_hpd_fini()
451 int rs600_asic_reset(struct radeon_device *rdev, bool hard) in rs600_asic_reset() argument
462 rv515_mc_stop(rdev, &save); in rs600_asic_reset()
464 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
472 pci_save_state(rdev->pdev); in rs600_asic_reset()
474 pci_clear_master(rdev->pdev); in rs600_asic_reset()
484 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
492 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
500 dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status); in rs600_asic_reset()
502 pci_restore_state(rdev->pdev); in rs600_asic_reset()
505 dev_err(rdev->dev, "failed to reset GPU\n"); in rs600_asic_reset()
508 dev_info(rdev->dev, "GPU reset succeed\n"); in rs600_asic_reset()
509 rv515_mc_resume(rdev, &save); in rs600_asic_reset()
516 void rs600_gart_tlb_flush(struct radeon_device *rdev) in rs600_gart_tlb_flush() argument
534 static int rs600_gart_init(struct radeon_device *rdev) in rs600_gart_init() argument
538 if (rdev->gart.robj) { in rs600_gart_init()
543 r = radeon_gart_init(rdev); in rs600_gart_init()
547 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in rs600_gart_init()
548 return radeon_gart_table_vram_alloc(rdev); in rs600_gart_init()
551 static int rs600_gart_enable(struct radeon_device *rdev) in rs600_gart_enable() argument
556 if (rdev->gart.robj == NULL) { in rs600_gart_enable()
557 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in rs600_gart_enable()
560 r = radeon_gart_table_vram_pin(rdev); in rs600_gart_enable()
593 rdev->gart.table_addr); in rs600_gart_enable()
594 WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start); in rs600_gart_enable()
595 WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end); in rs600_gart_enable()
599 WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start); in rs600_gart_enable()
600 WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end); in rs600_gart_enable()
607 rs600_gart_tlb_flush(rdev); in rs600_gart_enable()
609 (unsigned)(rdev->mc.gtt_size >> 20), in rs600_gart_enable()
610 (unsigned long long)rdev->gart.table_addr); in rs600_gart_enable()
611 rdev->gart.ready = true; in rs600_gart_enable()
615 static void rs600_gart_disable(struct radeon_device *rdev) in rs600_gart_disable() argument
623 radeon_gart_table_vram_unpin(rdev); in rs600_gart_disable()
626 static void rs600_gart_fini(struct radeon_device *rdev) in rs600_gart_fini() argument
628 radeon_gart_fini(rdev); in rs600_gart_fini()
629 rs600_gart_disable(rdev); in rs600_gart_fini()
630 radeon_gart_table_vram_free(rdev); in rs600_gart_fini()
648 void rs600_gart_set_page(struct radeon_device *rdev, unsigned i, in rs600_gart_set_page() argument
651 void __iomem *ptr = (void *)rdev->gart.ptr; in rs600_gart_set_page()
655 int rs600_irq_set(struct radeon_device *rdev) in rs600_irq_set() argument
664 if (ASIC_IS_DCE2(rdev)) in rs600_irq_set()
670 if (!rdev->irq.installed) { in rs600_irq_set()
675 if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) { in rs600_irq_set()
678 if (rdev->irq.crtc_vblank_int[0] || in rs600_irq_set()
679 atomic_read(&rdev->irq.pflip[0])) { in rs600_irq_set()
682 if (rdev->irq.crtc_vblank_int[1] || in rs600_irq_set()
683 atomic_read(&rdev->irq.pflip[1])) { in rs600_irq_set()
686 if (rdev->irq.hpd[0]) { in rs600_irq_set()
689 if (rdev->irq.hpd[1]) { in rs600_irq_set()
692 if (rdev->irq.afmt[0]) { in rs600_irq_set()
699 if (ASIC_IS_DCE2(rdev)) in rs600_irq_set()
708 static inline u32 rs600_irq_ack(struct radeon_device *rdev) in rs600_irq_ack() argument
715 rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); in rs600_irq_ack()
716 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
720 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
724 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
729 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_ack()
735 rdev->irq.stat_regs.r500.disp_int = 0; in rs600_irq_ack()
738 if (ASIC_IS_DCE2(rdev)) { in rs600_irq_ack()
739 rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & in rs600_irq_ack()
741 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { in rs600_irq_ack()
747 rdev->irq.stat_regs.r500.hdmi0_status = 0; in rs600_irq_ack()
755 void rs600_irq_disable(struct radeon_device *rdev) in rs600_irq_disable() argument
764 rs600_irq_ack(rdev); in rs600_irq_disable()
767 int rs600_irq_process(struct radeon_device *rdev) in rs600_irq_process() argument
773 status = rs600_irq_ack(rdev); in rs600_irq_process()
775 !rdev->irq.stat_regs.r500.disp_int && in rs600_irq_process()
776 !rdev->irq.stat_regs.r500.hdmi0_status) { in rs600_irq_process()
780 rdev->irq.stat_regs.r500.disp_int || in rs600_irq_process()
781 rdev->irq.stat_regs.r500.hdmi0_status) { in rs600_irq_process()
784 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX); in rs600_irq_process()
787 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
788 if (rdev->irq.crtc_vblank_int[0]) { in rs600_irq_process()
789 drm_handle_vblank(rdev->ddev, 0); in rs600_irq_process()
790 rdev->pm.vblank_sync = true; in rs600_irq_process()
791 wake_up(&rdev->irq.vblank_queue); in rs600_irq_process()
793 if (atomic_read(&rdev->irq.pflip[0])) in rs600_irq_process()
794 radeon_crtc_handle_vblank(rdev, 0); in rs600_irq_process()
796 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
797 if (rdev->irq.crtc_vblank_int[1]) { in rs600_irq_process()
798 drm_handle_vblank(rdev->ddev, 1); in rs600_irq_process()
799 rdev->pm.vblank_sync = true; in rs600_irq_process()
800 wake_up(&rdev->irq.vblank_queue); in rs600_irq_process()
802 if (atomic_read(&rdev->irq.pflip[1])) in rs600_irq_process()
803 radeon_crtc_handle_vblank(rdev, 1); in rs600_irq_process()
805 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
809 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { in rs600_irq_process()
813 if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { in rs600_irq_process()
817 status = rs600_irq_ack(rdev); in rs600_irq_process()
820 schedule_delayed_work(&rdev->hotplug_work, 0); in rs600_irq_process()
822 schedule_work(&rdev->audio_work); in rs600_irq_process()
823 if (rdev->msi_enabled) { in rs600_irq_process()
824 switch (rdev->family) { in rs600_irq_process()
840 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc) in rs600_get_vblank_counter() argument
848 int rs600_mc_wait_for_idle(struct radeon_device *rdev) in rs600_mc_wait_for_idle() argument
852 for (i = 0; i < rdev->usec_timeout; i++) { in rs600_mc_wait_for_idle()
860 static void rs600_gpu_init(struct radeon_device *rdev) in rs600_gpu_init() argument
862 r420_pipes_init(rdev); in rs600_gpu_init()
864 if (rs600_mc_wait_for_idle(rdev)) in rs600_gpu_init()
865 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in rs600_gpu_init()
868 static void rs600_mc_init(struct radeon_device *rdev) in rs600_mc_init() argument
872 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); in rs600_mc_init()
873 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); in rs600_mc_init()
874 rdev->mc.vram_is_ddr = true; in rs600_mc_init()
875 rdev->mc.vram_width = 128; in rs600_mc_init()
876 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE); in rs600_mc_init()
877 rdev->mc.mc_vram_size = rdev->mc.real_vram_size; in rs600_mc_init()
878 rdev->mc.visible_vram_size = rdev->mc.aper_size; in rs600_mc_init()
879 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev); in rs600_mc_init()
882 radeon_vram_location(rdev, &rdev->mc, base); in rs600_mc_init()
883 rdev->mc.gtt_base_align = 0; in rs600_mc_init()
884 radeon_gtt_location(rdev, &rdev->mc); in rs600_mc_init()
885 radeon_update_bandwidth_info(rdev); in rs600_mc_init()
888 void rs600_bandwidth_update(struct radeon_device *rdev) in rs600_bandwidth_update() argument
895 if (!rdev->mode_info.mode_config_initialized) in rs600_bandwidth_update()
898 radeon_update_display_priority(rdev); in rs600_bandwidth_update()
900 if (rdev->mode_info.crtcs[0]->base.enabled) in rs600_bandwidth_update()
901 mode0 = &rdev->mode_info.crtcs[0]->base.mode; in rs600_bandwidth_update()
902 if (rdev->mode_info.crtcs[1]->base.enabled) in rs600_bandwidth_update()
903 mode1 = &rdev->mode_info.crtcs[1]->base.mode; in rs600_bandwidth_update()
905 rs690_line_buffer_adjust(rdev, mode0, mode1); in rs600_bandwidth_update()
907 if (rdev->disp_priority == 2) { in rs600_bandwidth_update()
919 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg) in rs600_mc_rreg() argument
924 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs600_mc_rreg()
928 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs600_mc_rreg()
932 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) in rs600_mc_wreg() argument
936 spin_lock_irqsave(&rdev->mc_idx_lock, flags); in rs600_mc_wreg()
940 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags); in rs600_mc_wreg()
943 static void rs600_debugfs(struct radeon_device *rdev) in rs600_debugfs() argument
945 if (r100_debugfs_rbbm_init(rdev)) in rs600_debugfs()
949 void rs600_set_safe_registers(struct radeon_device *rdev) in rs600_set_safe_registers() argument
951 rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm; in rs600_set_safe_registers()
952 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm); in rs600_set_safe_registers()
955 static void rs600_mc_program(struct radeon_device *rdev) in rs600_mc_program() argument
960 rv515_mc_stop(rdev, &save); in rs600_mc_program()
963 if (rs600_mc_wait_for_idle(rdev)) in rs600_mc_program()
964 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); in rs600_mc_program()
972 S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | in rs600_mc_program()
973 S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); in rs600_mc_program()
975 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); in rs600_mc_program()
977 rv515_mc_resume(rdev, &save); in rs600_mc_program()
980 static int rs600_startup(struct radeon_device *rdev) in rs600_startup() argument
984 rs600_mc_program(rdev); in rs600_startup()
986 rv515_clock_startup(rdev); in rs600_startup()
988 rs600_gpu_init(rdev); in rs600_startup()
991 r = rs600_gart_enable(rdev); in rs600_startup()
996 r = radeon_wb_init(rdev); in rs600_startup()
1000 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX); in rs600_startup()
1002 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r); in rs600_startup()
1007 if (!rdev->irq.installed) { in rs600_startup()
1008 r = radeon_irq_kms_init(rdev); in rs600_startup()
1013 rs600_irq_set(rdev); in rs600_startup()
1014 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); in rs600_startup()
1016 r = r100_cp_init(rdev, 1024 * 1024); in rs600_startup()
1018 dev_err(rdev->dev, "failed initializing CP (%d).\n", r); in rs600_startup()
1022 r = radeon_ib_pool_init(rdev); in rs600_startup()
1024 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); in rs600_startup()
1028 r = radeon_audio_init(rdev); in rs600_startup()
1030 dev_err(rdev->dev, "failed initializing audio\n"); in rs600_startup()
1037 int rs600_resume(struct radeon_device *rdev) in rs600_resume() argument
1042 rs600_gart_disable(rdev); in rs600_resume()
1044 rv515_clock_startup(rdev); in rs600_resume()
1046 if (radeon_asic_reset(rdev)) { in rs600_resume()
1047 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", in rs600_resume()
1052 atom_asic_init(rdev->mode_info.atom_context); in rs600_resume()
1054 rv515_clock_startup(rdev); in rs600_resume()
1056 radeon_surface_init(rdev); in rs600_resume()
1058 rdev->accel_working = true; in rs600_resume()
1059 r = rs600_startup(rdev); in rs600_resume()
1061 rdev->accel_working = false; in rs600_resume()
1066 int rs600_suspend(struct radeon_device *rdev) in rs600_suspend() argument
1068 radeon_pm_suspend(rdev); in rs600_suspend()
1069 radeon_audio_fini(rdev); in rs600_suspend()
1070 r100_cp_disable(rdev); in rs600_suspend()
1071 radeon_wb_disable(rdev); in rs600_suspend()
1072 rs600_irq_disable(rdev); in rs600_suspend()
1073 rs600_gart_disable(rdev); in rs600_suspend()
1077 void rs600_fini(struct radeon_device *rdev) in rs600_fini() argument
1079 radeon_pm_fini(rdev); in rs600_fini()
1080 radeon_audio_fini(rdev); in rs600_fini()
1081 r100_cp_fini(rdev); in rs600_fini()
1082 radeon_wb_fini(rdev); in rs600_fini()
1083 radeon_ib_pool_fini(rdev); in rs600_fini()
1084 radeon_gem_fini(rdev); in rs600_fini()
1085 rs600_gart_fini(rdev); in rs600_fini()
1086 radeon_irq_kms_fini(rdev); in rs600_fini()
1087 radeon_fence_driver_fini(rdev); in rs600_fini()
1088 radeon_bo_fini(rdev); in rs600_fini()
1089 radeon_atombios_fini(rdev); in rs600_fini()
1090 kfree(rdev->bios); in rs600_fini()
1091 rdev->bios = NULL; in rs600_fini()
1094 int rs600_init(struct radeon_device *rdev) in rs600_init() argument
1099 rv515_vga_render_disable(rdev); in rs600_init()
1101 radeon_scratch_init(rdev); in rs600_init()
1103 radeon_surface_init(rdev); in rs600_init()
1105 r100_restore_sanity(rdev); in rs600_init()
1107 if (!radeon_get_bios(rdev)) { in rs600_init()
1108 if (ASIC_IS_AVIVO(rdev)) in rs600_init()
1111 if (rdev->is_atom_bios) { in rs600_init()
1112 r = radeon_atombios_init(rdev); in rs600_init()
1116 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n"); in rs600_init()
1120 if (radeon_asic_reset(rdev)) { in rs600_init()
1121 dev_warn(rdev->dev, in rs600_init()
1127 if (radeon_boot_test_post_card(rdev) == false) in rs600_init()
1131 radeon_get_clock_info(rdev->ddev); in rs600_init()
1133 rs600_mc_init(rdev); in rs600_init()
1134 rs600_debugfs(rdev); in rs600_init()
1136 r = radeon_fence_driver_init(rdev); in rs600_init()
1140 r = radeon_bo_init(rdev); in rs600_init()
1143 r = rs600_gart_init(rdev); in rs600_init()
1146 rs600_set_safe_registers(rdev); in rs600_init()
1149 radeon_pm_init(rdev); in rs600_init()
1151 rdev->accel_working = true; in rs600_init()
1152 r = rs600_startup(rdev); in rs600_init()
1155 dev_err(rdev->dev, "Disabling GPU acceleration\n"); in rs600_init()
1156 r100_cp_fini(rdev); in rs600_init()
1157 radeon_wb_fini(rdev); in rs600_init()
1158 radeon_ib_pool_fini(rdev); in rs600_init()
1159 rs600_gart_fini(rdev); in rs600_init()
1160 radeon_irq_kms_fini(rdev); in rs600_init()
1161 rdev->accel_working = false; in rs600_init()