1332 u64 read_csr(const struct hfi1_devdata *dd, u32 offset)  in read_csr()  function
1380 		ret = read_csr(dd, csr);  in read_write_csr()
5684 	u64 src = read_csr(dd, SEND_EGRESS_ERR_SOURCE); /* read first */  in handle_send_egress_err_info()
5685 	u64 info = read_csr(dd, SEND_EGRESS_ERR_INFO);  in handle_send_egress_err_info()
6347 	reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_1);  in handle_8051_request()
6390 	u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);  in set_up_vau()
6405 	u64 reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);  in set_up_vl15()
6478 	dd->lcb_err_en = read_csr(dd, DC_LCB_ERR_EN);  in lcb_shutdown()
6479 	reg = read_csr(dd, DCC_CFG_RESET);  in lcb_shutdown()
6483 	(void)read_csr(dd, DCC_CFG_RESET); /* make sure the write completed */  in lcb_shutdown()
6712 	rcvctrl = read_csr(dd, RCV_CTRL);  in adjust_rcvctrl()
6783 		reg = read_csr(dd, CCE_STATUS);  in wait_for_freeze_status()
7494 	reg = read_csr(dd, SEND_CM_CTRL);  in handle_verify_cap()
7557 		reg = read_csr(dd, DC_LCB_CFG_LINK_KILL_EN);  in handle_verify_cap()
7717 		info = read_csr(dd, DC_DC8051_DBG_ERR_INFO_SET_BY_8051);  in handle_8051_interrupt()
7822 			  read_csr(dd, DC_DC8051_ERR_EN) &  in handle_8051_interrupt()
7912 			info = read_csr(dd, DCC_ERR_INFO_UNCORRECTABLE);  in handle_dcc_err()
7931 		info = read_csr(dd, DCC_ERR_INFO_FMCONFIG);  in handle_dcc_err()
7982 		info = read_csr(dd, DCC_ERR_INFO_PORTRCV);  in handle_dcc_err()
7983 		hdr0 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR0);  in handle_dcc_err()
7984 		hdr1 = read_csr(dd, DCC_ERR_INFO_PORTRCV_HDR1);  in handle_dcc_err()
8272 		regs[i] = read_csr(dd, CCE_INT_STATUS + (8 * i)) &  in general_interrupt()
8304 	status = read_csr(dd,  in sdma_interrupt()
8335 	(void)read_csr(dd, addr);  in clear_recv_intr()
8452 	reg = read_csr(dd, DC_DC8051_STS_CUR_STATE);  in read_physical_state()
8461 	reg = read_csr(dd, DCC_CFG_PORT_CONFIG);  in read_logical_state()
8470 	reg = read_csr(dd, DCC_CFG_PORT_CONFIG);  in set_logical_state()
8487 			*data = read_csr(dd, addr);  in read_lcb_via_8051()
8567 	*data = read_csr(dd, addr);  in read_lcb_csr()
8682 		reg = read_csr(dd, DC_DC8051_CFG_EXT_DEV_0);  in do_8051_command()
8706 		reg = read_csr(dd, DC_DC8051_CFG_HOST_CMD_1);  in do_8051_command()
8726 			*out_data |= (read_csr(dd, DC_DC8051_CFG_EXT_DEV_1)  in do_8051_command()
9210 		  (read_csr(dd, DC_DC8051_CFG_MODE) | DISABLE_SELF_GUID_CHECK));  in init_loopback()
9406 		mask = read_csr(dd, dd->hfi1_id ?  in wait_for_qsfp_init()
9424 	mask = read_csr(dd, dd->hfi1_id ? ASIC_QSFP2_MASK : ASIC_QSFP1_MASK);  in set_qsfp_int_n()
9450 	qsfp_mask = read_csr(dd,  in reset_qsfp()
9653 	cce_int_mask = read_csr(dd, CCE_INT_MASK +  in init_qsfp_int()
10095 	len1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG);  in set_send_length()
10108 	u64 c1 = read_csr(ppd->dd, DCC_CFG_PORT_CONFIG1);  in set_lidlmc()
10276 		reg = read_csr(dd, DC_LCB_STS_LINK_TRANSFER_ACTIVE);  in wait_link_transfer_active()
10307 	(void)read_csr(dd, DC_LCB_CFG_TX_FIFOS_RESET);  in force_logical_link_state_down()
10581 		reg = read_csr(ppd->dd, SEND_CM_CREDIT_VL + (8 * i));  in data_vls_operational()
11097 	u64 reg = read_csr(dd, csr);  in read_one_cm_vl()
11126 	reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);  in get_buffer_control()
11143 	reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_15_0);  in get_sc2vlnt()
11151 	reg = read_csr(dd, DCC_CFG_SC_VL_TABLE_31_16);  in get_sc2vlnt()
11225 	reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);  in set_global_shared()
11236 	reg = read_csr(dd, SEND_CM_GLOBAL_CREDIT);  in set_global_limit()
11253 	reg = read_csr(dd, addr);  in set_vl_shared()
11270 	reg = read_csr(dd, addr);  in set_vl_dedicated()
11285 		reg = read_csr(dd, SEND_CM_CREDIT_USED_STATUS) & mask;  in wait_for_vl_status_clear()
12982 	reg = read_csr(dd, ASIC_STS_THERM);  in hfi1_tempsense_rd()
13115 	reg = read_csr(dd, CCE_INT_MAP + (8 * m));  in remap_intr()
13682 	reg = read_csr(dd, CCE_STATUS);  in clear_cce_status()
13692 		reg = read_csr(dd, CCE_STATUS);  in clear_cce_status()
13910 		reg = read_csr(dd, RCV_STATUS);  in init_rbufs()
13939 	read_csr(dd, RCV_CTRL);  in init_rbufs()
13946 		reg = read_csr(dd, RCV_STATUS);  in init_rbufs()
14136 	(void)read_csr(dd, CCE_DC_CTRL);  in init_chip()
14590 	reg = read_csr(dd, regoff);  in hfi1_init_vnic_rsm()
14607 				reg = read_csr(dd, regoff);  in hfi1_init_vnic_rsm()
14675 	val = read_csr(dd, RCV_BYPASS);  in init_rxe()
14960 	mask = read_csr(dd, CCE_INT_MASK);  in check_int_registers()
14962 	reg = read_csr(dd, CCE_INT_MASK);  in check_int_registers()
14968 	reg = read_csr(dd, CCE_INT_STATUS);  in check_int_registers()
14974 	reg = read_csr(dd, CCE_INT_STATUS);  in check_int_registers()
15083 	dd->revision = read_csr(dd, CCE_REVISION);  in hfi1_init_dd()
15109 	reg = read_csr(dd, CCE_REVISION2);  in hfi1_init_dd()
15126 	dd->chip_rcv_contexts = read_csr(dd, RCV_CONTEXTS);  in hfi1_init_dd()
15127 	dd->chip_send_contexts = read_csr(dd, SEND_CONTEXTS);  in hfi1_init_dd()
15128 	dd->chip_sdma_engines = read_csr(dd, SEND_DMA_ENGINES);  in hfi1_init_dd()
15129 	dd->chip_pio_mem_size = read_csr(dd, SEND_PIO_MEM_SIZE);  in hfi1_init_dd()
15130 	dd->chip_sdma_mem_size = read_csr(dd, SEND_DMA_MEM_SIZE);  in hfi1_init_dd()