Lines Matching refs:dd
136 int qib_pcie_ddinit(struct qib_devdata *dd, struct pci_dev *pdev, in qib_pcie_ddinit() argument
142 dd->pcidev = pdev; in qib_pcie_ddinit()
143 pci_set_drvdata(pdev, dd); in qib_pcie_ddinit()
148 dd->kregbase = ioremap_nocache(addr, len); in qib_pcie_ddinit()
149 if (!dd->kregbase) in qib_pcie_ddinit()
152 dd->kregend = (u64 __iomem *)((void __iomem *) dd->kregbase + len); in qib_pcie_ddinit()
153 dd->physaddr = addr; /* used for io_remap, etc. */ in qib_pcie_ddinit()
159 dd->pcibar0 = addr; in qib_pcie_ddinit()
160 dd->pcibar1 = addr >> 32; in qib_pcie_ddinit()
161 dd->deviceid = ent->device; /* save for later use */ in qib_pcie_ddinit()
162 dd->vendorid = ent->vendor; in qib_pcie_ddinit()
172 void qib_pcie_ddcleanup(struct qib_devdata *dd) in qib_pcie_ddcleanup() argument
174 u64 __iomem *base = (void __iomem *) dd->kregbase; in qib_pcie_ddcleanup()
176 dd->kregbase = NULL; in qib_pcie_ddcleanup()
178 if (dd->piobase) in qib_pcie_ddcleanup()
179 iounmap(dd->piobase); in qib_pcie_ddcleanup()
180 if (dd->userbase) in qib_pcie_ddcleanup()
181 iounmap(dd->userbase); in qib_pcie_ddcleanup()
182 if (dd->piovl15base) in qib_pcie_ddcleanup()
183 iounmap(dd->piovl15base); in qib_pcie_ddcleanup()
185 pci_disable_device(dd->pcidev); in qib_pcie_ddcleanup()
186 pci_release_regions(dd->pcidev); in qib_pcie_ddcleanup()
188 pci_set_drvdata(dd->pcidev, NULL); in qib_pcie_ddcleanup()
196 static void qib_msi_setup(struct qib_devdata *dd, int pos) in qib_msi_setup() argument
198 struct pci_dev *pdev = dd->pcidev; in qib_msi_setup()
201 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO, &dd->msi_lo); in qib_msi_setup()
202 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_HI, &dd->msi_hi); in qib_msi_setup()
208 &dd->msi_data); in qib_msi_setup()
211 static int qib_allocate_irqs(struct qib_devdata *dd, u32 maxvec) in qib_allocate_irqs() argument
216 if (dd->pcidev->msix_cap) { in qib_allocate_irqs()
219 if (dd->pcidev->msi_cap) { in qib_allocate_irqs()
222 qib_msi_setup(dd, dd->pcidev->msi_cap); in qib_allocate_irqs()
227 qib_dev_err(dd, "No PCI MSI or MSIx capability!\n"); in qib_allocate_irqs()
229 return pci_alloc_irq_vectors(dd->pcidev, 1, maxvec, flags); in qib_allocate_irqs()
232 int qib_pcie_params(struct qib_devdata *dd, u32 minw, u32 *nent) in qib_pcie_params() argument
239 if (!pci_is_pcie(dd->pcidev)) { in qib_pcie_params()
240 qib_dev_err(dd, "Can't find PCI Express capability!\n"); in qib_pcie_params()
242 dd->lbus_width = 1; in qib_pcie_params()
243 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */ in qib_pcie_params()
249 nvec = qib_allocate_irqs(dd, maxvec); in qib_pcie_params()
265 if (!dd->pcidev->msix_enabled) in qib_pcie_params()
266 qib_dev_err(dd, in qib_pcie_params()
270 pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); in qib_pcie_params()
278 dd->lbus_width = linkstat; in qib_pcie_params()
282 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */ in qib_pcie_params()
285 dd->lbus_speed = 5000; /* Gen1, 5GHz */ in qib_pcie_params()
288 dd->lbus_speed = 2500; in qib_pcie_params()
297 qib_dev_err(dd, in qib_pcie_params()
301 qib_tune_pcie_caps(dd); in qib_pcie_params()
303 qib_tune_pcie_coalesce(dd); in qib_pcie_params()
307 snprintf(dd->lbus_info, sizeof(dd->lbus_info), in qib_pcie_params()
308 "PCIe,%uMHz,x%u\n", dd->lbus_speed, dd->lbus_width); in qib_pcie_params()
320 int qib_reinit_intr(struct qib_devdata *dd) in qib_reinit_intr() argument
327 if (!dd->msi_lo) in qib_reinit_intr()
330 pos = dd->pcidev->msi_cap; in qib_reinit_intr()
332 qib_dev_err(dd, in qib_reinit_intr()
338 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO, in qib_reinit_intr()
339 dd->msi_lo); in qib_reinit_intr()
340 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI, in qib_reinit_intr()
341 dd->msi_hi); in qib_reinit_intr()
342 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control); in qib_reinit_intr()
345 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, in qib_reinit_intr()
349 pci_write_config_word(dd->pcidev, pos + in qib_reinit_intr()
351 dd->msi_data); in qib_reinit_intr()
354 if (!ret && (dd->flags & QIB_HAS_INTX)) { in qib_reinit_intr()
355 qib_enable_intx(dd); in qib_reinit_intr()
360 pci_set_master(dd->pcidev); in qib_reinit_intr()
370 void qib_nomsi(struct qib_devdata *dd) in qib_nomsi() argument
372 dd->msi_lo = 0; in qib_nomsi()
373 pci_free_irq_vectors(dd->pcidev); in qib_nomsi()
379 void qib_nomsix(struct qib_devdata *dd) in qib_nomsix() argument
381 pci_free_irq_vectors(dd->pcidev); in qib_nomsix()
388 void qib_enable_intx(struct qib_devdata *dd) in qib_enable_intx() argument
392 struct pci_dev *pdev = dd->pcidev; in qib_enable_intx()
395 qib_dev_err(dd, "Failed to enable INTx\n"); in qib_enable_intx()
419 void qib_pcie_getcmd(struct qib_devdata *dd, u16 *cmd, u8 *iline, u8 *cline) in qib_pcie_getcmd() argument
421 pci_read_config_word(dd->pcidev, PCI_COMMAND, cmd); in qib_pcie_getcmd()
422 pci_read_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline); in qib_pcie_getcmd()
423 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline); in qib_pcie_getcmd()
426 void qib_pcie_reenable(struct qib_devdata *dd, u16 cmd, u8 iline, u8 cline) in qib_pcie_reenable() argument
430 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, in qib_pcie_reenable()
431 dd->pcibar0); in qib_pcie_reenable()
433 qib_dev_err(dd, "rewrite of BAR0 failed: %d\n", r); in qib_pcie_reenable()
434 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, in qib_pcie_reenable()
435 dd->pcibar1); in qib_pcie_reenable()
437 qib_dev_err(dd, "rewrite of BAR1 failed: %d\n", r); in qib_pcie_reenable()
439 pci_write_config_word(dd->pcidev, PCI_COMMAND, cmd); in qib_pcie_reenable()
440 pci_write_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline); in qib_pcie_reenable()
441 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline); in qib_pcie_reenable()
442 r = pci_enable_device(dd->pcidev); in qib_pcie_reenable()
444 qib_dev_err(dd, in qib_pcie_reenable()
459 static void qib_tune_pcie_coalesce(struct qib_devdata *dd) in qib_tune_pcie_coalesce() argument
470 parent = dd->pcidev->bus->self; in qib_tune_pcie_coalesce()
472 qib_devinfo(dd->pcidev, "Parent not root\n"); in qib_tune_pcie_coalesce()
527 static void qib_tune_pcie_caps(struct qib_devdata *dd) in qib_tune_pcie_caps() argument
534 parent = dd->pcidev->bus->self; in qib_tune_pcie_caps()
536 qib_devinfo(dd->pcidev, "Parent not root\n"); in qib_tune_pcie_caps()
540 if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev)) in qib_tune_pcie_caps()
546 ep_mpss = dd->pcidev->pcie_mpss; in qib_tune_pcie_caps()
547 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; in qib_tune_pcie_caps()
564 pcie_set_mps(dd->pcidev, 128 << ep_mps); in qib_tune_pcie_caps()
578 ep_mrrs = pcie_get_readrq(dd->pcidev); in qib_tune_pcie_caps()
586 pcie_set_readrq(dd->pcidev, ep_mrrs); in qib_tune_pcie_caps()
598 struct qib_devdata *dd = pci_get_drvdata(pdev); in qib_pci_error_detected() local
614 if (dd) { in qib_pci_error_detected()
616 dd->flags &= ~QIB_PRESENT; in qib_pci_error_detected()
617 qib_disable_after_error(dd); in qib_pci_error_detected()
635 struct qib_devdata *dd = pci_get_drvdata(pdev); in qib_pci_mmio_enabled() local
638 if (dd && dd->pport) { in qib_pci_mmio_enabled()
639 words = dd->f_portcntr(dd->pport, QIBPORTCNTR_WORDRCV); in qib_pci_mmio_enabled()
659 struct qib_devdata *dd = pci_get_drvdata(pdev); in qib_pci_resume() local
668 qib_init(dd, 1); /* same as re-init after reset */ in qib_pci_resume()