Lines Matching refs:clock
1120 static int request_pll(u8 clock, bool enable) in request_pll() argument
1124 if (clock == PRCMU_PLLSOC0) in request_pll()
1125 clock = (enable ? PLL_SOC0_ON : PLL_SOC0_OFF); in request_pll()
1126 else if (clock == PRCMU_PLLSOC1) in request_pll()
1127 clock = (enable ? PLL_SOC1_ON : PLL_SOC1_OFF); in request_pll()
1137 writeb(clock, (tcdm_base + PRCM_REQ_MB1_PLL_ON_OFF)); in request_pll()
1319 static int request_clock(u8 clock, bool enable) in request_clock() argument
1330 val = readl(prcmu_base + clk_mgt[clock].offset); in request_clock()
1332 val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw); in request_clock()
1334 clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK); in request_clock()
1337 writel(val, prcmu_base + clk_mgt[clock].offset); in request_clock()
1347 static int request_sga_clock(u8 clock, bool enable) in request_sga_clock() argument
1357 ret = request_clock(clock, enable); in request_sga_clock()
1447 int db8500_prcmu_request_clock(u8 clock, bool enable) in db8500_prcmu_request_clock() argument
1449 if (clock == PRCMU_SGACLK) in db8500_prcmu_request_clock()
1450 return request_sga_clock(clock, enable); in db8500_prcmu_request_clock()
1451 else if (clock < PRCMU_NUM_REG_CLOCKS) in db8500_prcmu_request_clock()
1452 return request_clock(clock, enable); in db8500_prcmu_request_clock()
1453 else if (clock == PRCMU_TIMCLK) in db8500_prcmu_request_clock()
1455 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) in db8500_prcmu_request_clock()
1456 return request_dsiclk((clock - PRCMU_DSI0CLK), enable); in db8500_prcmu_request_clock()
1457 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) in db8500_prcmu_request_clock()
1458 return request_dsiescclk((clock - PRCMU_DSI0ESCCLK), enable); in db8500_prcmu_request_clock()
1459 else if (clock == PRCMU_PLLDSI) in db8500_prcmu_request_clock()
1461 else if (clock == PRCMU_SYSCLK) in db8500_prcmu_request_clock()
1463 else if ((clock == PRCMU_PLLSOC0) || (clock == PRCMU_PLLSOC1)) in db8500_prcmu_request_clock()
1464 return request_pll(clock, enable); in db8500_prcmu_request_clock()
1507 static unsigned long clock_rate(u8 clock) in clock_rate() argument
1513 val = readl(prcmu_base + clk_mgt[clock].offset); in clock_rate()
1516 if (clk_mgt[clock].clk38div && (val & PRCM_CLK_MGT_CLK38DIV)) in clock_rate()
1521 val |= clk_mgt[clock].pllsw; in clock_rate()
1525 rate = pll_rate(PRCM_PLLSOC0_FREQ, rate, clk_mgt[clock].branch); in clock_rate()
1527 rate = pll_rate(PRCM_PLLSOC1_FREQ, rate, clk_mgt[clock].branch); in clock_rate()
1529 rate = pll_rate(PRCM_PLLDDR_FREQ, rate, clk_mgt[clock].branch); in clock_rate()
1533 if ((clock == PRCMU_SGACLK) && in clock_rate()
1610 unsigned long prcmu_clock_rate(u8 clock) in prcmu_clock_rate() argument
1612 if (clock < PRCMU_NUM_REG_CLOCKS) in prcmu_clock_rate()
1613 return clock_rate(clock); in prcmu_clock_rate()
1614 else if (clock == PRCMU_TIMCLK) in prcmu_clock_rate()
1616 else if (clock == PRCMU_SYSCLK) in prcmu_clock_rate()
1618 else if (clock == PRCMU_PLLSOC0) in prcmu_clock_rate()
1620 else if (clock == PRCMU_PLLSOC1) in prcmu_clock_rate()
1622 else if (clock == PRCMU_ARMSS) in prcmu_clock_rate()
1624 else if (clock == PRCMU_PLLDDR) in prcmu_clock_rate()
1626 else if (clock == PRCMU_PLLDSI) in prcmu_clock_rate()
1629 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) in prcmu_clock_rate()
1630 return dsiclk_rate(clock - PRCMU_DSI0CLK); in prcmu_clock_rate()
1631 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) in prcmu_clock_rate()
1632 return dsiescclk_rate(clock - PRCMU_DSI0ESCCLK); in prcmu_clock_rate()
1664 static long round_clock_rate(u8 clock, unsigned long rate) in round_clock_rate() argument
1671 val = readl(prcmu_base + clk_mgt[clock].offset); in round_clock_rate()
1672 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), in round_clock_rate()
1673 clk_mgt[clock].branch); in round_clock_rate()
1676 if (clk_mgt[clock].clk38div) { in round_clock_rate()
1682 } else if ((clock == PRCMU_SGACLK) && (div == 3)) { in round_clock_rate()
1784 long prcmu_round_clock_rate(u8 clock, unsigned long rate) in prcmu_round_clock_rate() argument
1786 if (clock < PRCMU_NUM_REG_CLOCKS) in prcmu_round_clock_rate()
1787 return round_clock_rate(clock, rate); in prcmu_round_clock_rate()
1788 else if (clock == PRCMU_ARMSS) in prcmu_round_clock_rate()
1790 else if (clock == PRCMU_PLLDSI) in prcmu_round_clock_rate()
1792 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) in prcmu_round_clock_rate()
1794 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) in prcmu_round_clock_rate()
1797 return (long)prcmu_clock_rate(clock); in prcmu_round_clock_rate()
1800 static void set_clock_rate(u8 clock, unsigned long rate) in set_clock_rate() argument
1813 val = readl(prcmu_base + clk_mgt[clock].offset); in set_clock_rate()
1814 src_rate = clock_source_rate((val | clk_mgt[clock].pllsw), in set_clock_rate()
1815 clk_mgt[clock].branch); in set_clock_rate()
1818 if (clk_mgt[clock].clk38div) { in set_clock_rate()
1824 } else if (clock == PRCMU_SGACLK) { in set_clock_rate()
1841 writel(val, prcmu_base + clk_mgt[clock].offset); in set_clock_rate()
1946 int prcmu_set_clock_rate(u8 clock, unsigned long rate) in prcmu_set_clock_rate() argument
1948 if (clock < PRCMU_NUM_REG_CLOCKS) in prcmu_set_clock_rate()
1949 set_clock_rate(clock, rate); in prcmu_set_clock_rate()
1950 else if (clock == PRCMU_ARMSS) in prcmu_set_clock_rate()
1952 else if (clock == PRCMU_PLLDSI) in prcmu_set_clock_rate()
1954 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) in prcmu_set_clock_rate()
1955 set_dsiclk_rate((clock - PRCMU_DSI0CLK), rate); in prcmu_set_clock_rate()
1956 else if ((PRCMU_DSI0ESCCLK <= clock) && (clock <= PRCMU_DSI2ESCCLK)) in prcmu_set_clock_rate()
1957 set_dsiescclk_rate((clock - PRCMU_DSI0ESCCLK), rate); in prcmu_set_clock_rate()