Lines Matching refs:rb
57 static enum bfa_status bfa_ioc_ct_pll_init(void __iomem *rb,
59 static enum bfa_status bfa_ioc_ct2_pll_init(void __iomem *rb,
259 void __iomem *rb; in bfa_ioc_ct_reg_init() local
262 rb = bfa_ioc_bar0(ioc); in bfa_ioc_ct_reg_init()
264 ioc->ioc_regs.hfn_mbox = rb + ct_fnreg[pcifn].hfn_mbox; in bfa_ioc_ct_reg_init()
265 ioc->ioc_regs.lpu_mbox = rb + ct_fnreg[pcifn].lpu_mbox; in bfa_ioc_ct_reg_init()
266 ioc->ioc_regs.host_page_num_fn = rb + ct_fnreg[pcifn].hfn_pgn; in bfa_ioc_ct_reg_init()
269 ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG; in bfa_ioc_ct_reg_init()
270 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG; in bfa_ioc_ct_reg_init()
271 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG; in bfa_ioc_ct_reg_init()
272 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p0reg[pcifn].hfn; in bfa_ioc_ct_reg_init()
273 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p0reg[pcifn].lpu; in bfa_ioc_ct_reg_init()
274 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct_reg_init()
275 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct_reg_init()
277 ioc->ioc_regs.heartbeat = rb + BFA_IOC1_HBEAT_REG; in bfa_ioc_ct_reg_init()
278 ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC1_STATE_REG; in bfa_ioc_ct_reg_init()
279 ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC0_STATE_REG; in bfa_ioc_ct_reg_init()
280 ioc->ioc_regs.hfn_mbox_cmd = rb + ct_p1reg[pcifn].hfn; in bfa_ioc_ct_reg_init()
281 ioc->ioc_regs.lpu_mbox_cmd = rb + ct_p1reg[pcifn].lpu; in bfa_ioc_ct_reg_init()
282 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct_reg_init()
283 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct_reg_init()
289 ioc->ioc_regs.pss_ctl_reg = rb + PSS_CTL_REG; in bfa_ioc_ct_reg_init()
290 ioc->ioc_regs.pss_err_status_reg = rb + PSS_ERR_STATUS_REG; in bfa_ioc_ct_reg_init()
291 ioc->ioc_regs.app_pll_fast_ctl_reg = rb + APP_PLL_LCLK_CTL_REG; in bfa_ioc_ct_reg_init()
292 ioc->ioc_regs.app_pll_slow_ctl_reg = rb + APP_PLL_SCLK_CTL_REG; in bfa_ioc_ct_reg_init()
297 ioc->ioc_regs.ioc_sem_reg = rb + HOST_SEM0_REG; in bfa_ioc_ct_reg_init()
298 ioc->ioc_regs.ioc_usage_sem_reg = rb + HOST_SEM1_REG; in bfa_ioc_ct_reg_init()
299 ioc->ioc_regs.ioc_init_sem_reg = rb + HOST_SEM2_REG; in bfa_ioc_ct_reg_init()
300 ioc->ioc_regs.ioc_usage_reg = rb + BFA_FW_USE_COUNT; in bfa_ioc_ct_reg_init()
301 ioc->ioc_regs.ioc_fail_sync = rb + BFA_IOC_FAIL_SYNC; in bfa_ioc_ct_reg_init()
306 ioc->ioc_regs.smem_page_start = rb + PSS_SMEM_PAGE_START; in bfa_ioc_ct_reg_init()
312 ioc->ioc_regs.err_set = (rb + ERR_SET_REG); in bfa_ioc_ct_reg_init()
318 void __iomem *rb; in bfa_ioc_ct2_reg_init() local
321 rb = bfa_ioc_bar0(ioc); in bfa_ioc_ct2_reg_init()
323 ioc->ioc_regs.hfn_mbox = rb + ct2_reg[port].hfn_mbox; in bfa_ioc_ct2_reg_init()
324 ioc->ioc_regs.lpu_mbox = rb + ct2_reg[port].lpu_mbox; in bfa_ioc_ct2_reg_init()
325 ioc->ioc_regs.host_page_num_fn = rb + ct2_reg[port].hfn_pgn; in bfa_ioc_ct2_reg_init()
326 ioc->ioc_regs.hfn_mbox_cmd = rb + ct2_reg[port].hfn; in bfa_ioc_ct2_reg_init()
327 ioc->ioc_regs.lpu_mbox_cmd = rb + ct2_reg[port].lpu; in bfa_ioc_ct2_reg_init()
328 ioc->ioc_regs.lpu_read_stat = rb + ct2_reg[port].lpu_read; in bfa_ioc_ct2_reg_init()
331 ioc->ioc_regs.heartbeat = rb + CT2_BFA_IOC0_HBEAT_REG; in bfa_ioc_ct2_reg_init()
332 ioc->ioc_regs.ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG; in bfa_ioc_ct2_reg_init()
333 ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC1_STATE_REG; in bfa_ioc_ct2_reg_init()
334 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct2_reg_init()
335 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct2_reg_init()
337 ioc->ioc_regs.heartbeat = rb + CT2_BFA_IOC1_HBEAT_REG; in bfa_ioc_ct2_reg_init()
338 ioc->ioc_regs.ioc_fwstate = rb + CT2_BFA_IOC1_STATE_REG; in bfa_ioc_ct2_reg_init()
339 ioc->ioc_regs.alt_ioc_fwstate = rb + CT2_BFA_IOC0_STATE_REG; in bfa_ioc_ct2_reg_init()
340 ioc->ioc_regs.ll_halt = rb + FW_INIT_HALT_P1; in bfa_ioc_ct2_reg_init()
341 ioc->ioc_regs.alt_ll_halt = rb + FW_INIT_HALT_P0; in bfa_ioc_ct2_reg_init()
347 ioc->ioc_regs.pss_ctl_reg = rb + PSS_CTL_REG; in bfa_ioc_ct2_reg_init()
348 ioc->ioc_regs.pss_err_status_reg = rb + PSS_ERR_STATUS_REG; in bfa_ioc_ct2_reg_init()
349 ioc->ioc_regs.app_pll_fast_ctl_reg = rb + CT2_APP_PLL_LCLK_CTL_REG; in bfa_ioc_ct2_reg_init()
350 ioc->ioc_regs.app_pll_slow_ctl_reg = rb + CT2_APP_PLL_SCLK_CTL_REG; in bfa_ioc_ct2_reg_init()
355 ioc->ioc_regs.ioc_sem_reg = rb + CT2_HOST_SEM0_REG; in bfa_ioc_ct2_reg_init()
356 ioc->ioc_regs.ioc_usage_sem_reg = rb + CT2_HOST_SEM1_REG; in bfa_ioc_ct2_reg_init()
357 ioc->ioc_regs.ioc_init_sem_reg = rb + CT2_HOST_SEM2_REG; in bfa_ioc_ct2_reg_init()
358 ioc->ioc_regs.ioc_usage_reg = rb + CT2_BFA_FW_USE_COUNT; in bfa_ioc_ct2_reg_init()
359 ioc->ioc_regs.ioc_fail_sync = rb + CT2_BFA_IOC_FAIL_SYNC; in bfa_ioc_ct2_reg_init()
364 ioc->ioc_regs.smem_page_start = rb + PSS_SMEM_PAGE_START; in bfa_ioc_ct2_reg_init()
370 ioc->ioc_regs.err_set = rb + ERR_SET_REG; in bfa_ioc_ct2_reg_init()
379 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct_map_port() local
385 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_map_port()
394 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct2_map_port() local
397 r32 = readl(rb + CT2_HOSTFN_PERSONALITY0); in bfa_ioc_ct2_map_port()
405 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_ioc_ct_isr_mode_set() local
408 r32 = readl(rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
427 writel(r32, rb + FNC_PERS_REG); in bfa_ioc_ct_isr_mode_set()
455 void __iomem *rb = ioc->pcidev.pci_bar_kva; in bfa_nw_ioc_ct2_poweron() local
458 r32 = readl(rb + HOSTFN_MSIX_VT_OFST_NUMVT); in bfa_nw_ioc_ct2_poweron()
461 rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR); in bfa_nw_ioc_ct2_poweron()
467 rb + HOSTFN_MSIX_VT_OFST_NUMVT); in bfa_nw_ioc_ct2_poweron()
469 rb + HOSTFN_MSIX_VT_INDEX_MBOX_ERR); in bfa_nw_ioc_ct2_poweron()
609 bfa_ioc_ct_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode) in bfa_ioc_ct_pll_init() argument
624 writel(0, (rb + OP_MODE)); in bfa_ioc_ct_pll_init()
628 (rb + ETH_MAC_SER_REG)); in bfa_ioc_ct_pll_init()
630 writel(__GLOBAL_FCOE_MODE, (rb + OP_MODE)); in bfa_ioc_ct_pll_init()
632 (rb + ETH_MAC_SER_REG)); in bfa_ioc_ct_pll_init()
634 writel(BFI_IOC_UNINIT, (rb + BFA_IOC0_STATE_REG)); in bfa_ioc_ct_pll_init()
635 writel(BFI_IOC_UNINIT, (rb + BFA_IOC1_STATE_REG)); in bfa_ioc_ct_pll_init()
636 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); in bfa_ioc_ct_pll_init()
637 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); in bfa_ioc_ct_pll_init()
638 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); in bfa_ioc_ct_pll_init()
639 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); in bfa_ioc_ct_pll_init()
640 writel(0xffffffffU, (rb + HOSTFN0_INT_MSK)); in bfa_ioc_ct_pll_init()
641 writel(0xffffffffU, (rb + HOSTFN1_INT_MSK)); in bfa_ioc_ct_pll_init()
644 rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_pll_init()
647 rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_pll_init()
650 rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_pll_init()
653 rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_pll_init()
654 readl(rb + HOSTFN0_INT_MSK); in bfa_ioc_ct_pll_init()
656 writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS)); in bfa_ioc_ct_pll_init()
657 writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS)); in bfa_ioc_ct_pll_init()
660 rb + APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct_pll_init()
663 rb + APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct_pll_init()
666 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P0)); in bfa_ioc_ct_pll_init()
667 writel(__PMM_1T_RESET_P, (rb + PMM_1T_RESET_REG_P1)); in bfa_ioc_ct_pll_init()
669 r32 = readl(rb + PSS_CTL_REG); in bfa_ioc_ct_pll_init()
671 writel(r32, (rb + PSS_CTL_REG)); in bfa_ioc_ct_pll_init()
674 writel(0, (rb + PMM_1T_RESET_REG_P0)); in bfa_ioc_ct_pll_init()
675 writel(0, (rb + PMM_1T_RESET_REG_P1)); in bfa_ioc_ct_pll_init()
678 writel(__EDRAM_BISTR_START, (rb + MBIST_CTL_REG)); in bfa_ioc_ct_pll_init()
680 r32 = readl(rb + MBIST_STAT_REG); in bfa_ioc_ct_pll_init()
681 writel(0, (rb + MBIST_CTL_REG)); in bfa_ioc_ct_pll_init()
686 bfa_ioc_ct2_sclk_init(void __iomem *rb) in bfa_ioc_ct2_sclk_init() argument
693 r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_sclk_init()
697 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
703 r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_sclk_init()
705 writel(r32, (rb + CT2_APP_PLL_SCLK_CTL_REG)); in bfa_ioc_ct2_sclk_init()
710 r32 = readl(rb + CT2_CHIP_MISC_PRG); in bfa_ioc_ct2_sclk_init()
712 rb + CT2_CHIP_MISC_PRG); in bfa_ioc_ct2_sclk_init()
714 r32 = readl(rb + CT2_PCIE_MISC_REG); in bfa_ioc_ct2_sclk_init()
716 rb + CT2_PCIE_MISC_REG); in bfa_ioc_ct2_sclk_init()
721 r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_sclk_init()
724 writel(r32 | 0x1061731b, rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_sclk_init()
738 bfa_ioc_ct2_lclk_init(void __iomem *rb) in bfa_ioc_ct2_lclk_init() argument
745 r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_lclk_init()
749 writel(r32, rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_lclk_init()
754 r32 = readl(rb + CT2_CHIP_MISC_PRG); in bfa_ioc_ct2_lclk_init()
755 writel(r32, (rb + CT2_CHIP_MISC_PRG)); in bfa_ioc_ct2_lclk_init()
760 r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_lclk_init()
761 writel(r32, rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_lclk_init()
766 r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_lclk_init()
769 writel(r32, (rb + CT2_APP_PLL_LCLK_CTL_REG)); in bfa_ioc_ct2_lclk_init()
778 bfa_ioc_ct2_mem_init(void __iomem *rb) in bfa_ioc_ct2_mem_init() argument
782 r32 = readl(rb + PSS_CTL_REG); in bfa_ioc_ct2_mem_init()
784 writel(r32, rb + PSS_CTL_REG); in bfa_ioc_ct2_mem_init()
787 writel(__EDRAM_BISTR_START, rb + CT2_MBIST_CTL_REG); in bfa_ioc_ct2_mem_init()
789 writel(0, rb + CT2_MBIST_CTL_REG); in bfa_ioc_ct2_mem_init()
793 bfa_ioc_ct2_mac_reset(void __iomem *rb) in bfa_ioc_ct2_mac_reset() argument
797 bfa_ioc_ct2_sclk_init(rb); in bfa_ioc_ct2_mac_reset()
798 bfa_ioc_ct2_lclk_init(rb); in bfa_ioc_ct2_mac_reset()
803 r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_mac_reset()
805 rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_mac_reset()
810 r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_mac_reset()
812 rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_mac_reset()
816 rb + CT2_CSI_MAC_CONTROL_REG(0)); in bfa_ioc_ct2_mac_reset()
818 rb + CT2_CSI_MAC_CONTROL_REG(1)); in bfa_ioc_ct2_mac_reset()
826 bfa_ioc_ct2_nfc_halted(void __iomem *rb) in bfa_ioc_ct2_nfc_halted() argument
830 r32 = readl(rb + CT2_NFC_CSR_SET_REG); in bfa_ioc_ct2_nfc_halted()
838 bfa_ioc_ct2_nfc_resume(void __iomem *rb) in bfa_ioc_ct2_nfc_resume() argument
843 writel(__HALT_NFC_CONTROLLER, rb + CT2_NFC_CSR_CLR_REG); in bfa_ioc_ct2_nfc_resume()
845 r32 = readl(rb + CT2_NFC_CSR_SET_REG); in bfa_ioc_ct2_nfc_resume()
854 bfa_ioc_ct2_pll_init(void __iomem *rb, enum bfi_asic_mode asic_mode) in bfa_ioc_ct2_pll_init() argument
859 wgn = readl(rb + CT2_WGN_STATUS); in bfa_ioc_ct2_pll_init()
861 nfc_ver = readl(rb + CT2_RSC_GPR15_REG); in bfa_ioc_ct2_pll_init()
865 if (bfa_ioc_ct2_nfc_halted(rb)) in bfa_ioc_ct2_pll_init()
866 bfa_ioc_ct2_nfc_resume(rb); in bfa_ioc_ct2_pll_init()
868 rb + CT2_CSI_FW_CTL_SET_REG); in bfa_ioc_ct2_pll_init()
871 r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
878 r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
885 r32 = readl(rb + CT2_CSI_FW_CTL_REG); in bfa_ioc_ct2_pll_init()
888 writel(__HALT_NFC_CONTROLLER, (rb + CT2_NFC_CSR_SET_REG)); in bfa_ioc_ct2_pll_init()
890 r32 = readl(rb + CT2_NFC_CSR_SET_REG); in bfa_ioc_ct2_pll_init()
896 bfa_ioc_ct2_mac_reset(rb); in bfa_ioc_ct2_pll_init()
897 bfa_ioc_ct2_sclk_init(rb); in bfa_ioc_ct2_pll_init()
898 bfa_ioc_ct2_lclk_init(rb); in bfa_ioc_ct2_pll_init()
901 r32 = readl(rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
903 rb + CT2_APP_PLL_SCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
904 r32 = readl(rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
906 rb + CT2_APP_PLL_LCLK_CTL_REG); in bfa_ioc_ct2_pll_init()
911 r32 = readl(rb + PSS_GPIO_OUT_REG); in bfa_ioc_ct2_pll_init()
912 writel(r32 & ~1, rb + PSS_GPIO_OUT_REG); in bfa_ioc_ct2_pll_init()
913 r32 = readl(rb + PSS_GPIO_OE_REG); in bfa_ioc_ct2_pll_init()
914 writel(r32 | 1, rb + PSS_GPIO_OE_REG); in bfa_ioc_ct2_pll_init()
921 writel(1, rb + CT2_LPU0_HOSTFN_MBOX0_MSK); in bfa_ioc_ct2_pll_init()
922 writel(1, rb + CT2_LPU1_HOSTFN_MBOX0_MSK); in bfa_ioc_ct2_pll_init()
925 r32 = readl(rb + HOST_SEM5_REG); in bfa_ioc_ct2_pll_init()
927 r32 = readl(rb + CT2_LPU0_HOSTFN_CMD_STAT); in bfa_ioc_ct2_pll_init()
929 writel(1, rb + CT2_LPU0_HOSTFN_CMD_STAT); in bfa_ioc_ct2_pll_init()
930 readl(rb + CT2_LPU0_HOSTFN_CMD_STAT); in bfa_ioc_ct2_pll_init()
932 r32 = readl(rb + CT2_LPU1_HOSTFN_CMD_STAT); in bfa_ioc_ct2_pll_init()
934 writel(1, rb + CT2_LPU1_HOSTFN_CMD_STAT); in bfa_ioc_ct2_pll_init()
935 readl(rb + CT2_LPU1_HOSTFN_CMD_STAT); in bfa_ioc_ct2_pll_init()
939 bfa_ioc_ct2_mem_init(rb); in bfa_ioc_ct2_pll_init()
941 writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC0_STATE_REG); in bfa_ioc_ct2_pll_init()
942 writel(BFI_IOC_UNINIT, rb + CT2_BFA_IOC1_STATE_REG); in bfa_ioc_ct2_pll_init()