Lines Matching refs:adap
113 void t4_read_indirect(struct adapter *adap, unsigned int addr_reg, in t4_read_indirect() argument
118 t4_write_reg(adap, addr_reg, start_idx); in t4_read_indirect()
119 *vals++ = t4_read_reg(adap, data_reg); in t4_read_indirect()
136 void t4_write_indirect(struct adapter *adap, unsigned int addr_reg, in t4_write_indirect() argument
141 t4_write_reg(adap, addr_reg, start_idx++); in t4_write_indirect()
142 t4_write_reg(adap, data_reg, *vals++); in t4_write_indirect()
152 void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val) in t4_hw_pci_read_cfg4() argument
154 u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg); in t4_hw_pci_read_cfg4()
156 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) in t4_hw_pci_read_cfg4()
161 if (is_t4(adap->params.chip)) in t4_hw_pci_read_cfg4()
164 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req); in t4_hw_pci_read_cfg4()
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A); in t4_hw_pci_read_cfg4()
172 t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0); in t4_hw_pci_read_cfg4()
183 static void t4_report_fw_error(struct adapter *adap) in t4_report_fw_error() argument
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A); in t4_report_fw_error()
199 dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n", in t4_report_fw_error()
206 static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit, in get_mbox_rpl() argument
210 *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr)); in get_mbox_rpl()
216 static void fw_asrt(struct adapter *adap, u32 mbox_addr) in fw_asrt() argument
220 get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr); in fw_asrt()
221 dev_alert(adap->pdev_dev, in fw_asrt()
280 int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd, in t4_wr_mbox_meat_timeout() argument
306 if (adap->pdev->error_state != pci_channel_io_normal) in t4_wr_mbox_meat_timeout()
320 spin_lock(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
321 list_add_tail(&entry.list, &adap->mlist.list); in t4_wr_mbox_meat_timeout()
322 spin_unlock(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
333 pcie_fw = t4_read_reg(adap, PCIE_FW_A); in t4_wr_mbox_meat_timeout()
335 spin_lock(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
337 spin_unlock(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
339 t4_record_mbox(adap, cmd, size, access, ret); in t4_wr_mbox_meat_timeout()
346 if (list_first_entry(&adap->mlist.list, struct mbox_list, in t4_wr_mbox_meat_timeout()
364 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); in t4_wr_mbox_meat_timeout()
366 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); in t4_wr_mbox_meat_timeout()
368 spin_lock(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
370 spin_unlock(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
372 t4_record_mbox(adap, cmd, size, access, ret); in t4_wr_mbox_meat_timeout()
377 t4_record_mbox(adap, cmd, size, access, 0); in t4_wr_mbox_meat_timeout()
379 t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++)); in t4_wr_mbox_meat_timeout()
381 t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW)); in t4_wr_mbox_meat_timeout()
382 t4_read_reg(adap, ctl_reg); /* flush write */ in t4_wr_mbox_meat_timeout()
388 !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) && in t4_wr_mbox_meat_timeout()
399 v = t4_read_reg(adap, ctl_reg); in t4_wr_mbox_meat_timeout()
402 t4_write_reg(adap, ctl_reg, 0); in t4_wr_mbox_meat_timeout()
406 get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg); in t4_wr_mbox_meat_timeout()
410 fw_asrt(adap, data_reg); in t4_wr_mbox_meat_timeout()
416 t4_write_reg(adap, ctl_reg, 0); in t4_wr_mbox_meat_timeout()
419 t4_record_mbox(adap, cmd_rpl, in t4_wr_mbox_meat_timeout()
421 spin_lock(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
423 spin_unlock(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
429 t4_record_mbox(adap, cmd, size, access, ret); in t4_wr_mbox_meat_timeout()
430 dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n", in t4_wr_mbox_meat_timeout()
432 t4_report_fw_error(adap); in t4_wr_mbox_meat_timeout()
433 spin_lock(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
435 spin_unlock(&adap->mbox_lock); in t4_wr_mbox_meat_timeout()
436 t4_fatal_err(adap); in t4_wr_mbox_meat_timeout()
440 int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size, in t4_wr_mbox_meat() argument
443 return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok, in t4_wr_mbox_meat()
447 static int t4_edc_err_read(struct adapter *adap, int idx) in t4_edc_err_read() argument
452 if (is_t4(adap->params.chip)) { in t4_edc_err_read()
453 CH_WARN(adap, "%s: T4 NOT supported.\n", __func__); in t4_edc_err_read()
457 CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx); in t4_edc_err_read()
464 CH_WARN(adap, in t4_edc_err_read()
467 t4_read_reg(adap, edc_ecc_err_addr_reg)); in t4_edc_err_read()
468 CH_WARN(adap, in t4_edc_err_read()
471 (unsigned long long)t4_read_reg64(adap, rdata_reg), in t4_edc_err_read()
472 (unsigned long long)t4_read_reg64(adap, rdata_reg + 8), in t4_edc_err_read()
473 (unsigned long long)t4_read_reg64(adap, rdata_reg + 16), in t4_edc_err_read()
474 (unsigned long long)t4_read_reg64(adap, rdata_reg + 24), in t4_edc_err_read()
475 (unsigned long long)t4_read_reg64(adap, rdata_reg + 32), in t4_edc_err_read()
476 (unsigned long long)t4_read_reg64(adap, rdata_reg + 40), in t4_edc_err_read()
477 (unsigned long long)t4_read_reg64(adap, rdata_reg + 48), in t4_edc_err_read()
478 (unsigned long long)t4_read_reg64(adap, rdata_reg + 56), in t4_edc_err_read()
479 (unsigned long long)t4_read_reg64(adap, rdata_reg + 64)); in t4_edc_err_read()
501 int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr, in t4_memory_rw() argument
528 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A)); in t4_memory_rw()
532 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap, in t4_memory_rw()
548 mem_reg = t4_read_reg(adap, in t4_memory_rw()
553 if (is_t4(adap->params.chip)) in t4_memory_rw()
554 mem_base -= adap->t4_bar0; in t4_memory_rw()
555 win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf); in t4_memory_rw()
567 t4_write_reg(adap, in t4_memory_rw()
570 t4_read_reg(adap, in t4_memory_rw()
609 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap, in t4_memory_rw()
612 t4_write_reg(adap, mem_base + offset, in t4_memory_rw()
626 t4_write_reg(adap, in t4_memory_rw()
629 t4_read_reg(adap, in t4_memory_rw()
650 (__force __le32)t4_read_reg(adap, in t4_memory_rw()
658 t4_write_reg(adap, mem_base + offset, in t4_memory_rw()
671 u32 t4_read_pcie_cfg4(struct adapter *adap, int reg) in t4_read_pcie_cfg4() argument
690 (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf)); in t4_read_pcie_cfg4()
696 ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd), in t4_read_pcie_cfg4()
704 t4_hw_pci_read_cfg4(adap, reg, &val); in t4_read_pcie_cfg4()
712 static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask, in t4_get_window() argument
717 if (is_t4(adap->params.chip)) { in t4_get_window()
729 bar0 = t4_read_pcie_cfg4(adap, pci_base); in t4_get_window()
731 adap->t4_bar0 = bar0; in t4_get_window()
742 u32 t4_get_util_window(struct adapter *adap) in t4_get_util_window() argument
744 return t4_get_window(adap, PCI_BASE_ADDRESS_0, in t4_get_util_window()
752 void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window) in t4_setup_memwin() argument
754 t4_write_reg(adap, in t4_setup_memwin()
758 t4_read_reg(adap, in t4_setup_memwin()
796 void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size) in t4_get_regs() argument
2588 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); in t4_get_regs()
2610 dev_err(adap->pdev_dev, in t4_get_regs()
2628 *bufp++ = t4_read_reg(adap, reg); in t4_get_regs()
3042 int t4_get_exprom_version(struct adapter *adap, u32 *vers) in t4_get_exprom_version() argument
3052 ret = t4_read_flash(adap, FLASH_EXP_ROM_START, in t4_get_exprom_version()
3250 int t4_check_fw_version(struct adapter *adap) in t4_check_fw_version() argument
3254 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); in t4_check_fw_version()
3256 ret = t4_get_fw_version(adap, &adap->params.fw_vers); in t4_check_fw_version()
3259 ret = t4_get_fw_version(adap, &adap->params.fw_vers); in t4_check_fw_version()
3264 major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers); in t4_check_fw_version()
3265 minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers); in t4_check_fw_version()
3266 micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers); in t4_check_fw_version()
3285 dev_err(adap->pdev_dev, "Unsupported chip type, %x\n", in t4_check_fw_version()
3286 adap->chip); in t4_check_fw_version()
3292 dev_err(adap->pdev_dev, in t4_check_fw_version()
3324 static int should_install_fs_fw(struct adapter *adap, int card_fw_usable, in should_install_fs_fw() argument
3342 dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, " in should_install_fs_fw()
3352 int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info, in t4_prep_fw() argument
3364 ret = -t4_read_flash(adap, FLASH_FW_START, in t4_prep_fw()
3370 dev_err(adap->pdev_dev, in t4_prep_fw()
3390 should_install_fs_fw(adap, card_fw_usable, in t4_prep_fw()
3393 ret = -t4_fw_upgrade(adap, adap->mbox, fw_data, in t4_prep_fw()
3396 dev_err(adap->pdev_dev, in t4_prep_fw()
3414 dev_err(adap->pdev_dev, "Cannot find a usable firmware: " in t4_prep_fw()
3430 adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver); in t4_prep_fw()
3431 adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver); in t4_prep_fw()
3488 static bool t4_fw_matches_chip(const struct adapter *adap, in t4_fw_matches_chip() argument
3494 if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) || in t4_fw_matches_chip()
3495 (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) || in t4_fw_matches_chip()
3496 (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6)) in t4_fw_matches_chip()
3499 dev_err(adap->pdev_dev, in t4_fw_matches_chip()
3501 hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip)); in t4_fw_matches_chip()
3513 int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) in t4_load_fw() argument
3521 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; in t4_load_fw()
3522 unsigned int fw_img_start = adap->params.sf_fw_start; in t4_load_fw()
3526 dev_err(adap->pdev_dev, "FW image has no data\n"); in t4_load_fw()
3530 dev_err(adap->pdev_dev, in t4_load_fw()
3535 dev_err(adap->pdev_dev, in t4_load_fw()
3540 dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n", in t4_load_fw()
3544 if (!t4_fw_matches_chip(adap, hdr)) in t4_load_fw()
3551 dev_err(adap->pdev_dev, in t4_load_fw()
3557 ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1); in t4_load_fw()
3568 ret = t4_write_flash(adap, fw_img_start, SF_PAGE_SIZE, first_page); in t4_load_fw()
3576 ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data); in t4_load_fw()
3581 ret = t4_write_flash(adap, in t4_load_fw()
3586 dev_err(adap->pdev_dev, "firmware download failed, error %d\n", in t4_load_fw()
3589 ret = t4_get_fw_version(adap, &adap->params.fw_vers); in t4_load_fw()
3601 int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver) in t4_phy_fw_ver() argument
3608 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | in t4_phy_fw_ver()
3610 ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1, in t4_phy_fw_ver()
3645 int t4_load_phy_fw(struct adapter *adap, in t4_load_phy_fw() argument
3660 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver); in t4_load_phy_fw()
3665 CH_WARN(adap, "PHY Firmware already up-to-date, " in t4_load_phy_fw()
3679 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | in t4_load_phy_fw()
3682 ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1, in t4_load_phy_fw()
3694 ret = t4_memory_rw(adap, win, mtype, maddr, in t4_load_phy_fw()
3709 FW_PARAMS_PARAM_Y_V(adap->params.portvec) | in t4_load_phy_fw()
3711 ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1, in t4_load_phy_fw()
3718 ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver); in t4_load_phy_fw()
3723 CH_WARN(adap, "PHY Firmware did not update: " in t4_load_phy_fw()
3739 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op) in t4_fwcache() argument
3747 FW_PARAMS_CMD_PFN_V(adap->pf) | in t4_fwcache()
3755 return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL); in t4_fwcache()
3758 void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp, in t4_cim_read_pif_la() argument
3765 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A); in t4_cim_read_pif_la()
3767 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F); in t4_cim_read_pif_la()
3769 val = t4_read_reg(adap, CIM_DEBUGSTS_A); in t4_cim_read_pif_la()
3779 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) | in t4_cim_read_pif_la()
3781 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A); in t4_cim_read_pif_la()
3782 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A); in t4_cim_read_pif_la()
3789 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg); in t4_cim_read_pif_la()
3792 void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp) in t4_cim_read_ma_la() argument
3797 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A); in t4_cim_read_ma_la()
3799 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F); in t4_cim_read_ma_la()
3804 t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) | in t4_cim_read_ma_la()
3806 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A); in t4_cim_read_ma_la()
3807 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A); in t4_cim_read_ma_la()
3810 t4_write_reg(adap, CIM_DEBUGCFG_A, cfg); in t4_cim_read_ma_la()
3813 void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf) in t4_ulprx_read_la() argument
3820 t4_write_reg(adap, ULP_RX_LA_CTL_A, i); in t4_ulprx_read_la()
3821 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A); in t4_ulprx_read_la()
3822 t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j); in t4_ulprx_read_la()
3824 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A); in t4_ulprx_read_la()
4041 int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port) in t4_restart_aneg() argument
4053 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_restart_aneg()
4056 typedef void (*int_handler_t)(struct adapter *adap);
4493 static void le_intr_handler(struct adapter *adap) in le_intr_handler() argument
4495 enum chip_type chip = CHELSIO_CHIP_VERSION(adap->params.chip); in le_intr_handler()
4514 if (t4_handle_intr_status(adap, LE_DB_INT_CAUSE_A, in le_intr_handler()
4517 t4_fatal_err(adap); in le_intr_handler()
4659 static void ma_intr_handler(struct adapter *adap) in ma_intr_handler() argument
4661 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A); in ma_intr_handler()
4664 dev_alert(adap->pdev_dev, in ma_intr_handler()
4666 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A)); in ma_intr_handler()
4667 if (is_t5(adap->params.chip)) in ma_intr_handler()
4668 dev_alert(adap->pdev_dev, in ma_intr_handler()
4670 t4_read_reg(adap, in ma_intr_handler()
4674 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A); in ma_intr_handler()
4675 dev_alert(adap->pdev_dev, "MA address wrap-around error by " in ma_intr_handler()
4680 t4_write_reg(adap, MA_INT_CAUSE_A, status); in ma_intr_handler()
4681 t4_fatal_err(adap); in ma_intr_handler()
4687 static void smb_intr_handler(struct adapter *adap) in smb_intr_handler() argument
4696 if (t4_handle_intr_status(adap, SMB_INT_CAUSE_A, smb_intr_info)) in smb_intr_handler()
4697 t4_fatal_err(adap); in smb_intr_handler()
4703 static void ncsi_intr_handler(struct adapter *adap) in ncsi_intr_handler() argument
4713 if (t4_handle_intr_status(adap, NCSI_INT_CAUSE_A, ncsi_intr_info)) in ncsi_intr_handler()
4714 t4_fatal_err(adap); in ncsi_intr_handler()
4720 static void xgmac_intr_handler(struct adapter *adap, int port) in xgmac_intr_handler() argument
4724 if (is_t4(adap->params.chip)) in xgmac_intr_handler()
4729 v = t4_read_reg(adap, int_cause_reg); in xgmac_intr_handler()
4736 dev_alert(adap->pdev_dev, "XGMAC %d Tx FIFO parity error\n", in xgmac_intr_handler()
4739 dev_alert(adap->pdev_dev, "XGMAC %d Rx FIFO parity error\n", in xgmac_intr_handler()
4741 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE_A), v); in xgmac_intr_handler()
4742 t4_fatal_err(adap); in xgmac_intr_handler()
4748 static void pl_intr_handler(struct adapter *adap) in pl_intr_handler() argument
4756 if (t4_handle_intr_status(adap, PL_PL_INT_CAUSE_A, pl_intr_info)) in pl_intr_handler()
4757 t4_fatal_err(adap); in pl_intr_handler()
5010 static int rd_rss_row(struct adapter *adap, int row, u32 *val) in rd_rss_row() argument
5012 t4_write_reg(adap, TP_RSS_LKP_TABLE_A, 0xfff00000 | row); in rd_rss_row()
5013 return t4_wait_op_done_val(adap, TP_RSS_LKP_TABLE_A, LKPTBLROWVLD_F, 1, in rd_rss_row()
5039 static unsigned int t4_use_ldst(struct adapter *adap) in t4_use_ldst() argument
5041 return (adap->flags & FW_OK) || !adap->use_bd; in t4_use_ldst()
5054 static void t4_fw_tp_pio_rw(struct adapter *adap, u32 *vals, unsigned int nregs, in t4_fw_tp_pio_rw() argument
5072 ret = t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), &c); in t4_fw_tp_pio_rw()
5085 void t4_read_rss_key(struct adapter *adap, u32 *key) in t4_read_rss_key() argument
5087 if (t4_use_ldst(adap)) in t4_read_rss_key()
5088 t4_fw_tp_pio_rw(adap, key, 10, TP_RSS_SECRET_KEY0_A, 1); in t4_read_rss_key()
5090 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10, in t4_read_rss_key()
5104 void t4_write_rss_key(struct adapter *adap, const u32 *key, int idx) in t4_write_rss_key() argument
5107 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A); in t4_write_rss_key()
5113 if ((CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) && in t4_write_rss_key()
5117 if (t4_use_ldst(adap)) in t4_write_rss_key()
5118 t4_fw_tp_pio_rw(adap, (void *)key, 10, TP_RSS_SECRET_KEY0_A, 0); in t4_write_rss_key()
5120 t4_write_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, key, 10, in t4_write_rss_key()
5125 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A, in t4_write_rss_key()
5129 t4_write_reg(adap, TP_RSS_CONFIG_VRT_A, in t4_write_rss_key()
5242 void t4_tp_get_tcp_stats(struct adapter *adap, struct tp_tcp_stats *v4, in t4_tp_get_tcp_stats() argument
5252 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, in t4_tp_get_tcp_stats()
5260 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, in t4_tp_get_tcp_stats()
5279 void t4_tp_get_err_stats(struct adapter *adap, struct tp_err_stats *st) in t4_tp_get_err_stats() argument
5281 int nchan = adap->params.arch.nchan; in t4_tp_get_err_stats()
5283 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, in t4_tp_get_err_stats()
5285 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, in t4_tp_get_err_stats()
5287 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, in t4_tp_get_err_stats()
5289 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, in t4_tp_get_err_stats()
5291 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, in t4_tp_get_err_stats()
5293 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, in t4_tp_get_err_stats()
5295 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, in t4_tp_get_err_stats()
5297 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, in t4_tp_get_err_stats()
5300 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, in t4_tp_get_err_stats()
5311 void t4_tp_get_cpl_stats(struct adapter *adap, struct tp_cpl_stats *st) in t4_tp_get_cpl_stats() argument
5313 int nchan = adap->params.arch.nchan; in t4_tp_get_cpl_stats()
5315 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->req, in t4_tp_get_cpl_stats()
5317 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, st->rsp, in t4_tp_get_cpl_stats()
5329 void t4_tp_get_rdma_stats(struct adapter *adap, struct tp_rdma_stats *st) in t4_tp_get_rdma_stats() argument
5331 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->rqe_dfr_pkt, in t4_tp_get_rdma_stats()
5343 void t4_get_fcoe_stats(struct adapter *adap, unsigned int idx, in t4_get_fcoe_stats() argument
5348 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_ddp, in t4_get_fcoe_stats()
5350 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, &st->frames_drop, in t4_get_fcoe_stats()
5352 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, in t4_get_fcoe_stats()
5364 void t4_get_usm_stats(struct adapter *adap, struct tp_usm_stats *st) in t4_get_usm_stats() argument
5368 t4_read_indirect(adap, TP_MIB_INDEX_A, TP_MIB_DATA_A, val, 4, in t4_get_usm_stats()
5383 void t4_read_mtu_tbl(struct adapter *adap, u16 *mtus, u8 *mtu_log) in t4_read_mtu_tbl() argument
5389 t4_write_reg(adap, TP_MTU_TABLE_A, in t4_read_mtu_tbl()
5391 v = t4_read_reg(adap, TP_MTU_TABLE_A); in t4_read_mtu_tbl()
5406 void t4_read_cong_tbl(struct adapter *adap, u16 incr[NMTUS][NCCTRL_WIN]) in t4_read_cong_tbl() argument
5412 t4_write_reg(adap, TP_CCTRL_TABLE_A, in t4_read_cong_tbl()
5414 incr[mtu][w] = (u16)t4_read_reg(adap, in t4_read_cong_tbl()
5428 void t4_tp_wr_bits_indirect(struct adapter *adap, unsigned int addr, in t4_tp_wr_bits_indirect() argument
5431 t4_write_reg(adap, TP_PIO_ADDR_A, addr); in t4_tp_wr_bits_indirect()
5432 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask; in t4_tp_wr_bits_indirect()
5433 t4_write_reg(adap, TP_PIO_DATA_A, val); in t4_tp_wr_bits_indirect()
5495 void t4_load_mtus(struct adapter *adap, const unsigned short *mtus, in t4_load_mtus() argument
5512 t4_write_reg(adap, TP_MTU_TABLE_A, MTUINDEX_V(i) | in t4_load_mtus()
5521 t4_write_reg(adap, TP_CCTRL_TABLE_A, (i << 21) | in t4_load_mtus()
5536 static u64 chan_rate(struct adapter *adap, unsigned int bytes256) in chan_rate() argument
5538 u64 v = bytes256 * adap->params.vpd.cclk; in chan_rate()
5552 void t4_get_chan_txrate(struct adapter *adap, u64 *nic_rate, u64 *ofld_rate) in t4_get_chan_txrate() argument
5556 v = t4_read_reg(adap, TP_TX_TRATE_A); in t4_get_chan_txrate()
5557 nic_rate[0] = chan_rate(adap, TNLRATE0_G(v)); in t4_get_chan_txrate()
5558 nic_rate[1] = chan_rate(adap, TNLRATE1_G(v)); in t4_get_chan_txrate()
5559 if (adap->params.arch.nchan == NCHAN) { in t4_get_chan_txrate()
5560 nic_rate[2] = chan_rate(adap, TNLRATE2_G(v)); in t4_get_chan_txrate()
5561 nic_rate[3] = chan_rate(adap, TNLRATE3_G(v)); in t4_get_chan_txrate()
5564 v = t4_read_reg(adap, TP_TX_ORATE_A); in t4_get_chan_txrate()
5565 ofld_rate[0] = chan_rate(adap, OFDRATE0_G(v)); in t4_get_chan_txrate()
5566 ofld_rate[1] = chan_rate(adap, OFDRATE1_G(v)); in t4_get_chan_txrate()
5567 if (adap->params.arch.nchan == NCHAN) { in t4_get_chan_txrate()
5568 ofld_rate[2] = chan_rate(adap, OFDRATE2_G(v)); in t4_get_chan_txrate()
5569 ofld_rate[3] = chan_rate(adap, OFDRATE3_G(v)); in t4_get_chan_txrate()
5584 int t4_set_trace_filter(struct adapter *adap, const struct trace_params *tp, in t4_set_trace_filter() argument
5592 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0); in t4_set_trace_filter()
5596 cfg = t4_read_reg(adap, MPS_TRC_CFG_A); in t4_set_trace_filter()
5614 if (tp->port > (is_t4(adap->params.chip) ? 11 : 19) || tp->invert > 1 || in t4_set_trace_filter()
5620 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, 0); in t4_set_trace_filter()
5627 t4_write_reg(adap, data_reg, tp->data[i]); in t4_set_trace_filter()
5628 t4_write_reg(adap, mask_reg, ~tp->mask[i]); in t4_set_trace_filter()
5630 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst, in t4_set_trace_filter()
5633 t4_write_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst, in t4_set_trace_filter()
5635 (is_t4(adap->params.chip) ? in t4_set_trace_filter()
5652 void t4_get_trace_filter(struct adapter *adap, struct trace_params *tp, int idx, in t4_get_trace_filter() argument
5659 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst); in t4_get_trace_filter()
5660 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst); in t4_get_trace_filter()
5662 if (is_t4(adap->params.chip)) { in t4_get_trace_filter()
5681 tp->mask[i] = ~t4_read_reg(adap, mask_reg); in t4_get_trace_filter()
5682 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; in t4_get_trace_filter()
5694 void t4_pmtx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) in t4_pmtx_get_stats() argument
5699 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) { in t4_pmtx_get_stats()
5700 t4_write_reg(adap, PM_TX_STAT_CONFIG_A, i + 1); in t4_pmtx_get_stats()
5701 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A); in t4_pmtx_get_stats()
5702 if (is_t4(adap->params.chip)) { in t4_pmtx_get_stats()
5703 cycles[i] = t4_read_reg64(adap, PM_TX_STAT_LSB_A); in t4_pmtx_get_stats()
5705 t4_read_indirect(adap, PM_TX_DBG_CTRL_A, in t4_pmtx_get_stats()
5721 void t4_pmrx_get_stats(struct adapter *adap, u32 cnt[], u64 cycles[]) in t4_pmrx_get_stats() argument
5726 for (i = 0; i < adap->params.arch.pm_stats_cnt; i++) { in t4_pmrx_get_stats()
5727 t4_write_reg(adap, PM_RX_STAT_CONFIG_A, i + 1); in t4_pmrx_get_stats()
5728 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A); in t4_pmrx_get_stats()
5729 if (is_t4(adap->params.chip)) { in t4_pmrx_get_stats()
5730 cycles[i] = t4_read_reg64(adap, PM_RX_STAT_LSB_A); in t4_pmrx_get_stats()
5732 t4_read_indirect(adap, PM_RX_DBG_CTRL_A, in t4_pmrx_get_stats()
5855 unsigned int t4_get_tp_ch_map(struct adapter *adap, int pidx) in t4_get_tp_ch_map() argument
5857 unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip); in t4_get_tp_ch_map()
5858 unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A)); in t4_get_tp_ch_map()
5861 dev_warn(adap->pdev_dev, "TP Port Index %d >= Nports %d\n", in t4_get_tp_ch_map()
5887 dev_err(adap->pdev_dev, "Need TP Channel Map for Chip %0x, Nports %d\n", in t4_get_tp_ch_map()
5936 void t4_get_port_stats_offset(struct adapter *adap, int idx, in t4_get_port_stats_offset() argument
5943 t4_get_port_stats(adap, idx, stats); in t4_get_port_stats_offset()
5958 void t4_get_port_stats(struct adapter *adap, int idx, struct port_stats *p) in t4_get_port_stats() argument
5960 u32 bgmap = t4_get_mps_bg_map(adap, idx); in t4_get_port_stats()
5961 u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A); in t4_get_port_stats()
5964 t4_read_reg64(adap, \ in t4_get_port_stats()
5965 (is_t4(adap->params.chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \ in t4_get_port_stats()
5967 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L) in t4_get_port_stats()
5993 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) { in t4_get_port_stats()
6027 if (CHELSIO_CHIP_VERSION(adap->params.chip) >= CHELSIO_T5) { in t4_get_port_stats()
6055 void t4_get_lb_stats(struct adapter *adap, int idx, struct lb_port_stats *p) in t4_get_lb_stats() argument
6057 u32 bgmap = t4_get_mps_bg_map(adap, idx); in t4_get_lb_stats()
6060 t4_read_reg64(adap, \ in t4_get_lb_stats()
6061 (is_t4(adap->params.chip) ? \ in t4_get_lb_stats()
6064 #define GET_STAT_COM(name) t4_read_reg64(adap, MPS_STAT_##name##_L) in t4_get_lb_stats()
6123 int t4_fwaddrspace_write(struct adapter *adap, unsigned int mbox, in t4_fwaddrspace_write() argument
6139 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_fwaddrspace_write()
6153 int t4_mdio_rd(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, in t4_mdio_rd() argument
6170 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_mdio_rd()
6187 int t4_mdio_wr(struct adapter *adap, unsigned int mbox, unsigned int phy_addr, in t4_mdio_wr() argument
6204 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_mdio_wr()
6380 int t4_sge_ctxt_flush(struct adapter *adap, unsigned int mbox) in t4_sge_ctxt_flush() argument
6394 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_sge_ctxt_flush()
6409 int t4_fw_hello(struct adapter *adap, unsigned int mbox, unsigned int evt_mbox, in t4_fw_hello() argument
6437 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_fw_hello()
6441 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F) in t4_fw_hello()
6442 t4_report_fw_error(adap); in t4_fw_hello()
6491 pcie_fw = t4_read_reg(adap, PCIE_FW_A); in t4_fw_hello()
6535 int t4_fw_bye(struct adapter *adap, unsigned int mbox) in t4_fw_bye() argument
6541 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_fw_bye()
6552 int t4_early_init(struct adapter *adap, unsigned int mbox) in t4_early_init() argument
6558 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_early_init()
6569 int t4_fw_reset(struct adapter *adap, unsigned int mbox, int reset) in t4_fw_reset() argument
6576 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_fw_reset()
6595 static int t4_fw_halt(struct adapter *adap, unsigned int mbox, int force) in t4_fw_halt() argument
6610 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_fw_halt()
6627 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, UPCRST_F); in t4_fw_halt()
6628 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, in t4_fw_halt()
6660 static int t4_fw_restart(struct adapter *adap, unsigned int mbox, int reset) in t4_fw_restart() argument
6668 t4_set_reg_field(adap, PCIE_FW_A, PCIE_FW_HALT_F, 0); in t4_fw_restart()
6678 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0); in t4_fw_restart()
6680 if (t4_fw_reset(adap, mbox, in t4_fw_restart()
6685 t4_write_reg(adap, PL_RST_A, PIORST_F | PIORSTMODE_F); in t4_fw_restart()
6690 t4_set_reg_field(adap, CIM_BOOT_CFG_A, UPCRST_F, 0); in t4_fw_restart()
6692 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F)) in t4_fw_restart()
6723 int t4_fw_upgrade(struct adapter *adap, unsigned int mbox, in t4_fw_upgrade() argument
6729 if (!t4_fw_matches_chip(adap, fw_hdr)) in t4_fw_upgrade()
6735 adap->flags &= ~FW_OK; in t4_fw_upgrade()
6737 ret = t4_fw_halt(adap, mbox, force); in t4_fw_upgrade()
6741 ret = t4_load_fw(adap, fw_data, size); in t4_fw_upgrade()
6754 (void)t4_load_cfg(adap, NULL, 0); in t4_fw_upgrade()
6765 ret = t4_fw_restart(adap, mbox, reset); in t4_fw_upgrade()
6772 (void)t4_init_devlog_params(adap); in t4_fw_upgrade()
6774 adap->flags |= FW_OK; in t4_fw_upgrade()
6787 int t4_fl_pkt_align(struct adapter *adap) in t4_fl_pkt_align() argument
6792 sge_control = t4_read_reg(adap, SGE_CONTROL_A); in t4_fl_pkt_align()
6806 if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5) in t4_fl_pkt_align()
6814 if (!is_t4(adap->params.chip)) { in t4_fl_pkt_align()
6818 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A); in t4_fl_pkt_align()
6841 int t4_fixup_host_params(struct adapter *adap, unsigned int page_size, in t4_fixup_host_params() argument
6850 t4_write_reg(adap, SGE_HOST_PAGE_SIZE_A, in t4_fixup_host_params()
6860 if (is_t4(adap->params.chip)) { in t4_fixup_host_params()
6861 t4_set_reg_field(adap, SGE_CONTROL_A, in t4_fixup_host_params()
6895 pcie_cap = pci_find_capability(adap->pdev, PCI_CAP_ID_EXP); in t4_fixup_host_params()
6904 pci_read_config_word(adap->pdev, in t4_fixup_host_params()
6936 if (is_t5(adap->params.chip)) in t4_fixup_host_params()
6941 t4_set_reg_field(adap, SGE_CONTROL_A, in t4_fixup_host_params()
6946 t4_set_reg_field(adap, SGE_CONTROL2_A, in t4_fixup_host_params()
6971 t4_write_reg(adap, SGE_FL_BUFFER_SIZE0_A, page_size); in t4_fixup_host_params()
6972 t4_write_reg(adap, SGE_FL_BUFFER_SIZE2_A, in t4_fixup_host_params()
6973 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1) in t4_fixup_host_params()
6975 t4_write_reg(adap, SGE_FL_BUFFER_SIZE3_A, in t4_fixup_host_params()
6976 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1) in t4_fixup_host_params()
6979 t4_write_reg(adap, ULP_RX_TDDP_PSZ_A, HPZ0_V(page_shift - 12)); in t4_fixup_host_params()
6992 int t4_fw_initialize(struct adapter *adap, unsigned int mbox) in t4_fw_initialize() argument
6998 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_fw_initialize()
7016 int t4_query_params_rw(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_query_params_rw() argument
7041 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); in t4_query_params_rw()
7048 int t4_query_params(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_query_params() argument
7052 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0, in t4_query_params()
7056 int t4_query_params_ns(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_query_params_ns() argument
7060 return t4_query_params_rw(adap, mbox, pf, vf, nparams, params, val, 0, in t4_query_params_ns()
7078 int t4_set_params_timeout(struct adapter *adap, unsigned int mbox, in t4_set_params_timeout() argument
7101 return t4_wr_mbox_timeout(adap, mbox, &c, sizeof(c), NULL, timeout); in t4_set_params_timeout()
7117 int t4_set_params(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_set_params() argument
7121 return t4_set_params_timeout(adap, mbox, pf, vf, nparams, params, val, in t4_set_params()
7146 int t4_cfg_pfvf(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_cfg_pfvf() argument
7170 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_cfg_pfvf()
7190 int t4_alloc_vi(struct adapter *adap, unsigned int mbox, unsigned int port, in t4_alloc_vi() argument
7205 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_alloc_vi()
7237 int t4_free_vi(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_free_vi() argument
7251 return t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_free_vi()
7268 int t4_set_rxmode(struct adapter *adap, unsigned int mbox, unsigned int viid, in t4_set_rxmode() argument
7297 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); in t4_set_rxmode()
7322 int t4_alloc_mac_filt(struct adapter *adap, unsigned int mbox, in t4_alloc_mac_filt() argument
7329 unsigned int max_naddr = adap->params.arch.mps_tcam_size; in t4_alloc_mac_filt()
7366 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); in t4_alloc_mac_filt()
7407 int t4_free_mac_filt(struct adapter *adap, unsigned int mbox, in t4_free_mac_filt() argument
7414 unsigned int max_naddr = is_t4(adap->params.chip) ? in t4_free_mac_filt()
7448 ret = t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), &c, sleep_ok); in t4_free_mac_filt()
7488 int t4_change_mac(struct adapter *adap, unsigned int mbox, unsigned int viid, in t4_change_mac() argument
7494 unsigned int max_mac_addr = adap->params.arch.mps_tcam_size; in t4_change_mac()
7510 ret = t4_wr_mbox(adap, mbox, &c, sizeof(c), &c); in t4_change_mac()
7530 int t4_set_addr_hash(struct adapter *adap, unsigned int mbox, unsigned int viid, in t4_set_addr_hash() argument
7543 return t4_wr_mbox_meat(adap, mbox, &c, sizeof(c), NULL, sleep_ok); in t4_set_addr_hash()
7558 int t4_enable_vi_params(struct adapter *adap, unsigned int mbox, in t4_enable_vi_params() argument
7571 return t4_wr_mbox_ns(adap, mbox, &c, sizeof(c), NULL); in t4_enable_vi_params()
7584 int t4_enable_vi(struct adapter *adap, unsigned int mbox, unsigned int viid, in t4_enable_vi() argument
7587 return t4_enable_vi_params(adap, mbox, viid, rx_en, tx_en, 0); in t4_enable_vi()
7599 int t4_identify_port(struct adapter *adap, unsigned int mbox, unsigned int viid, in t4_identify_port() argument
7610 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_identify_port()
7628 int t4_iq_stop(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_iq_stop() argument
7643 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_iq_stop()
7659 int t4_iq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_iq_free() argument
7674 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_iq_free()
7687 int t4_eth_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_eth_eq_free() argument
7699 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_eth_eq_free()
7712 int t4_ctrl_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_ctrl_eq_free() argument
7724 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_ctrl_eq_free()
7737 int t4_ofld_eq_free(struct adapter *adap, unsigned int mbox, unsigned int pf, in t4_ofld_eq_free() argument
7749 return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL); in t4_ofld_eq_free()
8097 int t4_handle_fw_rpl(struct adapter *adap, const __be64 *rpl) in t4_handle_fw_rpl() argument
8117 for_each_port(adap, i) { in t4_handle_fw_rpl()
8118 pi = adap2pinfo(adap, i); in t4_handle_fw_rpl()
8125 dev_warn(adap->pdev_dev, "Unknown firmware reply %d\n", in t4_handle_fw_rpl()
8198 static int get_flash_params(struct adapter *adap) in get_flash_params() argument
8210 ret = sf1_write(adap, 1, 1, 0, SF_RD_ID); in get_flash_params()
8212 ret = sf1_read(adap, 3, 0, 1, &info); in get_flash_params()
8213 t4_write_reg(adap, SF_OP_A, 0); /* unlock SF */ in get_flash_params()
8219 adap->params.sf_size = supported_flash[ret].size_mb; in get_flash_params()
8220 adap->params.sf_nsec = in get_flash_params()
8221 adap->params.sf_size / SF_SEC_SIZE; in get_flash_params()
8229 adap->params.sf_nsec = 1 << (info - 16); in get_flash_params()
8231 adap->params.sf_nsec = 64; in get_flash_params()
8234 adap->params.sf_size = 1 << info; in get_flash_params()
8235 adap->params.sf_fw_start = in get_flash_params()
8236 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M; in get_flash_params()
8238 if (adap->params.sf_size < FLASH_MIN_SIZE) in get_flash_params()
8239 dev_warn(adap->pdev_dev, "WARNING!!! FLASH size %#x < %#x!!!\n", in get_flash_params()
8240 adap->params.sf_size, FLASH_MIN_SIZE); in get_flash_params()
8479 int t4_init_devlog_params(struct adapter *adap) in t4_init_devlog_params() argument
8481 struct devlog_params *dparams = &adap->params.devlog; in t4_init_devlog_params()
8492 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG)); in t4_init_devlog_params()
8512 ret = t4_wr_mbox(adap, adap->mbox, &devlog_cmd, sizeof(devlog_cmd), in t4_init_devlog_params()
8563 int t4_init_tp_params(struct adapter *adap) in t4_init_tp_params() argument
8568 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A); in t4_init_tp_params()
8569 adap->params.tp.tre = TIMERRESOLUTION_G(v); in t4_init_tp_params()
8570 adap->params.tp.dack_re = DELAYEDACKRESOLUTION_G(v); in t4_init_tp_params()
8574 adap->params.tp.tx_modq[chan] = chan; in t4_init_tp_params()
8579 if (t4_use_ldst(adap)) { in t4_init_tp_params()
8580 t4_fw_tp_pio_rw(adap, &adap->params.tp.vlan_pri_map, 1, in t4_init_tp_params()
8582 t4_fw_tp_pio_rw(adap, &adap->params.tp.ingress_config, 1, in t4_init_tp_params()
8585 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, in t4_init_tp_params()
8586 &adap->params.tp.vlan_pri_map, 1, in t4_init_tp_params()
8588 t4_read_indirect(adap, TP_PIO_ADDR_A, TP_PIO_DATA_A, in t4_init_tp_params()
8589 &adap->params.tp.ingress_config, 1, in t4_init_tp_params()
8595 if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) { in t4_init_tp_params()
8596 v = t4_read_reg(adap, TP_OUT_CONFIG_A); in t4_init_tp_params()
8597 adap->params.tp.rx_pkt_encap = (v & CRXPKTENC_F) ? 1 : 0; in t4_init_tp_params()
8604 adap->params.tp.vlan_shift = t4_filter_field_shift(adap, VLAN_F); in t4_init_tp_params()
8605 adap->params.tp.vnic_shift = t4_filter_field_shift(adap, VNIC_ID_F); in t4_init_tp_params()
8606 adap->params.tp.port_shift = t4_filter_field_shift(adap, PORT_F); in t4_init_tp_params()
8607 adap->params.tp.protocol_shift = t4_filter_field_shift(adap, in t4_init_tp_params()
8613 if ((adap->params.tp.ingress_config & VNIC_F) == 0) in t4_init_tp_params()
8614 adap->params.tp.vnic_shift = -1; in t4_init_tp_params()
8628 int t4_filter_field_shift(const struct adapter *adap, int filter_sel) in t4_filter_field_shift() argument
8630 unsigned int filter_mode = adap->params.tp.vlan_pri_map; in t4_filter_field_shift()
8674 int t4_init_rss_mode(struct adapter *adap, int mbox) in t4_init_rss_mode() argument
8681 for_each_port(adap, i) { in t4_init_rss_mode()
8682 struct port_info *p = adap2pinfo(adap, i); in t4_init_rss_mode()
8689 ret = t4_wr_mbox(adap, mbox, &rvc, sizeof(rvc), &rvc); in t4_init_rss_mode()
8792 int t4_port_init(struct adapter *adap, int mbox, int pf, int vf) in t4_port_init() argument
8797 for_each_port(adap, i) { in t4_port_init()
8798 struct port_info *pi = adap2pinfo(adap, i); in t4_port_init()
8800 while ((adap->params.portvec & (1 << j)) == 0) in t4_port_init()
8807 memcpy(adap->port[i]->dev_addr, addr, ETH_ALEN); in t4_port_init()
8823 void t4_read_cimq_cfg(struct adapter *adap, u16 *base, u16 *size, u16 *thres) in t4_read_cimq_cfg() argument
8826 int cim_num_obq = is_t4(adap->params.chip) ? in t4_read_cimq_cfg()
8830 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, IBQSELECT_F | in t4_read_cimq_cfg()
8832 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); in t4_read_cimq_cfg()
8839 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | in t4_read_cimq_cfg()
8841 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); in t4_read_cimq_cfg()
8859 int t4_read_cim_ibq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) in t4_read_cim_ibq() argument
8878 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, IBQDBGADDR_V(addr) | in t4_read_cim_ibq()
8880 err = t4_wait_op_done(adap, CIM_IBQ_DBG_CFG_A, IBQDBGBUSY_F, 0, in t4_read_cim_ibq()
8884 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A); in t4_read_cim_ibq()
8886 t4_write_reg(adap, CIM_IBQ_DBG_CFG_A, 0); in t4_read_cim_ibq()
8901 int t4_read_cim_obq(struct adapter *adap, unsigned int qid, u32 *data, size_t n) in t4_read_cim_obq() argument
8905 int cim_num_obq = is_t4(adap->params.chip) ? in t4_read_cim_obq()
8911 t4_write_reg(adap, CIM_QUEUE_CONFIG_REF_A, OBQSELECT_F | in t4_read_cim_obq()
8913 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); in t4_read_cim_obq()
8921 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, OBQDBGADDR_V(addr) | in t4_read_cim_obq()
8923 err = t4_wait_op_done(adap, CIM_OBQ_DBG_CFG_A, OBQDBGBUSY_F, 0, in t4_read_cim_obq()
8927 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A); in t4_read_cim_obq()
8929 t4_write_reg(adap, CIM_OBQ_DBG_CFG_A, 0); in t4_read_cim_obq()
8942 int t4_cim_read(struct adapter *adap, unsigned int addr, unsigned int n, in t4_cim_read() argument
8947 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F) in t4_cim_read()
8951 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr); in t4_cim_read()
8952 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F, in t4_cim_read()
8955 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A); in t4_cim_read()
8969 int t4_cim_write(struct adapter *adap, unsigned int addr, unsigned int n, in t4_cim_write() argument
8974 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F) in t4_cim_write()
8978 t4_write_reg(adap, CIM_HOST_ACC_DATA_A, *valp++); in t4_cim_write()
8979 t4_write_reg(adap, CIM_HOST_ACC_CTRL_A, addr | HOSTWRITE_F); in t4_cim_write()
8980 ret = t4_wait_op_done(adap, CIM_HOST_ACC_CTRL_A, HOSTBUSY_F, in t4_cim_write()
8986 static int t4_cim_write1(struct adapter *adap, unsigned int addr, in t4_cim_write1() argument
8989 return t4_cim_write(adap, addr, 1, &val); in t4_cim_write1()
9002 int t4_cim_read_la(struct adapter *adap, u32 *la_buf, unsigned int *wrptr) in t4_cim_read_la() argument
9007 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &cfg); in t4_cim_read_la()
9012 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, 0); in t4_cim_read_la()
9017 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val); in t4_cim_read_la()
9025 for (i = 0; i < adap->params.cim_la_size; i++) { in t4_cim_read_la()
9026 ret = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, in t4_cim_read_la()
9030 ret = t4_cim_read(adap, UP_UP_DBG_LA_CFG_A, 1, &val); in t4_cim_read_la()
9037 ret = t4_cim_read(adap, UP_UP_DBG_LA_DATA_A, 1, &la_buf[i]); in t4_cim_read_la()
9044 if (is_t6(adap->params.chip) && (idx & 0xf) >= 9) in t4_cim_read_la()
9053 int r = t4_cim_write1(adap, UP_UP_DBG_LA_CFG_A, in t4_cim_read_la()
9071 void t4_tp_read_la(struct adapter *adap, u64 *la_buf, unsigned int *wrptr) in t4_tp_read_la() argument
9076 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff; in t4_tp_read_la()
9078 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, in t4_tp_read_la()
9079 adap->params.tp.la_mask | (cfg ^ DBGLAENABLE_F)); in t4_tp_read_la()
9081 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A); in t4_tp_read_la()
9091 val |= adap->params.tp.la_mask; in t4_tp_read_la()
9094 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, DBGLARPTR_V(idx) | val); in t4_tp_read_la()
9095 la_buf[i] = t4_read_reg64(adap, TP_DBG_LA_DATAL_A); in t4_tp_read_la()
9104 t4_write_reg(adap, TP_DBG_LA_CONFIG_A, in t4_tp_read_la()
9105 cfg | adap->params.tp.la_mask); in t4_tp_read_la()
9243 int t4_load_cfg(struct adapter *adap, const u8 *cfg_data, unsigned int size) in t4_load_cfg() argument
9248 unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; in t4_load_cfg()
9250 cfg_addr = t4_flash_cfg_addr(adap); in t4_load_cfg()
9258 dev_err(adap->pdev_dev, "cfg file too large, max is %u bytes\n", in t4_load_cfg()
9265 ret = t4_flash_erase_sectors(adap, flash_cfg_start_sec, in t4_load_cfg()
9279 ret = t4_write_flash(adap, addr, n, cfg_data); in t4_load_cfg()
9289 dev_err(adap->pdev_dev, "config file %s failed %d\n", in t4_load_cfg()