Lines Matching refs:t4_read_reg
61 u32 val = t4_read_reg(adapter, reg); in t4_wait_op_done_val()
95 u32 v = t4_read_reg(adapter, addr) & ~mask; in t4_set_reg_field()
98 (void) t4_read_reg(adapter, addr); /* flush */ in t4_set_reg_field()
119 *vals++ = t4_read_reg(adap, data_reg); in t4_read_indirect()
165 *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A); in t4_hw_pci_read_cfg4()
197 pcie_fw = t4_read_reg(adap, PCIE_FW_A); in t4_report_fw_error()
333 pcie_fw = t4_read_reg(adap, PCIE_FW_A); in t4_wr_mbox_meat_timeout()
364 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); in t4_wr_mbox_meat_timeout()
366 v = MBOWNER_G(t4_read_reg(adap, ctl_reg)); in t4_wr_mbox_meat_timeout()
382 t4_read_reg(adap, ctl_reg); /* flush write */ in t4_wr_mbox_meat_timeout()
388 !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) && in t4_wr_mbox_meat_timeout()
399 v = t4_read_reg(adap, ctl_reg); in t4_wr_mbox_meat_timeout()
467 t4_read_reg(adap, edc_ecc_err_addr_reg)); in t4_edc_err_read()
528 edc_size = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A)); in t4_memory_rw()
532 mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap, in t4_memory_rw()
548 mem_reg = t4_read_reg(adap, in t4_memory_rw()
570 t4_read_reg(adap, in t4_memory_rw()
609 *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap, in t4_memory_rw()
629 t4_read_reg(adap, in t4_memory_rw()
650 (__force __le32)t4_read_reg(adap, in t4_memory_rw()
758 t4_read_reg(adap, in t4_setup_memwin()
2628 *bufp++ = t4_read_reg(adap, reg); in t4_get_regs()
2831 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F) in sf1_read()
2837 *valp = t4_read_reg(adapter, SF_DATA_A); in sf1_read()
2858 if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F) in sf1_write()
3765 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A); in t4_cim_read_pif_la()
3769 val = t4_read_reg(adap, CIM_DEBUGSTS_A); in t4_cim_read_pif_la()
3781 *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A); in t4_cim_read_pif_la()
3782 *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A); in t4_cim_read_pif_la()
3797 cfg = t4_read_reg(adap, CIM_DEBUGCFG_A); in t4_cim_read_ma_la()
3806 *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A); in t4_cim_read_ma_la()
3807 *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A); in t4_cim_read_ma_la()
3821 j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A); in t4_ulprx_read_la()
3824 *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A); in t4_ulprx_read_la()
4084 unsigned int status = t4_read_reg(adapter, reg); in t4_handle_intr_status()
4280 v = (u64)t4_read_reg(adapter, SGE_INT_CAUSE1_A) | in sge_intr_handler()
4281 ((u64)t4_read_reg(adapter, SGE_INT_CAUSE2_A) << 32); in sge_intr_handler()
4294 err = t4_read_reg(adapter, SGE_ERROR_STATS_A); in sge_intr_handler()
4365 fw_err = t4_read_reg(adapter, PCIE_FW_A); in cim_intr_handler()
4376 val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A); in cim_intr_handler()
4599 t4_read_reg(adapter, MPS_INT_CAUSE_A); /* flush */ in mps_intr_handler()
4632 v = t4_read_reg(adapter, addr) & MEM_INT_MASK; in mem_intr_handler()
4637 u32 cnt = ECC_CECNT_G(t4_read_reg(adapter, cnt_addr)); in mem_intr_handler()
4661 u32 v, status = t4_read_reg(adap, MA_INT_CAUSE_A); in ma_intr_handler()
4666 t4_read_reg(adap, MA_PARITY_ERROR_STATUS1_A)); in ma_intr_handler()
4670 t4_read_reg(adap, in ma_intr_handler()
4674 v = t4_read_reg(adap, MA_INT_WRAP_STATUS_A); in ma_intr_handler()
4729 v = t4_read_reg(adap, int_cause_reg); in xgmac_intr_handler()
4775 u32 cause = t4_read_reg(adapter, PL_INT_CAUSE_A); in t4_slow_intr_handler()
4828 (void)t4_read_reg(adapter, PL_INT_CAUSE_A); /* flush */ in t4_slow_intr_handler()
4848 u32 whoami = t4_read_reg(adapter, PL_WHOAMI_A); in t4_intr_enable()
4880 whoami = t4_read_reg(adapter, PL_WHOAMI_A); in t4_intr_disable()
5107 u32 vrt = t4_read_reg(adap, TP_RSS_CONFIG_VRT_A); in t4_write_rss_key()
5179 vrt = t4_read_reg(adapter, TP_RSS_CONFIG_VRT_A); in t4_read_rss_vf_config()
5391 v = t4_read_reg(adap, TP_MTU_TABLE_A); in t4_read_mtu_tbl()
5414 incr[mtu][w] = (u16)t4_read_reg(adap, in t4_read_cong_tbl()
5432 val |= t4_read_reg(adap, TP_PIO_DATA_A) & ~mask; in t4_tp_wr_bits_indirect()
5556 v = t4_read_reg(adap, TP_TX_TRATE_A); in t4_get_chan_txrate()
5564 v = t4_read_reg(adap, TP_TX_ORATE_A); in t4_get_chan_txrate()
5596 cfg = t4_read_reg(adap, MPS_TRC_CFG_A); in t4_set_trace_filter()
5659 ctla = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_A_A + ofst); in t4_get_trace_filter()
5660 ctlb = t4_read_reg(adap, MPS_TRC_FILTER_MATCH_CTL_B_A + ofst); in t4_get_trace_filter()
5681 tp->mask[i] = ~t4_read_reg(adap, mask_reg); in t4_get_trace_filter()
5682 tp->data[i] = t4_read_reg(adap, data_reg) & tp->mask[i]; in t4_get_trace_filter()
5701 cnt[i] = t4_read_reg(adap, PM_TX_STAT_COUNT_A); in t4_pmtx_get_stats()
5728 cnt[i] = t4_read_reg(adap, PM_RX_STAT_COUNT_A); in t4_pmrx_get_stats()
5755 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A)); in compute_mps_bg_map()
5794 nports = 1 << NUMPORTS_G(t4_read_reg(adapter, MPS_CMN_CTL_A)); in t4_get_mps_bg_map()
5858 unsigned int nports = 1 << NUMPORTS_G(t4_read_reg(adap, MPS_CMN_CTL_A)); in t4_get_tp_ch_map()
5961 u32 stat_ctl = t4_read_reg(adap, MPS_STAT_CTL_A); in t4_get_port_stats()
6369 sge_regs[i], t4_read_reg(adapter, sge_regs[i])); in t4_sge_decode_idma_state()
6441 if (t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_ERR_F) in t4_fw_hello()
6491 pcie_fw = t4_read_reg(adap, PCIE_FW_A); in t4_fw_hello()
6692 if (!(t4_read_reg(adap, PCIE_FW_A) & PCIE_FW_HALT_F)) in t4_fw_restart()
6792 sge_control = t4_read_reg(adap, SGE_CONTROL_A); in t4_fl_pkt_align()
6818 sge_control2 = t4_read_reg(adap, SGE_CONTROL2_A); in t4_fl_pkt_align()
6973 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE2_A) + fl_align-1) in t4_fixup_host_params()
6976 (t4_read_reg(adap, SGE_FL_BUFFER_SIZE3_A) + fl_align-1) in t4_fixup_host_params()
8236 t4_read_reg(adap, CIM_BOOT_CFG_A) & BOOTADDR_M; in get_flash_params()
8276 pl_rev = REV_G(t4_read_reg(adapter, PL_REV_A)); in t4_prep_adapter()
8374 t4_read_reg(adapter, a_port_cfg) in t4_shutdown_adapter()
8492 t4_read_reg(adap, PCIE_FW_REG(PCIE_FW_PF_A, PCIE_FW_PF_DEVLOG)); in t4_init_devlog_params()
8540 hps = t4_read_reg(adapter, SGE_HOST_PAGE_SIZE_A); in t4_init_sge_params()
8549 qpp = t4_read_reg(adapter, SGE_EGRESS_QUEUES_PER_PAGE_PF_A); in t4_init_sge_params()
8551 qpp = t4_read_reg(adapter, SGE_INGRESS_QUEUES_PER_PAGE_PF_A); in t4_init_sge_params()
8568 v = t4_read_reg(adap, TP_TIMER_RESOLUTION_A); in t4_init_tp_params()
8596 v = t4_read_reg(adap, TP_OUT_CONFIG_A); in t4_init_tp_params()
8832 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); in t4_read_cimq_cfg()
8841 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); in t4_read_cimq_cfg()
8884 *data++ = t4_read_reg(adap, CIM_IBQ_DBG_DATA_A); in t4_read_cim_ibq()
8913 v = t4_read_reg(adap, CIM_QUEUE_CONFIG_CTRL_A); in t4_read_cim_obq()
8927 *data++ = t4_read_reg(adap, CIM_OBQ_DBG_DATA_A); in t4_read_cim_obq()
8947 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F) in t4_cim_read()
8955 *valp++ = t4_read_reg(adap, CIM_HOST_ACC_DATA_A); in t4_cim_read()
8974 if (t4_read_reg(adap, CIM_HOST_ACC_CTRL_A) & HOSTBUSY_F) in t4_cim_write()
9076 cfg = t4_read_reg(adap, TP_DBG_LA_CONFIG_A) & 0xffff; in t4_tp_read_la()
9081 val = t4_read_reg(adap, TP_DBG_LA_CONFIG_A); in t4_tp_read_la()
9166 idma_same_state_cnt[0] = t4_read_reg(adapter, SGE_DEBUG_DATA_HIGH_A); in t4_idma_monitor()
9167 idma_same_state_cnt[1] = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A); in t4_idma_monitor()
9219 debug0 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A); in t4_idma_monitor()
9223 debug11 = t4_read_reg(adapter, SGE_DEBUG_DATA_LOW_A); in t4_idma_monitor()