85 	u32 phy_id;  in asix_get_phyid()  local
90 		phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);  in asix_get_phyid()
101 	phy_id = (phy_reg & 0xffff) << 16;  in asix_get_phyid()
103 	phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);  in asix_get_phyid()
107 	phy_id |= (phy_reg & 0xffff);  in asix_get_phyid()
109 	return phy_id;  in asix_get_phyid()
220 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits);  in asix_phy_reset()
227 		if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR)  in asix_phy_reset()
235 		   dev->mii.phy_id);  in asix_phy_reset()
277 	dev->mii.phy_id = asix_get_phy_addr(dev);  in ax88172_bind()
285 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,  in ax88172_bind()
371 	embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);  in ax88772_hw_reset()
406 	if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,  in ax88772_hw_reset()
466 	embd_phy = ((dev->mii.phy_id & 0x1f) == 0x10 ? 1 : 0);  in ax88772a_hw_reset()
498 	if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
519 		phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
521 		phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
523 		phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
532 			asix_mdio_write_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
536 			asix_mdio_write_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
540 			asix_mdio_write_nopm(dev->net, dev->mii.phy_id,  in ax88772a_hw_reset()
617 		asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_BMCR);  in ax88772_suspend()
621 		asix_mdio_read_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE);  in ax88772_suspend()
641 		asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_ADVERTISE,  in ax88772_restore_phy()
648 		asix_mdio_write_nopm(dev->net, dev->mii.phy_id, MII_BMCR,  in ax88772_restore_phy()
724 	dev->mii.phy_id = asix_get_phy_addr(dev);  in ax88772_bind()
800 	reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);  in marvell_phy_init()
803 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,  in marvell_phy_init()
807 		reg = asix_mdio_read(dev->net, dev->mii.phy_id,  in marvell_phy_init()
813 		asix_mdio_write(dev->net, dev->mii.phy_id,  in marvell_phy_init()
816 		reg = asix_mdio_read(dev->net, dev->mii.phy_id,  in marvell_phy_init()
831 	asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);  in rtl8211cl_phy_init()
832 	asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);  in rtl8211cl_phy_init()
833 	asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,  in rtl8211cl_phy_init()
834 		asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);  in rtl8211cl_phy_init()
835 	asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);  in rtl8211cl_phy_init()
838 		asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);  in rtl8211cl_phy_init()
839 		asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);  in rtl8211cl_phy_init()
840 		asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);  in rtl8211cl_phy_init()
848 	u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);  in marvell_led_status()
867 	asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);  in marvell_led_status()
936 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,  in ax88178_reset()
938 	asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,  in ax88178_reset()
1088 	dev->mii.phy_id = asix_get_phy_addr(dev);  in ax88178_bind()