Lines Matching refs:rt2x00dev
65 static void rt61pci_bbp_write(struct rt2x00_dev *rt2x00dev, in rt61pci_bbp_write() argument
70 mutex_lock(&rt2x00dev->csr_mutex); in rt61pci_bbp_write()
76 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt61pci_bbp_write()
83 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); in rt61pci_bbp_write()
86 mutex_unlock(&rt2x00dev->csr_mutex); in rt61pci_bbp_write()
89 static u8 rt61pci_bbp_read(struct rt2x00_dev *rt2x00dev, in rt61pci_bbp_read() argument
95 mutex_lock(&rt2x00dev->csr_mutex); in rt61pci_bbp_read()
105 if (WAIT_FOR_BBP(rt2x00dev, ®)) { in rt61pci_bbp_read()
111 rt2x00mmio_register_write(rt2x00dev, PHY_CSR3, reg); in rt61pci_bbp_read()
113 WAIT_FOR_BBP(rt2x00dev, ®); in rt61pci_bbp_read()
118 mutex_unlock(&rt2x00dev->csr_mutex); in rt61pci_bbp_read()
123 static void rt61pci_rf_write(struct rt2x00_dev *rt2x00dev, in rt61pci_rf_write() argument
128 mutex_lock(&rt2x00dev->csr_mutex); in rt61pci_rf_write()
134 if (WAIT_FOR_RF(rt2x00dev, ®)) { in rt61pci_rf_write()
141 rt2x00mmio_register_write(rt2x00dev, PHY_CSR4, reg); in rt61pci_rf_write()
142 rt2x00_rf_write(rt2x00dev, word, value); in rt61pci_rf_write()
145 mutex_unlock(&rt2x00dev->csr_mutex); in rt61pci_rf_write()
148 static void rt61pci_mcu_request(struct rt2x00_dev *rt2x00dev, in rt61pci_mcu_request() argument
154 mutex_lock(&rt2x00dev->csr_mutex); in rt61pci_mcu_request()
160 if (WAIT_FOR_MCU(rt2x00dev, ®)) { in rt61pci_mcu_request()
165 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg); in rt61pci_mcu_request()
167 reg = rt2x00mmio_register_read(rt2x00dev, HOST_CMD_CSR); in rt61pci_mcu_request()
170 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, reg); in rt61pci_mcu_request()
173 mutex_unlock(&rt2x00dev->csr_mutex); in rt61pci_mcu_request()
179 struct rt2x00_dev *rt2x00dev = eeprom->data; in rt61pci_eepromregister_read() local
182 reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR); in rt61pci_eepromregister_read()
194 struct rt2x00_dev *rt2x00dev = eeprom->data; in rt61pci_eepromregister_write() local
204 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg); in rt61pci_eepromregister_write()
242 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev) in rt61pci_rfkill_poll() argument
246 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13); in rt61pci_rfkill_poll()
258 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_5GHZ); in rt61pci_brightness_set()
260 (enabled && led->rt2x00dev->curr_band == NL80211_BAND_2GHZ); in rt61pci_brightness_set()
263 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, in rt61pci_brightness_set()
266 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, in rt61pci_brightness_set()
267 (led->rt2x00dev->led_mcu_reg & 0xff), in rt61pci_brightness_set()
268 ((led->rt2x00dev->led_mcu_reg >> 8))); in rt61pci_brightness_set()
270 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, in rt61pci_brightness_set()
272 rt2x00_set_field16(&led->rt2x00dev->led_mcu_reg, in rt61pci_brightness_set()
275 rt61pci_mcu_request(led->rt2x00dev, MCU_LED, 0xff, in rt61pci_brightness_set()
276 (led->rt2x00dev->led_mcu_reg & 0xff), in rt61pci_brightness_set()
277 ((led->rt2x00dev->led_mcu_reg >> 8))); in rt61pci_brightness_set()
284 rt61pci_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff, in rt61pci_brightness_set()
297 reg = rt2x00mmio_register_read(led->rt2x00dev, MAC_CSR14); in rt61pci_blink_set()
300 rt2x00mmio_register_write(led->rt2x00dev, MAC_CSR14, reg); in rt61pci_blink_set()
305 static void rt61pci_init_led(struct rt2x00_dev *rt2x00dev, in rt61pci_init_led() argument
309 led->rt2x00dev = rt2x00dev; in rt61pci_init_led()
320 static int rt61pci_config_shared_key(struct rt2x00_dev *rt2x00dev, in rt61pci_config_shared_key() argument
342 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR0); in rt61pci_config_shared_key()
361 rt2x00mmio_register_multiwrite(rt2x00dev, reg, in rt61pci_config_shared_key()
375 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR1); in rt61pci_config_shared_key()
377 rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, reg); in rt61pci_config_shared_key()
382 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR5); in rt61pci_config_shared_key()
384 rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, reg); in rt61pci_config_shared_key()
407 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR0); in rt61pci_config_shared_key()
412 rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, reg); in rt61pci_config_shared_key()
417 static int rt61pci_config_pairwise_key(struct rt2x00_dev *rt2x00dev, in rt61pci_config_pairwise_key() argument
436 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR2); in rt61pci_config_pairwise_key()
439 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR3); in rt61pci_config_pairwise_key()
461 rt2x00mmio_register_multiwrite(rt2x00dev, reg, in rt61pci_config_pairwise_key()
465 rt2x00mmio_register_multiwrite(rt2x00dev, reg, in rt61pci_config_pairwise_key()
473 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR4); in rt61pci_config_pairwise_key()
475 rt2x00mmio_register_write(rt2x00dev, SEC_CSR4, reg); in rt61pci_config_pairwise_key()
498 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR2); in rt61pci_config_pairwise_key()
503 rt2x00mmio_register_write(rt2x00dev, SEC_CSR2, reg); in rt61pci_config_pairwise_key()
507 reg = rt2x00mmio_register_read(rt2x00dev, SEC_CSR3); in rt61pci_config_pairwise_key()
512 rt2x00mmio_register_write(rt2x00dev, SEC_CSR3, reg); in rt61pci_config_pairwise_key()
518 static void rt61pci_config_filter(struct rt2x00_dev *rt2x00dev, in rt61pci_config_filter() argument
529 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); in rt61pci_config_filter()
537 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags)); in rt61pci_config_filter()
539 !test_bit(CONFIG_MONITORING, &rt2x00dev->flags) && in rt61pci_config_filter()
540 !rt2x00dev->intf_ap_count); in rt61pci_config_filter()
547 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_config_filter()
550 static void rt61pci_config_intf(struct rt2x00_dev *rt2x00dev, in rt61pci_config_intf() argument
561 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_config_intf()
563 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_config_intf()
571 rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR2, in rt61pci_config_intf()
580 rt2x00mmio_register_multiwrite(rt2x00dev, MAC_CSR4, in rt61pci_config_intf()
586 static void rt61pci_config_erp(struct rt2x00_dev *rt2x00dev, in rt61pci_config_erp() argument
592 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); in rt61pci_config_erp()
595 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_config_erp()
598 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4); in rt61pci_config_erp()
602 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); in rt61pci_config_erp()
606 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR5, in rt61pci_config_erp()
610 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_config_erp()
613 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_config_erp()
617 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR9); in rt61pci_config_erp()
619 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); in rt61pci_config_erp()
621 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR8); in rt61pci_config_erp()
625 rt2x00mmio_register_write(rt2x00dev, MAC_CSR8, reg); in rt61pci_config_erp()
629 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev, in rt61pci_config_antenna_5x() argument
636 r3 = rt61pci_bbp_read(rt2x00dev, 3); in rt61pci_config_antenna_5x()
637 r4 = rt61pci_bbp_read(rt2x00dev, 4); in rt61pci_config_antenna_5x()
638 r77 = rt61pci_bbp_read(rt2x00dev, 77); in rt61pci_config_antenna_5x()
640 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF5325)); in rt61pci_config_antenna_5x()
649 (rt2x00dev->curr_band != NL80211_BAND_5GHZ)); in rt61pci_config_antenna_5x()
654 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) in rt61pci_config_antenna_5x()
663 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) in rt61pci_config_antenna_5x()
670 rt61pci_bbp_write(rt2x00dev, 77, r77); in rt61pci_config_antenna_5x()
671 rt61pci_bbp_write(rt2x00dev, 3, r3); in rt61pci_config_antenna_5x()
672 rt61pci_bbp_write(rt2x00dev, 4, r4); in rt61pci_config_antenna_5x()
675 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev, in rt61pci_config_antenna_2x() argument
682 r3 = rt61pci_bbp_read(rt2x00dev, 3); in rt61pci_config_antenna_2x()
683 r4 = rt61pci_bbp_read(rt2x00dev, 4); in rt61pci_config_antenna_2x()
684 r77 = rt61pci_bbp_read(rt2x00dev, 77); in rt61pci_config_antenna_2x()
686 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, rt2x00_rf(rt2x00dev, RF2529)); in rt61pci_config_antenna_2x()
688 !rt2x00_has_cap_frame_type(rt2x00dev)); in rt61pci_config_antenna_2x()
708 rt61pci_bbp_write(rt2x00dev, 77, r77); in rt61pci_config_antenna_2x()
709 rt61pci_bbp_write(rt2x00dev, 3, r3); in rt61pci_config_antenna_2x()
710 rt61pci_bbp_write(rt2x00dev, 4, r4); in rt61pci_config_antenna_2x()
713 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev, in rt61pci_config_antenna_2529_rx() argument
718 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13); in rt61pci_config_antenna_2529_rx()
726 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); in rt61pci_config_antenna_2529_rx()
729 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev, in rt61pci_config_antenna_2529() argument
736 r3 = rt61pci_bbp_read(rt2x00dev, 3); in rt61pci_config_antenna_2529()
737 r4 = rt61pci_bbp_read(rt2x00dev, 4); in rt61pci_config_antenna_2529()
738 r77 = rt61pci_bbp_read(rt2x00dev, 77); in rt61pci_config_antenna_2529()
747 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0); in rt61pci_config_antenna_2529()
759 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1); in rt61pci_config_antenna_2529()
763 rt61pci_bbp_write(rt2x00dev, 77, r77); in rt61pci_config_antenna_2529()
764 rt61pci_bbp_write(rt2x00dev, 3, r3); in rt61pci_config_antenna_2529()
765 rt61pci_bbp_write(rt2x00dev, 4, r4); in rt61pci_config_antenna_2529()
799 static void rt61pci_config_ant(struct rt2x00_dev *rt2x00dev, in rt61pci_config_ant() argument
814 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { in rt61pci_config_ant()
816 lna = rt2x00_has_cap_external_lna_a(rt2x00dev); in rt61pci_config_ant()
819 lna = rt2x00_has_cap_external_lna_bg(rt2x00dev); in rt61pci_config_ant()
823 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]); in rt61pci_config_ant()
825 reg = rt2x00mmio_register_read(rt2x00dev, PHY_CSR0); in rt61pci_config_ant()
828 rt2x00dev->curr_band == NL80211_BAND_2GHZ); in rt61pci_config_ant()
830 rt2x00dev->curr_band == NL80211_BAND_5GHZ); in rt61pci_config_ant()
832 rt2x00mmio_register_write(rt2x00dev, PHY_CSR0, reg); in rt61pci_config_ant()
834 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) in rt61pci_config_ant()
835 rt61pci_config_antenna_5x(rt2x00dev, ant); in rt61pci_config_ant()
836 else if (rt2x00_rf(rt2x00dev, RF2527)) in rt61pci_config_ant()
837 rt61pci_config_antenna_2x(rt2x00dev, ant); in rt61pci_config_ant()
838 else if (rt2x00_rf(rt2x00dev, RF2529)) { in rt61pci_config_ant()
839 if (rt2x00_has_cap_double_antenna(rt2x00dev)) in rt61pci_config_ant()
840 rt61pci_config_antenna_2x(rt2x00dev, ant); in rt61pci_config_ant()
842 rt61pci_config_antenna_2529(rt2x00dev, ant); in rt61pci_config_ant()
846 static void rt61pci_config_lna_gain(struct rt2x00_dev *rt2x00dev, in rt61pci_config_lna_gain() argument
853 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) in rt61pci_config_lna_gain()
856 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG); in rt61pci_config_lna_gain()
859 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) in rt61pci_config_lna_gain()
862 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A); in rt61pci_config_lna_gain()
866 rt2x00dev->lna_gain = lna_gain; in rt61pci_config_lna_gain()
869 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev, in rt61pci_config_channel() argument
877 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset); in rt61pci_config_channel()
879 smart = !(rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF2527)); in rt61pci_config_channel()
881 r3 = rt61pci_bbp_read(rt2x00dev, 3); in rt61pci_config_channel()
883 rt61pci_bbp_write(rt2x00dev, 3, r3); in rt61pci_config_channel()
890 rt61pci_bbp_write(rt2x00dev, 94, r94); in rt61pci_config_channel()
892 rt61pci_rf_write(rt2x00dev, 1, rf->rf1); in rt61pci_config_channel()
893 rt61pci_rf_write(rt2x00dev, 2, rf->rf2); in rt61pci_config_channel()
894 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); in rt61pci_config_channel()
895 rt61pci_rf_write(rt2x00dev, 4, rf->rf4); in rt61pci_config_channel()
899 rt61pci_rf_write(rt2x00dev, 1, rf->rf1); in rt61pci_config_channel()
900 rt61pci_rf_write(rt2x00dev, 2, rf->rf2); in rt61pci_config_channel()
901 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004); in rt61pci_config_channel()
902 rt61pci_rf_write(rt2x00dev, 4, rf->rf4); in rt61pci_config_channel()
906 rt61pci_rf_write(rt2x00dev, 1, rf->rf1); in rt61pci_config_channel()
907 rt61pci_rf_write(rt2x00dev, 2, rf->rf2); in rt61pci_config_channel()
908 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004); in rt61pci_config_channel()
909 rt61pci_rf_write(rt2x00dev, 4, rf->rf4); in rt61pci_config_channel()
914 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev, in rt61pci_config_txpower() argument
919 rf.rf1 = rt2x00_rf_read(rt2x00dev, 1); in rt61pci_config_txpower()
920 rf.rf2 = rt2x00_rf_read(rt2x00dev, 2); in rt61pci_config_txpower()
921 rf.rf3 = rt2x00_rf_read(rt2x00dev, 3); in rt61pci_config_txpower()
922 rf.rf4 = rt2x00_rf_read(rt2x00dev, 4); in rt61pci_config_txpower()
924 rt61pci_config_channel(rt2x00dev, &rf, txpower); in rt61pci_config_txpower()
927 static void rt61pci_config_retry_limit(struct rt2x00_dev *rt2x00dev, in rt61pci_config_retry_limit() argument
932 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR4); in rt61pci_config_retry_limit()
940 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR4, reg); in rt61pci_config_retry_limit()
943 static void rt61pci_config_ps(struct rt2x00_dev *rt2x00dev, in rt61pci_config_ps() argument
952 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR11); in rt61pci_config_ps()
954 rt2x00dev->beacon_int - 10); in rt61pci_config_ps()
961 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
964 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
966 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, in rt61pci_config_ps()
968 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x0000001c); in rt61pci_config_ps()
969 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000060); in rt61pci_config_ps()
971 rt61pci_mcu_request(rt2x00dev, MCU_SLEEP, 0xff, 0, 0); in rt61pci_config_ps()
973 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR11); in rt61pci_config_ps()
978 rt2x00mmio_register_write(rt2x00dev, MAC_CSR11, reg); in rt61pci_config_ps()
980 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, in rt61pci_config_ps()
982 rt2x00mmio_register_write(rt2x00dev, IO_CNTL_CSR, 0x00000018); in rt61pci_config_ps()
983 rt2x00mmio_register_write(rt2x00dev, PCI_USEC_CSR, 0x00000020); in rt61pci_config_ps()
985 rt61pci_mcu_request(rt2x00dev, MCU_WAKEUP, 0xff, 0, 0); in rt61pci_config_ps()
989 static void rt61pci_config(struct rt2x00_dev *rt2x00dev, in rt61pci_config() argument
994 rt61pci_config_lna_gain(rt2x00dev, libconf); in rt61pci_config()
997 rt61pci_config_channel(rt2x00dev, &libconf->rf, in rt61pci_config()
1001 rt61pci_config_txpower(rt2x00dev, libconf->conf->power_level); in rt61pci_config()
1003 rt61pci_config_retry_limit(rt2x00dev, libconf); in rt61pci_config()
1005 rt61pci_config_ps(rt2x00dev, libconf); in rt61pci_config()
1011 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev, in rt61pci_link_stats() argument
1019 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR0); in rt61pci_link_stats()
1025 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR1); in rt61pci_link_stats()
1029 static inline void rt61pci_set_vgc(struct rt2x00_dev *rt2x00dev, in rt61pci_set_vgc() argument
1033 rt61pci_bbp_write(rt2x00dev, 17, vgc_level); in rt61pci_set_vgc()
1039 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev, in rt61pci_reset_tuner() argument
1042 rt61pci_set_vgc(rt2x00dev, qual, 0x20); in rt61pci_reset_tuner()
1045 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev, in rt61pci_link_tuner() argument
1054 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { in rt61pci_link_tuner()
1057 if (rt2x00_has_cap_external_lna_a(rt2x00dev)) { in rt61pci_link_tuner()
1064 if (rt2x00_has_cap_external_lna_bg(rt2x00dev)) { in rt61pci_link_tuner()
1074 if (!rt2x00dev->intf_associated) in rt61pci_link_tuner()
1081 rt61pci_set_vgc(rt2x00dev, qual, 0x60); in rt61pci_link_tuner()
1089 rt61pci_set_vgc(rt2x00dev, qual, up_bound); in rt61pci_link_tuner()
1097 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x10); in rt61pci_link_tuner()
1105 rt61pci_set_vgc(rt2x00dev, qual, low_bound + 0x08); in rt61pci_link_tuner()
1118 rt61pci_set_vgc(rt2x00dev, qual, up_bound); in rt61pci_link_tuner()
1129 rt61pci_set_vgc(rt2x00dev, qual, ++qual->vgc_level); in rt61pci_link_tuner()
1131 rt61pci_set_vgc(rt2x00dev, qual, --qual->vgc_level); in rt61pci_link_tuner()
1139 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt61pci_start_queue() local
1144 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); in rt61pci_start_queue()
1146 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_start_queue()
1149 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_start_queue()
1153 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_start_queue()
1162 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt61pci_kick_queue() local
1167 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_kick_queue()
1169 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1172 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_kick_queue()
1174 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1177 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_kick_queue()
1179 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1182 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_kick_queue()
1184 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_kick_queue()
1193 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev; in rt61pci_stop_queue() local
1198 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_stop_queue()
1200 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1203 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_stop_queue()
1205 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1208 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_stop_queue()
1210 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1213 reg = rt2x00mmio_register_read(rt2x00dev, TX_CNTL_CSR); in rt61pci_stop_queue()
1215 rt2x00mmio_register_write(rt2x00dev, TX_CNTL_CSR, reg); in rt61pci_stop_queue()
1218 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); in rt61pci_stop_queue()
1220 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_stop_queue()
1223 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_stop_queue()
1227 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_stop_queue()
1232 tasklet_kill(&rt2x00dev->tbtt_tasklet); in rt61pci_stop_queue()
1242 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev) in rt61pci_get_firmware_name() argument
1247 pci_read_config_word(to_pci_dev(rt2x00dev->dev), PCI_DEVICE_ID, &chip); in rt61pci_get_firmware_name()
1266 static int rt61pci_check_firmware(struct rt2x00_dev *rt2x00dev, in rt61pci_check_firmware() argument
1295 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, in rt61pci_load_firmware() argument
1305 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR0); in rt61pci_load_firmware()
1312 rt2x00_err(rt2x00dev, "Unstable hardware\n"); in rt61pci_load_firmware()
1321 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1322 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); in rt61pci_load_firmware()
1323 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0); in rt61pci_load_firmware()
1324 rt2x00mmio_register_write(rt2x00dev, HOST_CMD_CSR, 0); in rt61pci_load_firmware()
1332 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1334 rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE, in rt61pci_load_firmware()
1338 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1341 rt2x00mmio_register_write(rt2x00dev, MCU_CNTL_CSR, reg); in rt61pci_load_firmware()
1344 reg = rt2x00mmio_register_read(rt2x00dev, MCU_CNTL_CSR); in rt61pci_load_firmware()
1351 rt2x00_err(rt2x00dev, "MCU Control register not ready\n"); in rt61pci_load_firmware()
1366 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1368 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); in rt61pci_load_firmware()
1371 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1373 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); in rt61pci_load_firmware()
1375 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_load_firmware()
1423 static int rt61pci_init_queues(struct rt2x00_dev *rt2x00dev) in rt61pci_init_queues() argument
1431 reg = rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR0); in rt61pci_init_queues()
1433 rt2x00dev->tx[0].limit); in rt61pci_init_queues()
1435 rt2x00dev->tx[1].limit); in rt61pci_init_queues()
1437 rt2x00dev->tx[2].limit); in rt61pci_init_queues()
1439 rt2x00dev->tx[3].limit); in rt61pci_init_queues()
1440 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR0, reg); in rt61pci_init_queues()
1442 reg = rt2x00mmio_register_read(rt2x00dev, TX_RING_CSR1); in rt61pci_init_queues()
1444 rt2x00dev->tx[0].desc_size / 4); in rt61pci_init_queues()
1445 rt2x00mmio_register_write(rt2x00dev, TX_RING_CSR1, reg); in rt61pci_init_queues()
1447 entry_priv = rt2x00dev->tx[0].entries[0].priv_data; in rt61pci_init_queues()
1448 reg = rt2x00mmio_register_read(rt2x00dev, AC0_BASE_CSR); in rt61pci_init_queues()
1451 rt2x00mmio_register_write(rt2x00dev, AC0_BASE_CSR, reg); in rt61pci_init_queues()
1453 entry_priv = rt2x00dev->tx[1].entries[0].priv_data; in rt61pci_init_queues()
1454 reg = rt2x00mmio_register_read(rt2x00dev, AC1_BASE_CSR); in rt61pci_init_queues()
1457 rt2x00mmio_register_write(rt2x00dev, AC1_BASE_CSR, reg); in rt61pci_init_queues()
1459 entry_priv = rt2x00dev->tx[2].entries[0].priv_data; in rt61pci_init_queues()
1460 reg = rt2x00mmio_register_read(rt2x00dev, AC2_BASE_CSR); in rt61pci_init_queues()
1463 rt2x00mmio_register_write(rt2x00dev, AC2_BASE_CSR, reg); in rt61pci_init_queues()
1465 entry_priv = rt2x00dev->tx[3].entries[0].priv_data; in rt61pci_init_queues()
1466 reg = rt2x00mmio_register_read(rt2x00dev, AC3_BASE_CSR); in rt61pci_init_queues()
1469 rt2x00mmio_register_write(rt2x00dev, AC3_BASE_CSR, reg); in rt61pci_init_queues()
1471 reg = rt2x00mmio_register_read(rt2x00dev, RX_RING_CSR); in rt61pci_init_queues()
1472 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE, rt2x00dev->rx->limit); in rt61pci_init_queues()
1474 rt2x00dev->rx->desc_size / 4); in rt61pci_init_queues()
1476 rt2x00mmio_register_write(rt2x00dev, RX_RING_CSR, reg); in rt61pci_init_queues()
1478 entry_priv = rt2x00dev->rx->entries[0].priv_data; in rt61pci_init_queues()
1479 reg = rt2x00mmio_register_read(rt2x00dev, RX_BASE_CSR); in rt61pci_init_queues()
1482 rt2x00mmio_register_write(rt2x00dev, RX_BASE_CSR, reg); in rt61pci_init_queues()
1484 reg = rt2x00mmio_register_read(rt2x00dev, TX_DMA_DST_CSR); in rt61pci_init_queues()
1489 rt2x00mmio_register_write(rt2x00dev, TX_DMA_DST_CSR, reg); in rt61pci_init_queues()
1491 reg = rt2x00mmio_register_read(rt2x00dev, LOAD_TX_RING_CSR); in rt61pci_init_queues()
1496 rt2x00mmio_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg); in rt61pci_init_queues()
1498 reg = rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR); in rt61pci_init_queues()
1500 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); in rt61pci_init_queues()
1505 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev) in rt61pci_init_registers() argument
1509 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR0); in rt61pci_init_registers()
1513 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR0, reg); in rt61pci_init_registers()
1515 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR1); in rt61pci_init_registers()
1524 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR1, reg); in rt61pci_init_registers()
1529 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR2); in rt61pci_init_registers()
1538 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR2, reg); in rt61pci_init_registers()
1543 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR3); in rt61pci_init_registers()
1550 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR3, reg); in rt61pci_init_registers()
1552 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR7); in rt61pci_init_registers()
1557 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR7, reg); in rt61pci_init_registers()
1559 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR8); in rt61pci_init_registers()
1564 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR8, reg); in rt61pci_init_registers()
1566 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_init_registers()
1573 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_init_registers()
1575 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f); in rt61pci_init_registers()
1577 rt2x00mmio_register_write(rt2x00dev, MAC_CSR6, 0x00000fff); in rt61pci_init_registers()
1579 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR9); in rt61pci_init_registers()
1581 rt2x00mmio_register_write(rt2x00dev, MAC_CSR9, reg); in rt61pci_init_registers()
1583 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x0000071c); in rt61pci_init_registers()
1585 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE)) in rt61pci_init_registers()
1588 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, 0x0000e000); in rt61pci_init_registers()
1594 rt2x00mmio_register_write(rt2x00dev, SEC_CSR0, 0x00000000); in rt61pci_init_registers()
1595 rt2x00mmio_register_write(rt2x00dev, SEC_CSR1, 0x00000000); in rt61pci_init_registers()
1596 rt2x00mmio_register_write(rt2x00dev, SEC_CSR5, 0x00000000); in rt61pci_init_registers()
1598 rt2x00mmio_register_write(rt2x00dev, PHY_CSR1, 0x000023b0); in rt61pci_init_registers()
1599 rt2x00mmio_register_write(rt2x00dev, PHY_CSR5, 0x060a100c); in rt61pci_init_registers()
1600 rt2x00mmio_register_write(rt2x00dev, PHY_CSR6, 0x00080606); in rt61pci_init_registers()
1601 rt2x00mmio_register_write(rt2x00dev, PHY_CSR7, 0x00000a08); in rt61pci_init_registers()
1603 rt2x00mmio_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404); in rt61pci_init_registers()
1605 rt2x00mmio_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200); in rt61pci_init_registers()
1607 rt2x00mmio_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff); in rt61pci_init_registers()
1615 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE0, 0); in rt61pci_init_registers()
1616 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE1, 0); in rt61pci_init_registers()
1617 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE2, 0); in rt61pci_init_registers()
1618 rt2x00mmio_register_write(rt2x00dev, HW_BEACON_BASE3, 0); in rt61pci_init_registers()
1625 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR0); in rt61pci_init_registers()
1626 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR1); in rt61pci_init_registers()
1627 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR2); in rt61pci_init_registers()
1632 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); in rt61pci_init_registers()
1635 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1637 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); in rt61pci_init_registers()
1640 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1642 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR1); in rt61pci_init_registers()
1644 rt2x00mmio_register_write(rt2x00dev, MAC_CSR1, reg); in rt61pci_init_registers()
1649 static int rt61pci_wait_bbp_ready(struct rt2x00_dev *rt2x00dev) in rt61pci_wait_bbp_ready() argument
1655 value = rt61pci_bbp_read(rt2x00dev, 0); in rt61pci_wait_bbp_ready()
1661 rt2x00_err(rt2x00dev, "BBP register access failed, aborting\n"); in rt61pci_wait_bbp_ready()
1665 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev) in rt61pci_init_bbp() argument
1672 if (unlikely(rt61pci_wait_bbp_ready(rt2x00dev))) in rt61pci_init_bbp()
1675 rt61pci_bbp_write(rt2x00dev, 3, 0x00); in rt61pci_init_bbp()
1676 rt61pci_bbp_write(rt2x00dev, 15, 0x30); in rt61pci_init_bbp()
1677 rt61pci_bbp_write(rt2x00dev, 21, 0xc8); in rt61pci_init_bbp()
1678 rt61pci_bbp_write(rt2x00dev, 22, 0x38); in rt61pci_init_bbp()
1679 rt61pci_bbp_write(rt2x00dev, 23, 0x06); in rt61pci_init_bbp()
1680 rt61pci_bbp_write(rt2x00dev, 24, 0xfe); in rt61pci_init_bbp()
1681 rt61pci_bbp_write(rt2x00dev, 25, 0x0a); in rt61pci_init_bbp()
1682 rt61pci_bbp_write(rt2x00dev, 26, 0x0d); in rt61pci_init_bbp()
1683 rt61pci_bbp_write(rt2x00dev, 34, 0x12); in rt61pci_init_bbp()
1684 rt61pci_bbp_write(rt2x00dev, 37, 0x07); in rt61pci_init_bbp()
1685 rt61pci_bbp_write(rt2x00dev, 39, 0xf8); in rt61pci_init_bbp()
1686 rt61pci_bbp_write(rt2x00dev, 41, 0x60); in rt61pci_init_bbp()
1687 rt61pci_bbp_write(rt2x00dev, 53, 0x10); in rt61pci_init_bbp()
1688 rt61pci_bbp_write(rt2x00dev, 54, 0x18); in rt61pci_init_bbp()
1689 rt61pci_bbp_write(rt2x00dev, 60, 0x10); in rt61pci_init_bbp()
1690 rt61pci_bbp_write(rt2x00dev, 61, 0x04); in rt61pci_init_bbp()
1691 rt61pci_bbp_write(rt2x00dev, 62, 0x04); in rt61pci_init_bbp()
1692 rt61pci_bbp_write(rt2x00dev, 75, 0xfe); in rt61pci_init_bbp()
1693 rt61pci_bbp_write(rt2x00dev, 86, 0xfe); in rt61pci_init_bbp()
1694 rt61pci_bbp_write(rt2x00dev, 88, 0xfe); in rt61pci_init_bbp()
1695 rt61pci_bbp_write(rt2x00dev, 90, 0x0f); in rt61pci_init_bbp()
1696 rt61pci_bbp_write(rt2x00dev, 99, 0x00); in rt61pci_init_bbp()
1697 rt61pci_bbp_write(rt2x00dev, 102, 0x16); in rt61pci_init_bbp()
1698 rt61pci_bbp_write(rt2x00dev, 107, 0x04); in rt61pci_init_bbp()
1701 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i); in rt61pci_init_bbp()
1706 rt61pci_bbp_write(rt2x00dev, reg_id, value); in rt61pci_init_bbp()
1716 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev, in rt61pci_toggle_irq() argument
1728 reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR); in rt61pci_toggle_irq()
1729 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); in rt61pci_toggle_irq()
1731 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR); in rt61pci_toggle_irq()
1732 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg); in rt61pci_toggle_irq()
1739 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags); in rt61pci_toggle_irq()
1741 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); in rt61pci_toggle_irq()
1747 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_toggle_irq()
1749 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR); in rt61pci_toggle_irq()
1759 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_toggle_irq()
1761 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags); in rt61pci_toggle_irq()
1767 tasklet_kill(&rt2x00dev->txstatus_tasklet); in rt61pci_toggle_irq()
1768 tasklet_kill(&rt2x00dev->rxdone_tasklet); in rt61pci_toggle_irq()
1769 tasklet_kill(&rt2x00dev->autowake_tasklet); in rt61pci_toggle_irq()
1770 tasklet_kill(&rt2x00dev->tbtt_tasklet); in rt61pci_toggle_irq()
1774 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev) in rt61pci_enable_radio() argument
1781 if (unlikely(rt61pci_init_queues(rt2x00dev) || in rt61pci_enable_radio()
1782 rt61pci_init_registers(rt2x00dev) || in rt61pci_enable_radio()
1783 rt61pci_init_bbp(rt2x00dev))) in rt61pci_enable_radio()
1789 reg = rt2x00mmio_register_read(rt2x00dev, RX_CNTL_CSR); in rt61pci_enable_radio()
1791 rt2x00mmio_register_write(rt2x00dev, RX_CNTL_CSR, reg); in rt61pci_enable_radio()
1796 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev) in rt61pci_disable_radio() argument
1801 rt2x00mmio_register_write(rt2x00dev, MAC_CSR10, 0x00001818); in rt61pci_disable_radio()
1804 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state) in rt61pci_set_state() argument
1812 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR12); in rt61pci_set_state()
1815 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); in rt61pci_set_state()
1823 reg2 = rt2x00mmio_register_read(rt2x00dev, MAC_CSR12); in rt61pci_set_state()
1827 rt2x00mmio_register_write(rt2x00dev, MAC_CSR12, reg); in rt61pci_set_state()
1834 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev, in rt61pci_set_device_state() argument
1841 retval = rt61pci_enable_radio(rt2x00dev); in rt61pci_set_device_state()
1844 rt61pci_disable_radio(rt2x00dev); in rt61pci_set_device_state()
1848 rt61pci_toggle_irq(rt2x00dev, state); in rt61pci_set_device_state()
1854 retval = rt61pci_set_state(rt2x00dev, state); in rt61pci_set_device_state()
1862 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n", in rt61pci_set_device_state()
1911 TXPOWER_TO_DEV(entry->queue->rt2x00dev->tx_power)); in rt61pci_write_tx_desc()
1971 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; in rt61pci_write_beacon() local
1981 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_write_beacon()
1984 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_write_beacon()
1994 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry); in rt61pci_write_beacon()
2001 rt2x00_err(rt2x00dev, "Failure padding beacon, aborting\n"); in rt61pci_write_beacon()
2004 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg); in rt61pci_write_beacon()
2009 rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base, in rt61pci_write_beacon()
2011 rt2x00mmio_register_multiwrite(rt2x00dev, beacon_base + TXINFO_SIZE, in rt61pci_write_beacon()
2021 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR10, 0x00001008); in rt61pci_write_beacon()
2024 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_write_beacon()
2035 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; in rt61pci_clear_beacon() local
2042 orig_reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR9); in rt61pci_clear_beacon()
2045 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, reg); in rt61pci_clear_beacon()
2050 rt2x00mmio_register_write(rt2x00dev, in rt61pci_clear_beacon()
2056 rt2x00mmio_register_write(rt2x00dev, TXRX_CSR9, orig_reg); in rt61pci_clear_beacon()
2062 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1) in rt61pci_agc_to_rssi() argument
2064 u8 offset = rt2x00dev->lna_gain; in rt61pci_agc_to_rssi()
2082 if (rt2x00dev->curr_band == NL80211_BAND_5GHZ) { in rt61pci_agc_to_rssi()
2093 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev; in rt61pci_fill_rxdone() local
2141 rxdesc->rssi = rt61pci_agc_to_rssi(rt2x00dev, word1); in rt61pci_fill_rxdone()
2155 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev) in rt61pci_txdone() argument
2177 for (i = 0; i < rt2x00dev->tx->limit; i++) { in rt61pci_txdone()
2178 reg = rt2x00mmio_register_read(rt2x00dev, STA_CSR4); in rt61pci_txdone()
2187 queue = rt2x00queue_get_tx_queue(rt2x00dev, type); in rt61pci_txdone()
2212 rt2x00_warn(rt2x00dev, "TX status report missed for entry %d\n", in rt61pci_txdone()
2246 static void rt61pci_wakeup(struct rt2x00_dev *rt2x00dev) in rt61pci_wakeup() argument
2248 struct rt2x00lib_conf libconf = { .conf = &rt2x00dev->hw->conf }; in rt61pci_wakeup()
2250 rt61pci_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS); in rt61pci_wakeup()
2253 static inline void rt61pci_enable_interrupt(struct rt2x00_dev *rt2x00dev, in rt61pci_enable_interrupt() argument
2262 spin_lock_irq(&rt2x00dev->irqmask_lock); in rt61pci_enable_interrupt()
2264 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); in rt61pci_enable_interrupt()
2266 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_enable_interrupt()
2268 spin_unlock_irq(&rt2x00dev->irqmask_lock); in rt61pci_enable_interrupt()
2271 static void rt61pci_enable_mcu_interrupt(struct rt2x00_dev *rt2x00dev, in rt61pci_enable_mcu_interrupt() argument
2280 spin_lock_irq(&rt2x00dev->irqmask_lock); in rt61pci_enable_mcu_interrupt()
2282 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR); in rt61pci_enable_mcu_interrupt()
2284 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_enable_mcu_interrupt()
2286 spin_unlock_irq(&rt2x00dev->irqmask_lock); in rt61pci_enable_mcu_interrupt()
2291 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; in rt61pci_txstatus_tasklet() local
2292 rt61pci_txdone(rt2x00dev); in rt61pci_txstatus_tasklet()
2293 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_txstatus_tasklet()
2294 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TXDONE); in rt61pci_txstatus_tasklet()
2299 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; in rt61pci_tbtt_tasklet() local
2300 rt2x00lib_beacondone(rt2x00dev); in rt61pci_tbtt_tasklet()
2301 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_tbtt_tasklet()
2302 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_BEACON_DONE); in rt61pci_tbtt_tasklet()
2307 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; in rt61pci_rxdone_tasklet() local
2308 if (rt2x00mmio_rxdone(rt2x00dev)) in rt61pci_rxdone_tasklet()
2309 tasklet_schedule(&rt2x00dev->rxdone_tasklet); in rt61pci_rxdone_tasklet()
2310 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_rxdone_tasklet()
2311 rt61pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RXDONE); in rt61pci_rxdone_tasklet()
2316 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data; in rt61pci_autowake_tasklet() local
2317 rt61pci_wakeup(rt2x00dev); in rt61pci_autowake_tasklet()
2318 rt2x00mmio_register_write(rt2x00dev, in rt61pci_autowake_tasklet()
2320 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_autowake_tasklet()
2321 rt61pci_enable_mcu_interrupt(rt2x00dev, MCU_INT_MASK_CSR_TWAKEUP); in rt61pci_autowake_tasklet()
2326 struct rt2x00_dev *rt2x00dev = dev_instance; in rt61pci_interrupt() local
2334 reg_mcu = rt2x00mmio_register_read(rt2x00dev, MCU_INT_SOURCE_CSR); in rt61pci_interrupt()
2335 rt2x00mmio_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu); in rt61pci_interrupt()
2337 reg = rt2x00mmio_register_read(rt2x00dev, INT_SOURCE_CSR); in rt61pci_interrupt()
2338 rt2x00mmio_register_write(rt2x00dev, INT_SOURCE_CSR, reg); in rt61pci_interrupt()
2343 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags)) in rt61pci_interrupt()
2350 tasklet_schedule(&rt2x00dev->rxdone_tasklet); in rt61pci_interrupt()
2353 tasklet_schedule(&rt2x00dev->txstatus_tasklet); in rt61pci_interrupt()
2356 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet); in rt61pci_interrupt()
2359 tasklet_schedule(&rt2x00dev->autowake_tasklet); in rt61pci_interrupt()
2373 spin_lock(&rt2x00dev->irqmask_lock); in rt61pci_interrupt()
2375 reg = rt2x00mmio_register_read(rt2x00dev, INT_MASK_CSR); in rt61pci_interrupt()
2377 rt2x00mmio_register_write(rt2x00dev, INT_MASK_CSR, reg); in rt61pci_interrupt()
2379 reg = rt2x00mmio_register_read(rt2x00dev, MCU_INT_MASK_CSR); in rt61pci_interrupt()
2381 rt2x00mmio_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg); in rt61pci_interrupt()
2383 spin_unlock(&rt2x00dev->irqmask_lock); in rt61pci_interrupt()
2391 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev) in rt61pci_validate_eeprom() argument
2399 reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR); in rt61pci_validate_eeprom()
2401 eeprom.data = rt2x00dev; in rt61pci_validate_eeprom()
2411 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom, in rt61pci_validate_eeprom()
2417 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0); in rt61pci_validate_eeprom()
2418 rt2x00lib_set_mac_address(rt2x00dev, mac); in rt61pci_validate_eeprom()
2420 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA); in rt61pci_validate_eeprom()
2431 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word); in rt61pci_validate_eeprom()
2432 rt2x00_eeprom_dbg(rt2x00dev, "Antenna: 0x%04x\n", word); in rt61pci_validate_eeprom()
2435 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC); in rt61pci_validate_eeprom()
2444 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word); in rt61pci_validate_eeprom()
2445 rt2x00_eeprom_dbg(rt2x00dev, "NIC: 0x%04x\n", word); in rt61pci_validate_eeprom()
2448 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_LED); in rt61pci_validate_eeprom()
2452 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word); in rt61pci_validate_eeprom()
2453 rt2x00_eeprom_dbg(rt2x00dev, "Led: 0x%04x\n", word); in rt61pci_validate_eeprom()
2456 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ); in rt61pci_validate_eeprom()
2460 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word); in rt61pci_validate_eeprom()
2461 rt2x00_eeprom_dbg(rt2x00dev, "Freq: 0x%04x\n", word); in rt61pci_validate_eeprom()
2464 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG); in rt61pci_validate_eeprom()
2468 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); in rt61pci_validate_eeprom()
2469 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word); in rt61pci_validate_eeprom()
2477 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word); in rt61pci_validate_eeprom()
2480 word = rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A); in rt61pci_validate_eeprom()
2484 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); in rt61pci_validate_eeprom()
2485 rt2x00_eeprom_dbg(rt2x00dev, "RSSI OFFSET A: 0x%04x\n", word); in rt61pci_validate_eeprom()
2493 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word); in rt61pci_validate_eeprom()
2499 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev) in rt61pci_init_eeprom() argument
2508 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA); in rt61pci_init_eeprom()
2514 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR0); in rt61pci_init_eeprom()
2515 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET), in rt61pci_init_eeprom()
2518 if (!rt2x00_rf(rt2x00dev, RF5225) && in rt61pci_init_eeprom()
2519 !rt2x00_rf(rt2x00dev, RF5325) && in rt61pci_init_eeprom()
2520 !rt2x00_rf(rt2x00dev, RF2527) && in rt61pci_init_eeprom()
2521 !rt2x00_rf(rt2x00dev, RF2529)) { in rt61pci_init_eeprom()
2522 rt2x00_err(rt2x00dev, "Invalid RF chipset detected\n"); in rt61pci_init_eeprom()
2530 __set_bit(CAPABILITY_DOUBLE_ANTENNA, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2535 rt2x00dev->default_ant.tx = in rt61pci_init_eeprom()
2537 rt2x00dev->default_ant.rx = in rt61pci_init_eeprom()
2544 __set_bit(CAPABILITY_FRAME_TYPE, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2550 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2555 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ); in rt61pci_init_eeprom()
2557 __set_bit(CAPABILITY_RF_SEQUENCE, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2559 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET); in rt61pci_init_eeprom()
2564 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC); in rt61pci_init_eeprom()
2567 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2569 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags); in rt61pci_init_eeprom()
2576 if (rt2x00_rf(rt2x00dev, RF2529) && in rt61pci_init_eeprom()
2577 !rt2x00_has_cap_double_antenna(rt2x00dev)) { in rt61pci_init_eeprom()
2578 rt2x00dev->default_ant.rx = in rt61pci_init_eeprom()
2580 rt2x00dev->default_ant.tx = in rt61pci_init_eeprom()
2584 rt2x00dev->default_ant.tx = ANTENNA_SW_DIVERSITY; in rt61pci_init_eeprom()
2586 rt2x00dev->default_ant.rx = ANTENNA_SW_DIVERSITY; in rt61pci_init_eeprom()
2595 eeprom = rt2x00_eeprom_read(rt2x00dev, EEPROM_LED); in rt61pci_init_eeprom()
2598 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO); in rt61pci_init_eeprom()
2599 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC); in rt61pci_init_eeprom()
2601 rt61pci_init_led(rt2x00dev, &rt2x00dev->led_qual, in rt61pci_init_eeprom()
2604 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value); in rt61pci_init_eeprom()
2605 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_0, in rt61pci_init_eeprom()
2608 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_1, in rt61pci_init_eeprom()
2611 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_2, in rt61pci_init_eeprom()
2614 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_3, in rt61pci_init_eeprom()
2617 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_GPIO_4, in rt61pci_init_eeprom()
2620 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_ACT, in rt61pci_init_eeprom()
2622 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_BG, in rt61pci_init_eeprom()
2625 rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_POLARITY_READY_A, in rt61pci_init_eeprom()
2747 static int rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev) in rt61pci_probe_hw_mode() argument
2749 struct hw_mode_spec *spec = &rt2x00dev->spec; in rt61pci_probe_hw_mode()
2757 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; in rt61pci_probe_hw_mode()
2762 ieee80211_hw_set(rt2x00dev->hw, PS_NULLFUNC_STACK); in rt61pci_probe_hw_mode()
2763 ieee80211_hw_set(rt2x00dev->hw, SUPPORTS_PS); in rt61pci_probe_hw_mode()
2764 ieee80211_hw_set(rt2x00dev->hw, HOST_BROADCAST_PS_BUFFERING); in rt61pci_probe_hw_mode()
2765 ieee80211_hw_set(rt2x00dev->hw, SIGNAL_DBM); in rt61pci_probe_hw_mode()
2767 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev); in rt61pci_probe_hw_mode()
2768 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw, in rt61pci_probe_hw_mode()
2769 rt2x00_eeprom_addr(rt2x00dev, in rt61pci_probe_hw_mode()
2781 rt2x00dev->hw->max_rates = 1; in rt61pci_probe_hw_mode()
2782 rt2x00dev->hw->max_report_rates = 7; in rt61pci_probe_hw_mode()
2783 rt2x00dev->hw->max_rate_tries = 1; in rt61pci_probe_hw_mode()
2791 if (!rt2x00_has_cap_rf_sequence(rt2x00dev)) { in rt61pci_probe_hw_mode()
2799 if (rt2x00_rf(rt2x00dev, RF5225) || rt2x00_rf(rt2x00dev, RF5325)) { in rt61pci_probe_hw_mode()
2813 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START); in rt61pci_probe_hw_mode()
2820 tx_power = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START); in rt61pci_probe_hw_mode()
2831 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev) in rt61pci_probe_hw() argument
2839 rt2x00mmio_register_write(rt2x00dev, SOFT_RESET_CSR, 0x00000007); in rt61pci_probe_hw()
2844 retval = rt61pci_validate_eeprom(rt2x00dev); in rt61pci_probe_hw()
2848 retval = rt61pci_init_eeprom(rt2x00dev); in rt61pci_probe_hw()
2856 reg = rt2x00mmio_register_read(rt2x00dev, MAC_CSR13); in rt61pci_probe_hw()
2858 rt2x00mmio_register_write(rt2x00dev, MAC_CSR13, reg); in rt61pci_probe_hw()
2863 retval = rt61pci_probe_hw_mode(rt2x00dev); in rt61pci_probe_hw()
2871 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2876 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2877 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2879 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2880 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags); in rt61pci_probe_hw()
2885 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET; in rt61pci_probe_hw()
2897 struct rt2x00_dev *rt2x00dev = hw->priv; in rt61pci_conf_tx() local
2921 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx); in rt61pci_conf_tx()
2928 reg = rt2x00mmio_register_read(rt2x00dev, offset); in rt61pci_conf_tx()
2930 rt2x00mmio_register_write(rt2x00dev, offset, reg); in rt61pci_conf_tx()
2936 reg = rt2x00mmio_register_read(rt2x00dev, AIFSN_CSR); in rt61pci_conf_tx()
2938 rt2x00mmio_register_write(rt2x00dev, AIFSN_CSR, reg); in rt61pci_conf_tx()
2940 reg = rt2x00mmio_register_read(rt2x00dev, CWMIN_CSR); in rt61pci_conf_tx()
2942 rt2x00mmio_register_write(rt2x00dev, CWMIN_CSR, reg); in rt61pci_conf_tx()
2944 reg = rt2x00mmio_register_read(rt2x00dev, CWMAX_CSR); in rt61pci_conf_tx()
2946 rt2x00mmio_register_write(rt2x00dev, CWMAX_CSR, reg); in rt61pci_conf_tx()
2953 struct rt2x00_dev *rt2x00dev = hw->priv; in rt61pci_get_tsf() local
2957 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR13); in rt61pci_get_tsf()
2959 reg = rt2x00mmio_register_read(rt2x00dev, TXRX_CSR12); in rt61pci_get_tsf()