645 	u8 val8;  in rtl8192eu_init_phy_bb()  local
653 	val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;  in rtl8192eu_init_phy_bb()
654 	rtl8xxxu_write8(priv, REG_RF_CTRL, val8);  in rtl8192eu_init_phy_bb()
660 	val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;  in rtl8192eu_init_phy_bb()
661 	rtl8xxxu_write8(priv, REG_RF_CTRL, val8);  in rtl8192eu_init_phy_bb()
1294 	u8 val8;  in rtl8192e_crystal_afe_adjust()  local
1300 	val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);  in rtl8192e_crystal_afe_adjust()
1301 	val8 &= 0xfb;  in rtl8192e_crystal_afe_adjust()
1302 	rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);  in rtl8192e_crystal_afe_adjust()
1312 	val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);  in rtl8192e_crystal_afe_adjust()
1313 	val8 &= 0xbf;  in rtl8192e_crystal_afe_adjust()
1314 	rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);  in rtl8192e_crystal_afe_adjust()
1326 	u8 val8;  in rtl8192e_disabled_to_emu()  local
1329 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);  in rtl8192e_disabled_to_emu()
1330 	val8 &= ~(BIT(3) | BIT(4));  in rtl8192e_disabled_to_emu()
1331 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);  in rtl8192e_disabled_to_emu()
1336 	u8 val8;  in rtl8192e_emu_to_active()  local
1341 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);  in rtl8192e_emu_to_active()
1342 	val8 &= ~BIT(7);  in rtl8192e_emu_to_active()
1343 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);  in rtl8192e_emu_to_active()
1346 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);  in rtl8192e_emu_to_active()
1347 	val8 &= ~BIT(2);  in rtl8192e_emu_to_active()
1348 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);  in rtl8192e_emu_to_active()
1351 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);  in rtl8192e_emu_to_active()
1352 	val8 &= ~(BIT(3) | BIT(4));  in rtl8192e_emu_to_active()
1353 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);  in rtl8192e_emu_to_active()
1372 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);  in rtl8192e_emu_to_active()
1373 	val8 |= BIT(0);  in rtl8192e_emu_to_active()
1374 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);  in rtl8192e_emu_to_active()
1402 	u8 val8;  in rtl8192eu_active_to_lps()  local
1429 	val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);  in rtl8192eu_active_to_lps()
1430 	val8 &= ~SYS_FUNC_BBRSTB;  in rtl8192eu_active_to_lps()
1431 	rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);  in rtl8192eu_active_to_lps()
1436 	val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);  in rtl8192eu_active_to_lps()
1437 	val8 &= ~SYS_FUNC_BB_GLB_RSTN;  in rtl8192eu_active_to_lps()
1438 	rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);  in rtl8192eu_active_to_lps()
1450 	val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);  in rtl8192eu_active_to_lps()
1451 	val8 |= DUAL_TSF_TX_OK;  in rtl8192eu_active_to_lps()
1452 	rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);  in rtl8192eu_active_to_lps()
1460 	u8 val8;  in rtl8192eu_active_to_emu()  local
1464 	val8 = rtl8xxxu_read8(priv, REG_RF_CTRL);  in rtl8192eu_active_to_emu()
1465 	val8 &= ~RF_ENABLE;  in rtl8192eu_active_to_emu()
1466 	rtl8xxxu_write8(priv, REG_RF_CTRL, val8);  in rtl8192eu_active_to_emu()
1469 	val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);  in rtl8192eu_active_to_emu()
1470 	val8 &= ~LEDCFG2_DPDT_SELECT;  in rtl8192eu_active_to_emu()
1471 	rtl8xxxu_write8(priv, REG_LEDCFG2, val8);  in rtl8192eu_active_to_emu()
1474 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);  in rtl8192eu_active_to_emu()
1475 	val8 |= BIT(1);  in rtl8192eu_active_to_emu()
1476 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);  in rtl8192eu_active_to_emu()
1479 		val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);  in rtl8192eu_active_to_emu()
1480 		if ((val8 & BIT(1)) == 0)  in rtl8192eu_active_to_emu()
1498 	u8 val8;  in rtl8192eu_emu_to_disabled()  local
1501 	val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);  in rtl8192eu_emu_to_disabled()
1502 	val8 &= ~(BIT(3) | BIT(4));  in rtl8192eu_emu_to_disabled()
1503 	val8 |= BIT(3);  in rtl8192eu_emu_to_disabled()
1504 	rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);  in rtl8192eu_emu_to_disabled()
1561 	u8 val8;  in rtl8192eu_power_off()  local
1566 	val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);  in rtl8192eu_power_off()
1567 	val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE;  in rtl8192eu_power_off()
1568 	rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);  in rtl8192eu_power_off()
1596 	u8 val8;  in rtl8192e_enable_rf()  local
1602 	val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG);  in rtl8192e_enable_rf()
1603 	val8 |= BIT(5);  in rtl8192e_enable_rf()
1604 	rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8);  in rtl8192e_enable_rf()
1629 	val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1);  in rtl8192e_enable_rf()
1630 	val8 &= ~BIT(0);  in rtl8192e_enable_rf()
1631 	rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8);  in rtl8192e_enable_rf()