Lines Matching refs:minfo
92 void matroxfb_DAC_out(const struct matrox_fb_info *minfo, int reg, int val) in matroxfb_DAC_out() argument
99 int matroxfb_DAC_in(const struct matrox_fb_info *minfo, int reg) in matroxfb_DAC_in() argument
189 int matroxfb_vgaHWinit(struct matrox_fb_info *minfo, struct my_timming *m) in matroxfb_vgaHWinit() argument
196 struct matrox_hw_state * const hw = &minfo->hw; in matroxfb_vgaHWinit()
246 divider = minfo->curr.final_bppShift; in matroxfb_vgaHWinit()
276 wd = minfo->fbcon.var.xres_virtual * minfo->curr.final_bppShift / 64; in matroxfb_vgaHWinit()
293 if (minfo->outputs[1].src == MATROXFB_SRC_CRTC1) in matroxfb_vgaHWinit()
337 void matroxfb_vgaHWrestore(struct matrox_fb_info *minfo) in matroxfb_vgaHWrestore() argument
340 struct matrox_hw_state * const hw = &minfo->hw; in matroxfb_vgaHWrestore()
529 static int parse_pins1(struct matrox_fb_info *minfo, in parse_pins1() argument
542 minfo->limits.pixel.vcomax = maxdac; in parse_pins1()
543 minfo->values.pll.system = get_unaligned_le16(bd->pins + 28) ? in parse_pins1()
546 minfo->features.pll.ref_freq = 14318; in parse_pins1()
547 minfo->values.reg.mctlwtst = 0x00030101; in parse_pins1()
551 static void default_pins1(struct matrox_fb_info *minfo) in default_pins1() argument
554 minfo->limits.pixel.vcomax = 220000; in default_pins1()
555 minfo->values.pll.system = 50000; in default_pins1()
556 minfo->features.pll.ref_freq = 14318; in default_pins1()
557 minfo->values.reg.mctlwtst = 0x00030101; in default_pins1()
560 static int parse_pins2(struct matrox_fb_info *minfo, in parse_pins2() argument
563 minfo->limits.pixel.vcomax = in parse_pins2()
564 minfo->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000); in parse_pins2()
565 minfo->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) | in parse_pins2()
569 minfo->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000); in parse_pins2()
570 minfo->features.pll.ref_freq = 14318; in parse_pins2()
574 static void default_pins2(struct matrox_fb_info *minfo) in default_pins2() argument
577 minfo->limits.pixel.vcomax = in default_pins2()
578 minfo->limits.system.vcomax = 230000; in default_pins2()
579 minfo->values.reg.mctlwtst = 0x00030101; in default_pins2()
580 minfo->values.pll.system = 50000; in default_pins2()
581 minfo->features.pll.ref_freq = 14318; in default_pins2()
584 static int parse_pins3(struct matrox_fb_info *minfo, in parse_pins3() argument
587 minfo->limits.pixel.vcomax = in parse_pins3()
588 minfo->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000); in parse_pins3()
589 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 48) == 0xFFFFFFFF ? in parse_pins3()
592 minfo->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) | in parse_pins3()
596 minfo->values.reg.opt = (bd->pins[54] & 7) << 10; in parse_pins3()
597 minfo->values.reg.opt2 = bd->pins[58] << 12; in parse_pins3()
598 minfo->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000; in parse_pins3()
602 static void default_pins3(struct matrox_fb_info *minfo) in default_pins3() argument
605 minfo->limits.pixel.vcomax = in default_pins3()
606 minfo->limits.system.vcomax = 230000; in default_pins3()
607 minfo->values.reg.mctlwtst = 0x01250A21; in default_pins3()
608 minfo->values.reg.memrdbk = 0x00000000; in default_pins3()
609 minfo->values.reg.opt = 0x00000C00; in default_pins3()
610 minfo->values.reg.opt2 = 0x00000000; in default_pins3()
611 minfo->features.pll.ref_freq = 27000; in default_pins3()
614 static int parse_pins4(struct matrox_fb_info *minfo, in parse_pins4() argument
617 minfo->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000; in parse_pins4()
618 …minfo->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 38]… in parse_pins4()
619 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 71); in parse_pins4()
620 minfo->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) | in parse_pins4()
624 minfo->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) | in parse_pins4()
627 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 67); in parse_pins4()
628 minfo->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000; in parse_pins4()
629 minfo->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000; in parse_pins4()
633 static void default_pins4(struct matrox_fb_info *minfo) in default_pins4() argument
636 minfo->limits.pixel.vcomax = in default_pins4()
637 minfo->limits.system.vcomax = 252000; in default_pins4()
638 minfo->values.reg.mctlwtst = 0x04A450A1; in default_pins4()
639 minfo->values.reg.memrdbk = 0x000000E7; in default_pins4()
640 minfo->values.reg.opt = 0x10000400; in default_pins4()
641 minfo->values.reg.opt3 = 0x0190A419; in default_pins4()
642 minfo->values.pll.system = 200000; in default_pins4()
643 minfo->features.pll.ref_freq = 27000; in default_pins4()
646 static int parse_pins5(struct matrox_fb_info *minfo, in parse_pins5() argument
653 minfo->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult; in parse_pins5()
654 …minfo->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? minfo->limits.pixel.vcomax : bd->pins[ 36]… in parse_pins5()
655 …minfo->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? minfo->limits.system.vcomax : bd->pins[ 37]… in parse_pins5()
656 minfo->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult; in parse_pins5()
657 …minfo->limits.system.vcomin = (bd->pins[121] == 0xFF) ? minfo->limits.pixel.vcomin : bd->pins[121]… in parse_pins5()
658 …minfo->limits.video.vcomin = (bd->pins[122] == 0xFF) ? minfo->limits.system.vcomin : bd->pins[122]… in parse_pins5()
659 minfo->values.pll.system = in parse_pins5()
660 minfo->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000; in parse_pins5()
661 minfo->values.reg.opt = get_unaligned_le32(bd->pins + 48); in parse_pins5()
662 minfo->values.reg.opt2 = get_unaligned_le32(bd->pins + 52); in parse_pins5()
663 minfo->values.reg.opt3 = get_unaligned_le32(bd->pins + 94); in parse_pins5()
664 minfo->values.reg.mctlwtst = get_unaligned_le32(bd->pins + 98); in parse_pins5()
665 minfo->values.reg.memmisc = get_unaligned_le32(bd->pins + 102); in parse_pins5()
666 minfo->values.reg.memrdbk = get_unaligned_le32(bd->pins + 106); in parse_pins5()
667 minfo->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000; in parse_pins5()
668 minfo->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20; in parse_pins5()
669 minfo->values.memory.dll = (bd->pins[115] & 0x02) != 0; in parse_pins5()
670 minfo->values.memory.emrswen = (bd->pins[115] & 0x01) != 0; in parse_pins5()
671 minfo->values.reg.maccess = minfo->values.memory.emrswen ? 0x00004000 : 0x00000000; in parse_pins5()
673 minfo->values.reg.mctlwtst_core = minfo->values.reg.mctlwtst; in parse_pins5()
676 minfo->values.reg.mctlwtst_core = (minfo->values.reg.mctlwtst & ~7) | in parse_pins5()
677 wtst_xlat[minfo->values.reg.mctlwtst & 7]; in parse_pins5()
679 minfo->max_pixel_clock_panellink = bd->pins[47] * 4000; in parse_pins5()
683 static void default_pins5(struct matrox_fb_info *minfo) in default_pins5() argument
686 minfo->limits.pixel.vcomax = in default_pins5()
687 minfo->limits.system.vcomax = in default_pins5()
688 minfo->limits.video.vcomax = 600000; in default_pins5()
689 minfo->limits.pixel.vcomin = in default_pins5()
690 minfo->limits.system.vcomin = in default_pins5()
691 minfo->limits.video.vcomin = 256000; in default_pins5()
692 minfo->values.pll.system = in default_pins5()
693 minfo->values.pll.video = 284000; in default_pins5()
694 minfo->values.reg.opt = 0x404A1160; in default_pins5()
695 minfo->values.reg.opt2 = 0x0000AC00; in default_pins5()
696 minfo->values.reg.opt3 = 0x0090A409; in default_pins5()
697 minfo->values.reg.mctlwtst_core = in default_pins5()
698 minfo->values.reg.mctlwtst = 0x0C81462B; in default_pins5()
699 minfo->values.reg.memmisc = 0x80000004; in default_pins5()
700 minfo->values.reg.memrdbk = 0x01001103; in default_pins5()
701 minfo->features.pll.ref_freq = 27000; in default_pins5()
702 minfo->values.memory.ddr = 1; in default_pins5()
703 minfo->values.memory.dll = 1; in default_pins5()
704 minfo->values.memory.emrswen = 1; in default_pins5()
705 minfo->values.reg.maccess = 0x00004000; in default_pins5()
708 static int matroxfb_set_limits(struct matrox_fb_info *minfo, in matroxfb_set_limits() argument
714 switch (minfo->chip) { in matroxfb_set_limits()
715 case MGA_2064: default_pins1(minfo); break; in matroxfb_set_limits()
718 case MGA_1164: default_pins2(minfo); break; in matroxfb_set_limits()
720 case MGA_G200: default_pins3(minfo); break; in matroxfb_set_limits()
721 case MGA_G400: default_pins4(minfo); break; in matroxfb_set_limits()
723 case MGA_G550: default_pins5(minfo); break; in matroxfb_set_limits()
748 return parse_pins1(minfo, bd); in matroxfb_set_limits()
750 return parse_pins2(minfo, bd); in matroxfb_set_limits()
752 return parse_pins3(minfo, bd); in matroxfb_set_limits()
754 return parse_pins4(minfo, bd); in matroxfb_set_limits()
756 return parse_pins5(minfo, bd); in matroxfb_set_limits()
763 void matroxfb_read_pins(struct matrox_fb_info *minfo) in matroxfb_read_pins() argument
768 struct pci_dev *pdev = minfo->pcidev; in matroxfb_read_pins()
770 memset(&minfo->bios, 0, sizeof(minfo->bios)); in matroxfb_read_pins()
774 pci_read_config_dword(pdev, minfo->devflags.fbResource, &fbbase); in matroxfb_read_pins()
776 parse_bios(vaddr_va(minfo->video.vbase), &minfo->bios); in matroxfb_read_pins()
780 if (!minfo->bios.bios_valid) { in matroxfb_read_pins()
794 parse_bios(b, &minfo->bios); in matroxfb_read_pins()
800 matroxfb_set_limits(minfo, &minfo->bios); in matroxfb_read_pins()
802 (minfo->values.reg.opt & 0x1C00) >> 10); in matroxfb_read_pins()