132 	struct lcd_ctrl_extif	*extif;  member
144 	hwa742.extif->set_bits_per_cycle(8);  in hwa742_read_reg()
145 	hwa742.extif->write_command(&reg, 1);  in hwa742_read_reg()
146 	hwa742.extif->read_data(&data, 1);  in hwa742_read_reg()
153 	hwa742.extif->set_bits_per_cycle(8);  in hwa742_write_reg()
154 	hwa742.extif->write_command(&reg, 1);  in hwa742_write_reg()
155 	hwa742.extif->write_data(&data, 1);  in hwa742_write_reg()
174 	hwa742.extif->set_bits_per_cycle(8);  in set_window_regs()
177 	hwa742.extif->write_command(&cmd, 1);  in set_window_regs()
179 	hwa742.extif->write_data(tmp, 8);  in set_window_regs()
211 		hwa742.extif->enable_tearsync(1, 0);  in enable_tearsync()
216 		hwa742.extif->enable_tearsync(1, 0);  in enable_tearsync()
222 		hwa742.extif->enable_tearsync(1, 0);  in enable_tearsync()
226 	hwa742.extif->enable_tearsync(1, y + 1);  in enable_tearsync()
233 	hwa742.extif->enable_tearsync(0, 0);  in disable_tearsync()
402 	hwa742.extif->set_bits_per_cycle(16);  in send_frame_handler()
405 	hwa742.extif->transfer_area(w, h, request_complete, req);  in send_frame_handler()
678 	return hwa742.extif->convert_timings(t);  in calc_reg_timing()
729 	return hwa742.extif->convert_timings(t);  in calc_lut_timing()
737 	hwa742.extif->get_clk_info(&hwa742.extif_clk_period, &max_clk_div);  in calc_extif_timings()
814 	if (hwa742.extif->get_max_tx_rate != NULL) {  in setup_tearsync()
820 		unsigned long max_tx_rate = hwa742.extif->get_max_tx_rate();  in setup_tearsync()
894 	return hwa742.extif->setup_tearsync(1, hs, vs,  in setup_tearsync()
947 	hwa742.extif = fbdev->ext_if;  in hwa742_init()
959 	if ((r = hwa742.extif->init(fbdev)) < 0)  in hwa742_init()
965 	hwa742.extif->set_timings(&hwa742.reg_timings);  in hwa742_init()
971 	hwa742.extif->set_timings(&hwa742.reg_timings);  in hwa742_init()
995 	hwa742.max_transmit_size = hwa742.extif->max_transmit_size;  in hwa742_init()
1029 	hwa742.extif->cleanup();  in hwa742_init()
1039 	hwa742.extif->cleanup();  in hwa742_cleanup()