Lines Matching refs:clocks
77 afe_priv->clocks[i] = devm_clk_get(afe->dev, aud_clks[i]); in mt2701_init_clock()
78 if (IS_ERR(afe_priv->clocks[i])) { in mt2701_init_clock()
149 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]); in mt2701_turn_on_a1sys_clock()
156 ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL], in mt2701_turn_on_a1sys_clock()
157 afe_priv->clocks[MT2701_AUD_AUD1PLL_98M]); in mt2701_turn_on_a1sys_clock()
166 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]); in mt2701_turn_on_a1sys_clock()
175 ret = clk_set_rate(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV], in mt2701_turn_on_a1sys_clock()
185 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]); in mt2701_turn_on_a1sys_clock()
193 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); in mt2701_turn_on_a1sys_clock()
203 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); in mt2701_turn_on_a1sys_clock()
205 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]); in mt2701_turn_on_a1sys_clock()
207 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]); in mt2701_turn_on_a1sys_clock()
209 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]); in mt2701_turn_on_a1sys_clock()
218 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); in mt2701_turn_off_a1sys_clock()
219 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_48K_TIMING]); in mt2701_turn_off_a1sys_clock()
220 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_DIV]); in mt2701_turn_off_a1sys_clock()
221 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]); in mt2701_turn_off_a1sys_clock()
230 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]); in mt2701_turn_on_a2sys_clock()
237 ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL], in mt2701_turn_on_a2sys_clock()
238 afe_priv->clocks[MT2701_AUD_AUD2PLL_90M]); in mt2701_turn_on_a2sys_clock()
247 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]); in mt2701_turn_on_a2sys_clock()
254 ret = clk_set_rate(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV], in mt2701_turn_on_a2sys_clock()
264 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]); in mt2701_turn_on_a2sys_clock()
272 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); in mt2701_turn_on_a2sys_clock()
282 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); in mt2701_turn_on_a2sys_clock()
284 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]); in mt2701_turn_on_a2sys_clock()
286 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]); in mt2701_turn_on_a2sys_clock()
288 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]); in mt2701_turn_on_a2sys_clock()
297 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); in mt2701_turn_off_a2sys_clock()
298 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_44K_TIMING]); in mt2701_turn_off_a2sys_clock()
299 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_DIV]); in mt2701_turn_off_a2sys_clock()
300 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]); in mt2701_turn_off_a2sys_clock()
309 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); in mt2701_turn_on_afe_clock()
317 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_AUDINTBUS]); in mt2701_turn_on_afe_clock()
324 ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_AUDINTBUS], in mt2701_turn_on_afe_clock()
325 afe_priv->clocks[MT2701_AUD_SYSPLL1_D4]); in mt2701_turn_on_afe_clock()
334 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]); in mt2701_turn_on_afe_clock()
341 ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_ASM_H_SEL], in mt2701_turn_on_afe_clock()
342 afe_priv->clocks[MT2701_AUD_UNIVPLL2_D2]); in mt2701_turn_on_afe_clock()
351 ret = clk_prepare_enable(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]); in mt2701_turn_on_afe_clock()
358 ret = clk_set_parent(afe_priv->clocks[MT2701_AUD_ASM_M_SEL], in mt2701_turn_on_afe_clock()
359 afe_priv->clocks[MT2701_AUD_UNIVPLL2_D4]); in mt2701_turn_on_afe_clock()
381 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]); in mt2701_turn_on_afe_clock()
383 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]); in mt2701_turn_on_afe_clock()
385 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUDINTBUS]); in mt2701_turn_on_afe_clock()
387 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); in mt2701_turn_on_afe_clock()
396 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_INFRA_SYS_AUDIO]); in mt2701_turn_off_afe_clock()
398 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_AUDINTBUS]); in mt2701_turn_off_afe_clock()
399 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_H_SEL]); in mt2701_turn_off_afe_clock()
400 clk_disable_unprepare(afe_priv->clocks[MT2701_AUD_ASM_M_SEL]); in mt2701_turn_off_afe_clock()
427 ret = clk_prepare_enable(afe_priv->clocks[aud_src_clk_id]); in mt2701_mclk_configuration()
433 ret = clk_set_parent(afe_priv->clocks[aud_src_clk_id], in mt2701_mclk_configuration()
434 afe_priv->clocks[MT2701_AUD_AUD_MUX1_SEL]); in mt2701_mclk_configuration()
440 ret = clk_set_parent(afe_priv->clocks[aud_src_clk_id], in mt2701_mclk_configuration()
441 afe_priv->clocks[MT2701_AUD_AUD_MUX2_SEL]); in mt2701_mclk_configuration()
447 clk_disable_unprepare(afe_priv->clocks[aud_src_clk_id]); in mt2701_mclk_configuration()
450 ret = clk_prepare_enable(afe_priv->clocks[aud_src_div_id]); in mt2701_mclk_configuration()
455 ret = clk_set_rate(afe_priv->clocks[aud_src_div_id], mclk); in mt2701_mclk_configuration()
459 clk_disable_unprepare(afe_priv->clocks[aud_src_div_id]); in mt2701_mclk_configuration()