89 static inline void zx_tdm_writel(struct zx_tdm_info *tdm, u16 reg, u32 val)  in zx_tdm_writel()  argument
91 	writel_relaxed(val, tdm->regbase + reg);  in zx_tdm_writel()
96 	unsigned long val;  in zx_tdm_tx_en()  local
98 	val = zx_tdm_readl(tdm, REG_PROCESS_CTRL);  in zx_tdm_tx_en()
100 		val |= PROCESS_TX_EN | PROCESS_TDM_EN;  in zx_tdm_tx_en()
102 		val &= ~(PROCESS_TX_EN | PROCESS_TDM_EN);  in zx_tdm_tx_en()
103 	zx_tdm_writel(tdm, REG_PROCESS_CTRL, val);  in zx_tdm_tx_en()
108 	unsigned long val;  in zx_tdm_rx_en()  local
110 	val = zx_tdm_readl(tdm, REG_PROCESS_CTRL);  in zx_tdm_rx_en()
112 		val |= PROCESS_RX_EN | PROCESS_TDM_EN;  in zx_tdm_rx_en()
114 		val &= ~(PROCESS_RX_EN | PROCESS_TDM_EN);  in zx_tdm_rx_en()
115 	zx_tdm_writel(tdm, REG_PROCESS_CTRL, val);  in zx_tdm_rx_en()
120 	unsigned long val;  in zx_tdm_tx_dma_en()  local
122 	val = zx_tdm_readl(tdm, REG_TX_FIFO_CTRL);  in zx_tdm_tx_dma_en()
123 	val |= FIFO_CTRL_TX_RST | DEAGULT_FIFO_THRES;  in zx_tdm_tx_dma_en()
125 		val |= FIFO_CTRL_TX_DMA_EN;  in zx_tdm_tx_dma_en()
127 		val &= ~FIFO_CTRL_TX_DMA_EN;  in zx_tdm_tx_dma_en()
128 	zx_tdm_writel(tdm, REG_TX_FIFO_CTRL, val);  in zx_tdm_tx_dma_en()
133 	unsigned long val;  in zx_tdm_rx_dma_en()  local
135 	val = zx_tdm_readl(tdm, REG_RX_FIFO_CTRL);  in zx_tdm_rx_dma_en()
136 	val |= FIFO_CTRL_RX_RST | DEAGULT_FIFO_THRES;  in zx_tdm_rx_dma_en()
138 		val |= FIFO_CTRL_RX_DMA_EN;  in zx_tdm_rx_dma_en()
140 		val &= ~FIFO_CTRL_RX_DMA_EN;  in zx_tdm_rx_dma_en()
141 	zx_tdm_writel(tdm, REG_RX_FIFO_CTRL, val);  in zx_tdm_rx_dma_en()
167 	unsigned long val;  in zx_tdm_set_fmt()  local
169 	val = zx_tdm_readl(tdm, REG_TIMING_CTRL);  in zx_tdm_set_fmt()
170 	val &= ~(TIMING_SYNC_WIDTH_MASK | TIMING_MS_MASK);  in zx_tdm_set_fmt()
171 	val |= TIMING_DEFAULT_WIDTH << TIMING_WIDTH_SHIFT;  in zx_tdm_set_fmt()
176 		val |= TIMING_MASTER_MODE;  in zx_tdm_set_fmt()
180 		val &= ~TIMING_MASTER_MODE;  in zx_tdm_set_fmt()
188 	zx_tdm_writel(tdm, REG_TIMING_CTRL, val);  in zx_tdm_set_fmt()
203 	unsigned long val;  in zx_tdm_hw_params()  local
220 	val = zx_tdm_readl(tdm, REG_TIMING_CTRL);  in zx_tdm_hw_params()
221 	val |= TIMING_TS_WIDTH(ts_width) | TIMING_TS_NUM(1);  in zx_tdm_hw_params()
222 	zx_tdm_writel(tdm, REG_TIMING_CTRL, val);  in zx_tdm_hw_params()
237 	unsigned int val;  in zx_tdm_trigger()  local
243 			val = zx_tdm_readl(zx_tdm, REG_RX_FIFO_CTRL);  in zx_tdm_trigger()
244 			val |= FIFOCTRL_RX_FIFO_RST;  in zx_tdm_trigger()
245 			zx_tdm_writel(zx_tdm, REG_RX_FIFO_CTRL, val);  in zx_tdm_trigger()
249 			val = zx_tdm_readl(zx_tdm, REG_TX_FIFO_CTRL);  in zx_tdm_trigger()
250 			val |= FIFOCTRL_TX_FIFO_RST;  in zx_tdm_trigger()
251 			zx_tdm_writel(zx_tdm, REG_TX_FIFO_CTRL, val);  in zx_tdm_trigger()
326 	unsigned int val;  in zx_tdm_init_state()  local
330 	val = zx_tdm_readl(tdm, REG_TIMING_CTRL);  in zx_tdm_init_state()
331 	val |= TIMING_LSB_FIRST;  in zx_tdm_init_state()
332 	val &= ~TIMING_CLK_SEL_MASK;  in zx_tdm_init_state()
333 	val |= TIMING_CLK_SEL_DEF;  in zx_tdm_init_state()
334 	zx_tdm_writel(tdm, REG_TIMING_CTRL, val);  in zx_tdm_init_state()
344 	val = zx_tdm_readl(tdm, REG_RX_FIFO_CTRL);  in zx_tdm_init_state()
345 	val &= ~(RXTH_MASK | RX_FIFO_RST_MASK);  in zx_tdm_init_state()
346 	val |= FIFOCTRL_THRESHOLD(8);  in zx_tdm_init_state()
347 	zx_tdm_writel(tdm, REG_RX_FIFO_CTRL, val);  in zx_tdm_init_state()
349 	val = zx_tdm_readl(tdm, REG_TX_FIFO_CTRL);  in zx_tdm_init_state()
350 	val &= ~(TXTH_MASK | TX_FIFO_RST_MASK);  in zx_tdm_init_state()
351 	val |= FIFOCTRL_THRESHOLD(8);  in zx_tdm_init_state()
352 	zx_tdm_writel(tdm, REG_TX_FIFO_CTRL, val);  in zx_tdm_init_state()