1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #ifndef __AMDGPU_H__
29 #define __AMDGPU_H__
30
31 #include <linux/atomic.h>
32 #include <linux/wait.h>
33 #include <linux/list.h>
34 #include <linux/kref.h>
35 #include <linux/rbtree.h>
36 #include <linux/hashtable.h>
37 #include <linux/dma-fence.h>
38
39 #include <drm/ttm/ttm_bo_api.h>
40 #include <drm/ttm/ttm_bo_driver.h>
41 #include <drm/ttm/ttm_placement.h>
42 #include <drm/ttm/ttm_module.h>
43 #include <drm/ttm/ttm_execbuf_util.h>
44
45 #include <drm/drmP.h>
46 #include <drm/drm_gem.h>
47 #include <drm/amdgpu_drm.h>
48
49 #include <kgd_kfd_interface.h>
50
51 #include "amd_shared.h"
52 #include "amdgpu_mode.h"
53 #include "amdgpu_ih.h"
54 #include "amdgpu_irq.h"
55 #include "amdgpu_ucode.h"
56 #include "amdgpu_ttm.h"
57 #include "amdgpu_psp.h"
58 #include "amdgpu_gds.h"
59 #include "amdgpu_sync.h"
60 #include "amdgpu_ring.h"
61 #include "amdgpu_vm.h"
62 #include "amd_powerplay.h"
63 #include "amdgpu_dpm.h"
64 #include "amdgpu_acp.h"
65 #include "amdgpu_uvd.h"
66 #include "amdgpu_vce.h"
67 #include "amdgpu_vcn.h"
68
69 #include "gpu_scheduler.h"
70 #include "amdgpu_virt.h"
71 #include "amdgpu_gart.h"
72
73 /*
74 * Modules parameters.
75 */
76 extern int amdgpu_modeset;
77 extern int amdgpu_vram_limit;
78 extern int amdgpu_vis_vram_limit;
79 extern int amdgpu_gart_size;
80 extern int amdgpu_gtt_size;
81 extern int amdgpu_moverate;
82 extern int amdgpu_benchmarking;
83 extern int amdgpu_testing;
84 extern int amdgpu_audio;
85 extern int amdgpu_disp_priority;
86 extern int amdgpu_hw_i2c;
87 extern int amdgpu_pcie_gen2;
88 extern int amdgpu_msi;
89 extern int amdgpu_lockup_timeout;
90 extern int amdgpu_dpm;
91 extern int amdgpu_fw_load_type;
92 extern int amdgpu_aspm;
93 extern int amdgpu_runtime_pm;
94 extern unsigned amdgpu_ip_block_mask;
95 extern int amdgpu_bapm;
96 extern int amdgpu_deep_color;
97 extern int amdgpu_vm_size;
98 extern int amdgpu_vm_block_size;
99 extern int amdgpu_vm_fragment_size;
100 extern int amdgpu_vm_fault_stop;
101 extern int amdgpu_vm_debug;
102 extern int amdgpu_vm_update_mode;
103 extern int amdgpu_sched_jobs;
104 extern int amdgpu_sched_hw_submission;
105 extern int amdgpu_no_evict;
106 extern int amdgpu_direct_gma_size;
107 extern unsigned amdgpu_pcie_gen_cap;
108 extern unsigned amdgpu_pcie_lane_cap;
109 extern unsigned amdgpu_cg_mask;
110 extern unsigned amdgpu_pg_mask;
111 extern unsigned amdgpu_sdma_phase_quantum;
112 extern char *amdgpu_disable_cu;
113 extern char *amdgpu_virtual_display;
114 extern unsigned amdgpu_pp_feature_mask;
115 extern int amdgpu_vram_page_split;
116 extern int amdgpu_ngg;
117 extern int amdgpu_prim_buf_per_se;
118 extern int amdgpu_pos_buf_per_se;
119 extern int amdgpu_cntl_sb_buf_per_se;
120 extern int amdgpu_param_buf_per_se;
121 extern int amdgpu_job_hang_limit;
122 extern int amdgpu_lbpw;
123
124 #ifdef CONFIG_DRM_AMDGPU_SI
125 extern int amdgpu_si_support;
126 #endif
127 #ifdef CONFIG_DRM_AMDGPU_CIK
128 extern int amdgpu_cik_support;
129 #endif
130
131 #define AMDGPU_DEFAULT_GTT_SIZE_MB 3072ULL /* 3GB by default */
132 #define AMDGPU_WAIT_IDLE_TIMEOUT_IN_MS 3000
133 #define AMDGPU_MAX_USEC_TIMEOUT 100000 /* 100 ms */
134 #define AMDGPU_FENCE_JIFFIES_TIMEOUT (HZ / 2)
135 /* AMDGPU_IB_POOL_SIZE must be a power of 2 */
136 #define AMDGPU_IB_POOL_SIZE 16
137 #define AMDGPU_DEBUGFS_MAX_COMPONENTS 32
138 #define AMDGPUFB_CONN_LIMIT 4
139 #define AMDGPU_BIOS_NUM_SCRATCH 16
140
141 /* max number of IP instances */
142 #define AMDGPU_MAX_SDMA_INSTANCES 2
143
144 /* hard reset data */
145 #define AMDGPU_ASIC_RESET_DATA 0x39d5e86b
146
147 /* reset flags */
148 #define AMDGPU_RESET_GFX (1 << 0)
149 #define AMDGPU_RESET_COMPUTE (1 << 1)
150 #define AMDGPU_RESET_DMA (1 << 2)
151 #define AMDGPU_RESET_CP (1 << 3)
152 #define AMDGPU_RESET_GRBM (1 << 4)
153 #define AMDGPU_RESET_DMA1 (1 << 5)
154 #define AMDGPU_RESET_RLC (1 << 6)
155 #define AMDGPU_RESET_SEM (1 << 7)
156 #define AMDGPU_RESET_IH (1 << 8)
157 #define AMDGPU_RESET_VMC (1 << 9)
158 #define AMDGPU_RESET_MC (1 << 10)
159 #define AMDGPU_RESET_DISPLAY (1 << 11)
160 #define AMDGPU_RESET_UVD (1 << 12)
161 #define AMDGPU_RESET_VCE (1 << 13)
162 #define AMDGPU_RESET_VCE1 (1 << 14)
163
164 /* GFX current status */
165 #define AMDGPU_GFX_NORMAL_MODE 0x00000000L
166 #define AMDGPU_GFX_SAFE_MODE 0x00000001L
167 #define AMDGPU_GFX_PG_DISABLED_MODE 0x00000002L
168 #define AMDGPU_GFX_CG_DISABLED_MODE 0x00000004L
169 #define AMDGPU_GFX_LBPW_DISABLED_MODE 0x00000008L
170
171 /* max cursor sizes (in pixels) */
172 #define CIK_CURSOR_WIDTH 128
173 #define CIK_CURSOR_HEIGHT 128
174
175 struct amdgpu_device;
176 struct amdgpu_ib;
177 struct amdgpu_cs_parser;
178 struct amdgpu_job;
179 struct amdgpu_irq_src;
180 struct amdgpu_fpriv;
181
182 enum amdgpu_cp_irq {
183 AMDGPU_CP_IRQ_GFX_EOP = 0,
184 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP,
185 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP,
186 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP,
187 AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP,
188 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP,
189 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP,
190 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP,
191 AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP,
192
193 AMDGPU_CP_IRQ_LAST
194 };
195
196 enum amdgpu_sdma_irq {
197 AMDGPU_SDMA_IRQ_TRAP0 = 0,
198 AMDGPU_SDMA_IRQ_TRAP1,
199
200 AMDGPU_SDMA_IRQ_LAST
201 };
202
203 enum amdgpu_thermal_irq {
204 AMDGPU_THERMAL_IRQ_LOW_TO_HIGH = 0,
205 AMDGPU_THERMAL_IRQ_HIGH_TO_LOW,
206
207 AMDGPU_THERMAL_IRQ_LAST
208 };
209
210 enum amdgpu_kiq_irq {
211 AMDGPU_CP_KIQ_IRQ_DRIVER0 = 0,
212 AMDGPU_CP_KIQ_IRQ_LAST
213 };
214
215 int amdgpu_set_clockgating_state(struct amdgpu_device *adev,
216 enum amd_ip_block_type block_type,
217 enum amd_clockgating_state state);
218 int amdgpu_set_powergating_state(struct amdgpu_device *adev,
219 enum amd_ip_block_type block_type,
220 enum amd_powergating_state state);
221 void amdgpu_get_clockgating_state(struct amdgpu_device *adev, u32 *flags);
222 int amdgpu_wait_for_idle(struct amdgpu_device *adev,
223 enum amd_ip_block_type block_type);
224 bool amdgpu_is_idle(struct amdgpu_device *adev,
225 enum amd_ip_block_type block_type);
226
227 #define AMDGPU_MAX_IP_NUM 16
228
229 struct amdgpu_ip_block_status {
230 bool valid;
231 bool sw;
232 bool hw;
233 bool late_initialized;
234 bool hang;
235 };
236
237 struct amdgpu_ip_block_version {
238 const enum amd_ip_block_type type;
239 const u32 major;
240 const u32 minor;
241 const u32 rev;
242 const struct amd_ip_funcs *funcs;
243 };
244
245 struct amdgpu_ip_block {
246 struct amdgpu_ip_block_status status;
247 const struct amdgpu_ip_block_version *version;
248 };
249
250 int amdgpu_ip_block_version_cmp(struct amdgpu_device *adev,
251 enum amd_ip_block_type type,
252 u32 major, u32 minor);
253
254 struct amdgpu_ip_block * amdgpu_get_ip_block(struct amdgpu_device *adev,
255 enum amd_ip_block_type type);
256
257 int amdgpu_ip_block_add(struct amdgpu_device *adev,
258 const struct amdgpu_ip_block_version *ip_block_version);
259
260 /* provided by hw blocks that can move/clear data. e.g., gfx or sdma */
261 struct amdgpu_buffer_funcs {
262 /* maximum bytes in a single operation */
263 uint32_t copy_max_bytes;
264
265 /* number of dw to reserve per operation */
266 unsigned copy_num_dw;
267
268 /* used for buffer migration */
269 void (*emit_copy_buffer)(struct amdgpu_ib *ib,
270 /* src addr in bytes */
271 uint64_t src_offset,
272 /* dst addr in bytes */
273 uint64_t dst_offset,
274 /* number of byte to transfer */
275 uint32_t byte_count);
276
277 /* maximum bytes in a single operation */
278 uint32_t fill_max_bytes;
279
280 /* number of dw to reserve per operation */
281 unsigned fill_num_dw;
282
283 /* used for buffer clearing */
284 void (*emit_fill_buffer)(struct amdgpu_ib *ib,
285 /* value to write to memory */
286 uint32_t src_data,
287 /* dst addr in bytes */
288 uint64_t dst_offset,
289 /* number of byte to fill */
290 uint32_t byte_count);
291 };
292
293 /* provided by hw blocks that can write ptes, e.g., sdma */
294 struct amdgpu_vm_pte_funcs {
295 /* copy pte entries from GART */
296 void (*copy_pte)(struct amdgpu_ib *ib,
297 uint64_t pe, uint64_t src,
298 unsigned count);
299 /* write pte one entry at a time with addr mapping */
300 void (*write_pte)(struct amdgpu_ib *ib, uint64_t pe,
301 uint64_t value, unsigned count,
302 uint32_t incr);
303 /* for linear pte/pde updates without addr mapping */
304 void (*set_pte_pde)(struct amdgpu_ib *ib,
305 uint64_t pe,
306 uint64_t addr, unsigned count,
307 uint32_t incr, uint64_t flags);
308 };
309
310 /* provided by the gmc block */
311 struct amdgpu_gart_funcs {
312 /* flush the vm tlb via mmio */
313 void (*flush_gpu_tlb)(struct amdgpu_device *adev,
314 uint32_t vmid);
315 /* write pte/pde updates using the cpu */
316 int (*set_pte_pde)(struct amdgpu_device *adev,
317 void *cpu_pt_addr, /* cpu addr of page table */
318 uint32_t gpu_page_idx, /* pte/pde to update */
319 uint64_t addr, /* addr to write into pte/pde */
320 uint64_t flags); /* access flags */
321 /* enable/disable PRT support */
322 void (*set_prt)(struct amdgpu_device *adev, bool enable);
323 /* set pte flags based per asic */
324 uint64_t (*get_vm_pte_flags)(struct amdgpu_device *adev,
325 uint32_t flags);
326 /* get the pde for a given mc addr */
327 u64 (*get_vm_pde)(struct amdgpu_device *adev, u64 addr);
328 uint32_t (*get_invalidate_req)(unsigned int vm_id);
329 };
330
331 /* provided by the ih block */
332 struct amdgpu_ih_funcs {
333 /* ring read/write ptr handling, called from interrupt context */
334 u32 (*get_wptr)(struct amdgpu_device *adev);
335 void (*decode_iv)(struct amdgpu_device *adev,
336 struct amdgpu_iv_entry *entry);
337 void (*set_rptr)(struct amdgpu_device *adev);
338 };
339
340 /*
341 * BIOS.
342 */
343 bool amdgpu_get_bios(struct amdgpu_device *adev);
344 bool amdgpu_read_bios(struct amdgpu_device *adev);
345
346 /*
347 * Dummy page
348 */
349 struct amdgpu_dummy_page {
350 struct page *page;
351 dma_addr_t addr;
352 };
353 int amdgpu_dummy_page_init(struct amdgpu_device *adev);
354 void amdgpu_dummy_page_fini(struct amdgpu_device *adev);
355
356
357 /*
358 * Clocks
359 */
360
361 #define AMDGPU_MAX_PPLL 3
362
363 struct amdgpu_clock {
364 struct amdgpu_pll ppll[AMDGPU_MAX_PPLL];
365 struct amdgpu_pll spll;
366 struct amdgpu_pll mpll;
367 /* 10 Khz units */
368 uint32_t default_mclk;
369 uint32_t default_sclk;
370 uint32_t default_dispclk;
371 uint32_t current_dispclk;
372 uint32_t dp_extclk;
373 uint32_t max_pixel_clock;
374 };
375
376 /*
377 * GEM.
378 */
379
380 #define AMDGPU_GEM_DOMAIN_MAX 0x3
381 #define gem_to_amdgpu_bo(gobj) container_of((gobj), struct amdgpu_bo, gem_base)
382
383 void amdgpu_gem_object_free(struct drm_gem_object *obj);
384 int amdgpu_gem_object_open(struct drm_gem_object *obj,
385 struct drm_file *file_priv);
386 void amdgpu_gem_object_close(struct drm_gem_object *obj,
387 struct drm_file *file_priv);
388 unsigned long amdgpu_gem_timeout(uint64_t timeout_ns);
389 struct sg_table *amdgpu_gem_prime_get_sg_table(struct drm_gem_object *obj);
390 struct drm_gem_object *
391 amdgpu_gem_prime_import_sg_table(struct drm_device *dev,
392 struct dma_buf_attachment *attach,
393 struct sg_table *sg);
394 struct dma_buf *amdgpu_gem_prime_export(struct drm_device *dev,
395 struct drm_gem_object *gobj,
396 int flags);
397 int amdgpu_gem_prime_pin(struct drm_gem_object *obj);
398 void amdgpu_gem_prime_unpin(struct drm_gem_object *obj);
399 struct reservation_object *amdgpu_gem_prime_res_obj(struct drm_gem_object *);
400 void *amdgpu_gem_prime_vmap(struct drm_gem_object *obj);
401 void amdgpu_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
402 int amdgpu_gem_debugfs_init(struct amdgpu_device *adev);
403
404 /* sub-allocation manager, it has to be protected by another lock.
405 * By conception this is an helper for other part of the driver
406 * like the indirect buffer or semaphore, which both have their
407 * locking.
408 *
409 * Principe is simple, we keep a list of sub allocation in offset
410 * order (first entry has offset == 0, last entry has the highest
411 * offset).
412 *
413 * When allocating new object we first check if there is room at
414 * the end total_size - (last_object_offset + last_object_size) >=
415 * alloc_size. If so we allocate new object there.
416 *
417 * When there is not enough room at the end, we start waiting for
418 * each sub object until we reach object_offset+object_size >=
419 * alloc_size, this object then become the sub object we return.
420 *
421 * Alignment can't be bigger than page size.
422 *
423 * Hole are not considered for allocation to keep things simple.
424 * Assumption is that there won't be hole (all object on same
425 * alignment).
426 */
427
428 #define AMDGPU_SA_NUM_FENCE_LISTS 32
429
430 struct amdgpu_sa_manager {
431 wait_queue_head_t wq;
432 struct amdgpu_bo *bo;
433 struct list_head *hole;
434 struct list_head flist[AMDGPU_SA_NUM_FENCE_LISTS];
435 struct list_head olist;
436 unsigned size;
437 uint64_t gpu_addr;
438 void *cpu_ptr;
439 uint32_t domain;
440 uint32_t align;
441 };
442
443 /* sub-allocation buffer */
444 struct amdgpu_sa_bo {
445 struct list_head olist;
446 struct list_head flist;
447 struct amdgpu_sa_manager *manager;
448 unsigned soffset;
449 unsigned eoffset;
450 struct dma_fence *fence;
451 };
452
453 /*
454 * GEM objects.
455 */
456 void amdgpu_gem_force_release(struct amdgpu_device *adev);
457 int amdgpu_gem_object_create(struct amdgpu_device *adev, unsigned long size,
458 int alignment, u32 initial_domain,
459 u64 flags, bool kernel,
460 struct drm_gem_object **obj);
461
462 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
463 struct drm_device *dev,
464 struct drm_mode_create_dumb *args);
465 int amdgpu_mode_dumb_mmap(struct drm_file *filp,
466 struct drm_device *dev,
467 uint32_t handle, uint64_t *offset_p);
468 int amdgpu_fence_slab_init(void);
469 void amdgpu_fence_slab_fini(void);
470
471 /*
472 * VMHUB structures, functions & helpers
473 */
474 struct amdgpu_vmhub {
475 uint32_t ctx0_ptb_addr_lo32;
476 uint32_t ctx0_ptb_addr_hi32;
477 uint32_t vm_inv_eng0_req;
478 uint32_t vm_inv_eng0_ack;
479 uint32_t vm_context0_cntl;
480 uint32_t vm_l2_pro_fault_status;
481 uint32_t vm_l2_pro_fault_cntl;
482 };
483
484 /*
485 * GPU MC structures, functions & helpers
486 */
487 struct amdgpu_mc {
488 resource_size_t aper_size;
489 resource_size_t aper_base;
490 resource_size_t agp_base;
491 /* for some chips with <= 32MB we need to lie
492 * about vram size near mc fb location */
493 u64 mc_vram_size;
494 u64 visible_vram_size;
495 u64 gart_size;
496 u64 gart_start;
497 u64 gart_end;
498 u64 vram_start;
499 u64 vram_end;
500 unsigned vram_width;
501 u64 real_vram_size;
502 int vram_mtrr;
503 u64 mc_mask;
504 const struct firmware *fw; /* MC firmware */
505 uint32_t fw_version;
506 struct amdgpu_irq_src vm_fault;
507 uint32_t vram_type;
508 uint32_t srbm_soft_reset;
509 bool prt_warning;
510 uint64_t stolen_size;
511 /* apertures */
512 u64 shared_aperture_start;
513 u64 shared_aperture_end;
514 u64 private_aperture_start;
515 u64 private_aperture_end;
516 /* protects concurrent invalidation */
517 spinlock_t invalidate_lock;
518 };
519
520 /*
521 * GPU doorbell structures, functions & helpers
522 */
523 typedef enum _AMDGPU_DOORBELL_ASSIGNMENT
524 {
525 AMDGPU_DOORBELL_KIQ = 0x000,
526 AMDGPU_DOORBELL_HIQ = 0x001,
527 AMDGPU_DOORBELL_DIQ = 0x002,
528 AMDGPU_DOORBELL_MEC_RING0 = 0x010,
529 AMDGPU_DOORBELL_MEC_RING1 = 0x011,
530 AMDGPU_DOORBELL_MEC_RING2 = 0x012,
531 AMDGPU_DOORBELL_MEC_RING3 = 0x013,
532 AMDGPU_DOORBELL_MEC_RING4 = 0x014,
533 AMDGPU_DOORBELL_MEC_RING5 = 0x015,
534 AMDGPU_DOORBELL_MEC_RING6 = 0x016,
535 AMDGPU_DOORBELL_MEC_RING7 = 0x017,
536 AMDGPU_DOORBELL_GFX_RING0 = 0x020,
537 AMDGPU_DOORBELL_sDMA_ENGINE0 = 0x1E0,
538 AMDGPU_DOORBELL_sDMA_ENGINE1 = 0x1E1,
539 AMDGPU_DOORBELL_IH = 0x1E8,
540 AMDGPU_DOORBELL_MAX_ASSIGNMENT = 0x3FF,
541 AMDGPU_DOORBELL_INVALID = 0xFFFF
542 } AMDGPU_DOORBELL_ASSIGNMENT;
543
544 struct amdgpu_doorbell {
545 /* doorbell mmio */
546 resource_size_t base;
547 resource_size_t size;
548 u32 __iomem *ptr;
549 u32 num_doorbells; /* Number of doorbells actually reserved for amdgpu. */
550 };
551
552 /*
553 * 64bit doorbell, offset are in QWORD, occupy 2KB doorbell space
554 */
555 typedef enum _AMDGPU_DOORBELL64_ASSIGNMENT
556 {
557 /*
558 * All compute related doorbells: kiq, hiq, diq, traditional compute queue, user queue, should locate in
559 * a continues range so that programming CP_MEC_DOORBELL_RANGE_LOWER/UPPER can cover this range.
560 * Compute related doorbells are allocated from 0x00 to 0x8a
561 */
562
563
564 /* kernel scheduling */
565 AMDGPU_DOORBELL64_KIQ = 0x00,
566
567 /* HSA interface queue and debug queue */
568 AMDGPU_DOORBELL64_HIQ = 0x01,
569 AMDGPU_DOORBELL64_DIQ = 0x02,
570
571 /* Compute engines */
572 AMDGPU_DOORBELL64_MEC_RING0 = 0x03,
573 AMDGPU_DOORBELL64_MEC_RING1 = 0x04,
574 AMDGPU_DOORBELL64_MEC_RING2 = 0x05,
575 AMDGPU_DOORBELL64_MEC_RING3 = 0x06,
576 AMDGPU_DOORBELL64_MEC_RING4 = 0x07,
577 AMDGPU_DOORBELL64_MEC_RING5 = 0x08,
578 AMDGPU_DOORBELL64_MEC_RING6 = 0x09,
579 AMDGPU_DOORBELL64_MEC_RING7 = 0x0a,
580
581 /* User queue doorbell range (128 doorbells) */
582 AMDGPU_DOORBELL64_USERQUEUE_START = 0x0b,
583 AMDGPU_DOORBELL64_USERQUEUE_END = 0x8a,
584
585 /* Graphics engine */
586 AMDGPU_DOORBELL64_GFX_RING0 = 0x8b,
587
588 /*
589 * Other graphics doorbells can be allocated here: from 0x8c to 0xef
590 * Graphics voltage island aperture 1
591 * default non-graphics QWORD index is 0xF0 - 0xFF inclusive
592 */
593
594 /* sDMA engines */
595 AMDGPU_DOORBELL64_sDMA_ENGINE0 = 0xF0,
596 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE0 = 0xF1,
597 AMDGPU_DOORBELL64_sDMA_ENGINE1 = 0xF2,
598 AMDGPU_DOORBELL64_sDMA_HI_PRI_ENGINE1 = 0xF3,
599
600 /* Interrupt handler */
601 AMDGPU_DOORBELL64_IH = 0xF4, /* For legacy interrupt ring buffer */
602 AMDGPU_DOORBELL64_IH_RING1 = 0xF5, /* For page migration request log */
603 AMDGPU_DOORBELL64_IH_RING2 = 0xF6, /* For page migration translation/invalidation log */
604
605 /* VCN engine use 32 bits doorbell */
606 AMDGPU_DOORBELL64_VCN0_1 = 0xF8, /* lower 32 bits for VNC0 and upper 32 bits for VNC1 */
607 AMDGPU_DOORBELL64_VCN2_3 = 0xF9,
608 AMDGPU_DOORBELL64_VCN4_5 = 0xFA,
609 AMDGPU_DOORBELL64_VCN6_7 = 0xFB,
610
611 /* overlap the doorbell assignment with VCN as they are mutually exclusive
612 * VCE engine's doorbell is 32 bit and two VCE ring share one QWORD
613 */
614 AMDGPU_DOORBELL64_UVD_RING0_1 = 0xF8,
615 AMDGPU_DOORBELL64_UVD_RING2_3 = 0xF9,
616 AMDGPU_DOORBELL64_UVD_RING4_5 = 0xFA,
617 AMDGPU_DOORBELL64_UVD_RING6_7 = 0xFB,
618
619 AMDGPU_DOORBELL64_VCE_RING0_1 = 0xFC,
620 AMDGPU_DOORBELL64_VCE_RING2_3 = 0xFD,
621 AMDGPU_DOORBELL64_VCE_RING4_5 = 0xFE,
622 AMDGPU_DOORBELL64_VCE_RING6_7 = 0xFF,
623
624 AMDGPU_DOORBELL64_MAX_ASSIGNMENT = 0xFF,
625 AMDGPU_DOORBELL64_INVALID = 0xFFFF
626 } AMDGPU_DOORBELL64_ASSIGNMENT;
627
628
629 void amdgpu_doorbell_get_kfd_info(struct amdgpu_device *adev,
630 phys_addr_t *aperture_base,
631 size_t *aperture_size,
632 size_t *start_offset);
633
634 /*
635 * IRQS.
636 */
637
638 struct amdgpu_flip_work {
639 struct delayed_work flip_work;
640 struct work_struct unpin_work;
641 struct amdgpu_device *adev;
642 int crtc_id;
643 u32 target_vblank;
644 uint64_t base;
645 struct drm_pending_vblank_event *event;
646 struct amdgpu_bo *old_abo;
647 struct dma_fence *excl;
648 unsigned shared_count;
649 struct dma_fence **shared;
650 struct dma_fence_cb cb;
651 bool async;
652 };
653
654
655 /*
656 * CP & rings.
657 */
658
659 struct amdgpu_ib {
660 struct amdgpu_sa_bo *sa_bo;
661 uint32_t length_dw;
662 uint64_t gpu_addr;
663 uint32_t *ptr;
664 uint32_t flags;
665 };
666
667 extern const struct amd_sched_backend_ops amdgpu_sched_ops;
668
669 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
670 struct amdgpu_job **job, struct amdgpu_vm *vm);
671 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
672 struct amdgpu_job **job);
673
674 void amdgpu_job_free_resources(struct amdgpu_job *job);
675 void amdgpu_job_free(struct amdgpu_job *job);
676 int amdgpu_job_submit(struct amdgpu_job *job, struct amdgpu_ring *ring,
677 struct amd_sched_entity *entity, void *owner,
678 struct dma_fence **f);
679
680 /*
681 * Queue manager
682 */
683 struct amdgpu_queue_mapper {
684 int hw_ip;
685 struct mutex lock;
686 /* protected by lock */
687 struct amdgpu_ring *queue_map[AMDGPU_MAX_RINGS];
688 };
689
690 struct amdgpu_queue_mgr {
691 struct amdgpu_queue_mapper mapper[AMDGPU_MAX_IP_NUM];
692 };
693
694 int amdgpu_queue_mgr_init(struct amdgpu_device *adev,
695 struct amdgpu_queue_mgr *mgr);
696 int amdgpu_queue_mgr_fini(struct amdgpu_device *adev,
697 struct amdgpu_queue_mgr *mgr);
698 int amdgpu_queue_mgr_map(struct amdgpu_device *adev,
699 struct amdgpu_queue_mgr *mgr,
700 u32 hw_ip, u32 instance, u32 ring,
701 struct amdgpu_ring **out_ring);
702
703 /*
704 * context related structures
705 */
706
707 struct amdgpu_ctx_ring {
708 uint64_t sequence;
709 struct dma_fence **fences;
710 struct amd_sched_entity entity;
711 };
712
713 struct amdgpu_ctx {
714 struct kref refcount;
715 struct amdgpu_device *adev;
716 struct amdgpu_queue_mgr queue_mgr;
717 unsigned reset_counter;
718 spinlock_t ring_lock;
719 struct dma_fence **fences;
720 struct amdgpu_ctx_ring rings[AMDGPU_MAX_RINGS];
721 bool preamble_presented;
722 };
723
724 struct amdgpu_ctx_mgr {
725 struct amdgpu_device *adev;
726 struct mutex lock;
727 /* protected by lock */
728 struct idr ctx_handles;
729 };
730
731 struct amdgpu_ctx *amdgpu_ctx_get(struct amdgpu_fpriv *fpriv, uint32_t id);
732 int amdgpu_ctx_put(struct amdgpu_ctx *ctx);
733
734 uint64_t amdgpu_ctx_add_fence(struct amdgpu_ctx *ctx, struct amdgpu_ring *ring,
735 struct dma_fence *fence);
736 struct dma_fence *amdgpu_ctx_get_fence(struct amdgpu_ctx *ctx,
737 struct amdgpu_ring *ring, uint64_t seq);
738
739 int amdgpu_ctx_ioctl(struct drm_device *dev, void *data,
740 struct drm_file *filp);
741
742 void amdgpu_ctx_mgr_init(struct amdgpu_ctx_mgr *mgr);
743 void amdgpu_ctx_mgr_fini(struct amdgpu_ctx_mgr *mgr);
744
745 /*
746 * file private structure
747 */
748
749 struct amdgpu_fpriv {
750 struct amdgpu_vm vm;
751 struct amdgpu_bo_va *prt_va;
752 struct amdgpu_bo_va *csa_va;
753 struct mutex bo_list_lock;
754 struct idr bo_list_handles;
755 struct amdgpu_ctx_mgr ctx_mgr;
756 u32 vram_lost_counter;
757 };
758
759 /*
760 * residency list
761 */
762 struct amdgpu_bo_list_entry {
763 struct amdgpu_bo *robj;
764 struct ttm_validate_buffer tv;
765 struct amdgpu_bo_va *bo_va;
766 uint32_t priority;
767 struct page **user_pages;
768 int user_invalidated;
769 };
770
771 struct amdgpu_bo_list {
772 struct mutex lock;
773 struct rcu_head rhead;
774 struct kref refcount;
775 struct amdgpu_bo *gds_obj;
776 struct amdgpu_bo *gws_obj;
777 struct amdgpu_bo *oa_obj;
778 unsigned first_userptr;
779 unsigned num_entries;
780 struct amdgpu_bo_list_entry *array;
781 };
782
783 struct amdgpu_bo_list *
784 amdgpu_bo_list_get(struct amdgpu_fpriv *fpriv, int id);
785 void amdgpu_bo_list_get_list(struct amdgpu_bo_list *list,
786 struct list_head *validated);
787 void amdgpu_bo_list_put(struct amdgpu_bo_list *list);
788 void amdgpu_bo_list_free(struct amdgpu_bo_list *list);
789
790 /*
791 * GFX stuff
792 */
793 #include "clearstate_defs.h"
794
795 struct amdgpu_rlc_funcs {
796 void (*enter_safe_mode)(struct amdgpu_device *adev);
797 void (*exit_safe_mode)(struct amdgpu_device *adev);
798 };
799
800 struct amdgpu_rlc {
801 /* for power gating */
802 struct amdgpu_bo *save_restore_obj;
803 uint64_t save_restore_gpu_addr;
804 volatile uint32_t *sr_ptr;
805 const u32 *reg_list;
806 u32 reg_list_size;
807 /* for clear state */
808 struct amdgpu_bo *clear_state_obj;
809 uint64_t clear_state_gpu_addr;
810 volatile uint32_t *cs_ptr;
811 const struct cs_section_def *cs_data;
812 u32 clear_state_size;
813 /* for cp tables */
814 struct amdgpu_bo *cp_table_obj;
815 uint64_t cp_table_gpu_addr;
816 volatile uint32_t *cp_table_ptr;
817 u32 cp_table_size;
818
819 /* safe mode for updating CG/PG state */
820 bool in_safe_mode;
821 const struct amdgpu_rlc_funcs *funcs;
822
823 /* for firmware data */
824 u32 save_and_restore_offset;
825 u32 clear_state_descriptor_offset;
826 u32 avail_scratch_ram_locations;
827 u32 reg_restore_list_size;
828 u32 reg_list_format_start;
829 u32 reg_list_format_separate_start;
830 u32 starting_offsets_start;
831 u32 reg_list_format_size_bytes;
832 u32 reg_list_size_bytes;
833
834 u32 *register_list_format;
835 u32 *register_restore;
836 };
837
838 #define AMDGPU_MAX_COMPUTE_QUEUES KGD_MAX_QUEUES
839
840 struct amdgpu_mec {
841 struct amdgpu_bo *hpd_eop_obj;
842 u64 hpd_eop_gpu_addr;
843 struct amdgpu_bo *mec_fw_obj;
844 u64 mec_fw_gpu_addr;
845 u32 num_mec;
846 u32 num_pipe_per_mec;
847 u32 num_queue_per_pipe;
848 void *mqd_backup[AMDGPU_MAX_COMPUTE_RINGS + 1];
849
850 /* These are the resources for which amdgpu takes ownership */
851 DECLARE_BITMAP(queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
852 };
853
854 struct amdgpu_kiq {
855 u64 eop_gpu_addr;
856 struct amdgpu_bo *eop_obj;
857 struct mutex ring_mutex;
858 struct amdgpu_ring ring;
859 struct amdgpu_irq_src irq;
860 };
861
862 /*
863 * GPU scratch registers structures, functions & helpers
864 */
865 struct amdgpu_scratch {
866 unsigned num_reg;
867 uint32_t reg_base;
868 uint32_t free_mask;
869 };
870
871 /*
872 * GFX configurations
873 */
874 #define AMDGPU_GFX_MAX_SE 4
875 #define AMDGPU_GFX_MAX_SH_PER_SE 2
876
877 struct amdgpu_rb_config {
878 uint32_t rb_backend_disable;
879 uint32_t user_rb_backend_disable;
880 uint32_t raster_config;
881 uint32_t raster_config_1;
882 };
883
884 struct gb_addr_config {
885 uint16_t pipe_interleave_size;
886 uint8_t num_pipes;
887 uint8_t max_compress_frags;
888 uint8_t num_banks;
889 uint8_t num_se;
890 uint8_t num_rb_per_se;
891 };
892
893 struct amdgpu_gfx_config {
894 unsigned max_shader_engines;
895 unsigned max_tile_pipes;
896 unsigned max_cu_per_sh;
897 unsigned max_sh_per_se;
898 unsigned max_backends_per_se;
899 unsigned max_texture_channel_caches;
900 unsigned max_gprs;
901 unsigned max_gs_threads;
902 unsigned max_hw_contexts;
903 unsigned sc_prim_fifo_size_frontend;
904 unsigned sc_prim_fifo_size_backend;
905 unsigned sc_hiz_tile_fifo_size;
906 unsigned sc_earlyz_tile_fifo_size;
907
908 unsigned num_tile_pipes;
909 unsigned backend_enable_mask;
910 unsigned mem_max_burst_length_bytes;
911 unsigned mem_row_size_in_kb;
912 unsigned shader_engine_tile_size;
913 unsigned num_gpus;
914 unsigned multi_gpu_tile_size;
915 unsigned mc_arb_ramcfg;
916 unsigned gb_addr_config;
917 unsigned num_rbs;
918 unsigned gs_vgt_table_depth;
919 unsigned gs_prim_buffer_depth;
920
921 uint32_t tile_mode_array[32];
922 uint32_t macrotile_mode_array[16];
923
924 struct gb_addr_config gb_addr_config_fields;
925 struct amdgpu_rb_config rb_config[AMDGPU_GFX_MAX_SE][AMDGPU_GFX_MAX_SH_PER_SE];
926
927 /* gfx configure feature */
928 uint32_t double_offchip_lds_buf;
929 };
930
931 struct amdgpu_cu_info {
932 uint32_t max_waves_per_simd;
933 uint32_t wave_front_size;
934 uint32_t max_scratch_slots_per_cu;
935 uint32_t lds_size;
936
937 /* total active CU number */
938 uint32_t number;
939 uint32_t ao_cu_mask;
940 uint32_t ao_cu_bitmap[4][4];
941 uint32_t bitmap[4][4];
942 };
943
944 struct amdgpu_gfx_funcs {
945 /* get the gpu clock counter */
946 uint64_t (*get_gpu_clock_counter)(struct amdgpu_device *adev);
947 void (*select_se_sh)(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
948 void (*read_wave_data)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields);
949 void (*read_wave_vgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t thread, uint32_t start, uint32_t size, uint32_t *dst);
950 void (*read_wave_sgprs)(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t start, uint32_t size, uint32_t *dst);
951 };
952
953 struct amdgpu_ngg_buf {
954 struct amdgpu_bo *bo;
955 uint64_t gpu_addr;
956 uint32_t size;
957 uint32_t bo_size;
958 };
959
960 enum {
961 NGG_PRIM = 0,
962 NGG_POS,
963 NGG_CNTL,
964 NGG_PARAM,
965 NGG_BUF_MAX
966 };
967
968 struct amdgpu_ngg {
969 struct amdgpu_ngg_buf buf[NGG_BUF_MAX];
970 uint32_t gds_reserve_addr;
971 uint32_t gds_reserve_size;
972 bool init;
973 };
974
975 struct amdgpu_gfx {
976 struct mutex gpu_clock_mutex;
977 struct amdgpu_gfx_config config;
978 struct amdgpu_rlc rlc;
979 struct amdgpu_mec mec;
980 struct amdgpu_kiq kiq;
981 struct amdgpu_scratch scratch;
982 const struct firmware *me_fw; /* ME firmware */
983 uint32_t me_fw_version;
984 const struct firmware *pfp_fw; /* PFP firmware */
985 uint32_t pfp_fw_version;
986 const struct firmware *ce_fw; /* CE firmware */
987 uint32_t ce_fw_version;
988 const struct firmware *rlc_fw; /* RLC firmware */
989 uint32_t rlc_fw_version;
990 const struct firmware *mec_fw; /* MEC firmware */
991 uint32_t mec_fw_version;
992 const struct firmware *mec2_fw; /* MEC2 firmware */
993 uint32_t mec2_fw_version;
994 uint32_t me_feature_version;
995 uint32_t ce_feature_version;
996 uint32_t pfp_feature_version;
997 uint32_t rlc_feature_version;
998 uint32_t mec_feature_version;
999 uint32_t mec2_feature_version;
1000 struct amdgpu_ring gfx_ring[AMDGPU_MAX_GFX_RINGS];
1001 unsigned num_gfx_rings;
1002 struct amdgpu_ring compute_ring[AMDGPU_MAX_COMPUTE_RINGS];
1003 unsigned num_compute_rings;
1004 struct amdgpu_irq_src eop_irq;
1005 struct amdgpu_irq_src priv_reg_irq;
1006 struct amdgpu_irq_src priv_inst_irq;
1007 /* gfx status */
1008 uint32_t gfx_current_status;
1009 /* ce ram size*/
1010 unsigned ce_ram_size;
1011 struct amdgpu_cu_info cu_info;
1012 const struct amdgpu_gfx_funcs *funcs;
1013
1014 /* reset mask */
1015 uint32_t grbm_soft_reset;
1016 uint32_t srbm_soft_reset;
1017 bool in_reset;
1018 /* s3/s4 mask */
1019 bool in_suspend;
1020 /* NGG */
1021 struct amdgpu_ngg ngg;
1022 };
1023
1024 int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
1025 unsigned size, struct amdgpu_ib *ib);
1026 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib,
1027 struct dma_fence *f);
1028 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
1029 struct amdgpu_ib *ibs, struct amdgpu_job *job,
1030 struct dma_fence **f);
1031 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
1032 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
1033 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
1034
1035 /*
1036 * CS.
1037 */
1038 struct amdgpu_cs_chunk {
1039 uint32_t chunk_id;
1040 uint32_t length_dw;
1041 void *kdata;
1042 };
1043
1044 struct amdgpu_cs_parser {
1045 struct amdgpu_device *adev;
1046 struct drm_file *filp;
1047 struct amdgpu_ctx *ctx;
1048
1049 /* chunks */
1050 unsigned nchunks;
1051 struct amdgpu_cs_chunk *chunks;
1052
1053 /* scheduler job object */
1054 struct amdgpu_job *job;
1055
1056 /* buffer objects */
1057 struct ww_acquire_ctx ticket;
1058 struct amdgpu_bo_list *bo_list;
1059 struct amdgpu_bo_list_entry vm_pd;
1060 struct list_head validated;
1061 struct dma_fence *fence;
1062 uint64_t bytes_moved_threshold;
1063 uint64_t bytes_moved_vis_threshold;
1064 uint64_t bytes_moved;
1065 uint64_t bytes_moved_vis;
1066 struct amdgpu_bo_list_entry *evictable;
1067
1068 /* user fence */
1069 struct amdgpu_bo_list_entry uf_entry;
1070
1071 unsigned num_post_dep_syncobjs;
1072 struct drm_syncobj **post_dep_syncobjs;
1073 };
1074
1075 #define AMDGPU_PREAMBLE_IB_PRESENT (1 << 0) /* bit set means command submit involves a preamble IB */
1076 #define AMDGPU_PREAMBLE_IB_PRESENT_FIRST (1 << 1) /* bit set means preamble IB is first presented in belonging context */
1077 #define AMDGPU_HAVE_CTX_SWITCH (1 << 2) /* bit set means context switch occured */
1078
1079 struct amdgpu_job {
1080 struct amd_sched_job base;
1081 struct amdgpu_device *adev;
1082 struct amdgpu_vm *vm;
1083 struct amdgpu_ring *ring;
1084 struct amdgpu_sync sync;
1085 struct amdgpu_sync dep_sync;
1086 struct amdgpu_sync sched_sync;
1087 struct amdgpu_ib *ibs;
1088 struct dma_fence *fence; /* the hw fence */
1089 uint32_t preamble_status;
1090 uint32_t num_ibs;
1091 void *owner;
1092 uint64_t fence_ctx; /* the fence_context this job uses */
1093 bool vm_needs_flush;
1094 unsigned vm_id;
1095 uint64_t vm_pd_addr;
1096 uint32_t gds_base, gds_size;
1097 uint32_t gws_base, gws_size;
1098 uint32_t oa_base, oa_size;
1099
1100 /* user fence handling */
1101 uint64_t uf_addr;
1102 uint64_t uf_sequence;
1103
1104 };
1105 #define to_amdgpu_job(sched_job) \
1106 container_of((sched_job), struct amdgpu_job, base)
1107
amdgpu_get_ib_value(struct amdgpu_cs_parser * p,uint32_t ib_idx,int idx)1108 static inline u32 amdgpu_get_ib_value(struct amdgpu_cs_parser *p,
1109 uint32_t ib_idx, int idx)
1110 {
1111 return p->job->ibs[ib_idx].ptr[idx];
1112 }
1113
amdgpu_set_ib_value(struct amdgpu_cs_parser * p,uint32_t ib_idx,int idx,uint32_t value)1114 static inline void amdgpu_set_ib_value(struct amdgpu_cs_parser *p,
1115 uint32_t ib_idx, int idx,
1116 uint32_t value)
1117 {
1118 p->job->ibs[ib_idx].ptr[idx] = value;
1119 }
1120
1121 /*
1122 * Writeback
1123 */
1124 #define AMDGPU_MAX_WB 1024 /* Reserve at most 1024 WB slots for amdgpu-owned rings. */
1125
1126 struct amdgpu_wb {
1127 struct amdgpu_bo *wb_obj;
1128 volatile uint32_t *wb;
1129 uint64_t gpu_addr;
1130 u32 num_wb; /* Number of wb slots actually reserved for amdgpu. */
1131 unsigned long used[DIV_ROUND_UP(AMDGPU_MAX_WB, BITS_PER_LONG)];
1132 };
1133
1134 int amdgpu_wb_get(struct amdgpu_device *adev, u32 *wb);
1135 void amdgpu_wb_free(struct amdgpu_device *adev, u32 wb);
1136
1137 void amdgpu_get_pcie_info(struct amdgpu_device *adev);
1138
1139 /*
1140 * SDMA
1141 */
1142 struct amdgpu_sdma_instance {
1143 /* SDMA firmware */
1144 const struct firmware *fw;
1145 uint32_t fw_version;
1146 uint32_t feature_version;
1147
1148 struct amdgpu_ring ring;
1149 bool burst_nop;
1150 };
1151
1152 struct amdgpu_sdma {
1153 struct amdgpu_sdma_instance instance[AMDGPU_MAX_SDMA_INSTANCES];
1154 #ifdef CONFIG_DRM_AMDGPU_SI
1155 //SI DMA has a difference trap irq number for the second engine
1156 struct amdgpu_irq_src trap_irq_1;
1157 #endif
1158 struct amdgpu_irq_src trap_irq;
1159 struct amdgpu_irq_src illegal_inst_irq;
1160 int num_instances;
1161 uint32_t srbm_soft_reset;
1162 };
1163
1164 /*
1165 * Firmware
1166 */
1167 enum amdgpu_firmware_load_type {
1168 AMDGPU_FW_LOAD_DIRECT = 0,
1169 AMDGPU_FW_LOAD_SMU,
1170 AMDGPU_FW_LOAD_PSP,
1171 };
1172
1173 struct amdgpu_firmware {
1174 struct amdgpu_firmware_info ucode[AMDGPU_UCODE_ID_MAXIMUM];
1175 enum amdgpu_firmware_load_type load_type;
1176 struct amdgpu_bo *fw_buf;
1177 unsigned int fw_size;
1178 unsigned int max_ucodes;
1179 /* firmwares are loaded by psp instead of smu from vega10 */
1180 const struct amdgpu_psp_funcs *funcs;
1181 struct amdgpu_bo *rbuf;
1182 struct mutex mutex;
1183
1184 /* gpu info firmware data pointer */
1185 const struct firmware *gpu_info_fw;
1186 };
1187
1188 /*
1189 * Benchmarking
1190 */
1191 void amdgpu_benchmark(struct amdgpu_device *adev, int test_number);
1192
1193
1194 /*
1195 * Testing
1196 */
1197 void amdgpu_test_moves(struct amdgpu_device *adev);
1198
1199 /*
1200 * MMU Notifier
1201 */
1202 #if defined(CONFIG_MMU_NOTIFIER)
1203 int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr);
1204 void amdgpu_mn_unregister(struct amdgpu_bo *bo);
1205 #else
amdgpu_mn_register(struct amdgpu_bo * bo,unsigned long addr)1206 static inline int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
1207 {
1208 return -ENODEV;
1209 }
amdgpu_mn_unregister(struct amdgpu_bo * bo)1210 static inline void amdgpu_mn_unregister(struct amdgpu_bo *bo) {}
1211 #endif
1212
1213 /*
1214 * Debugfs
1215 */
1216 struct amdgpu_debugfs {
1217 const struct drm_info_list *files;
1218 unsigned num_files;
1219 };
1220
1221 int amdgpu_debugfs_add_files(struct amdgpu_device *adev,
1222 const struct drm_info_list *files,
1223 unsigned nfiles);
1224 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev);
1225
1226 #if defined(CONFIG_DEBUG_FS)
1227 int amdgpu_debugfs_init(struct drm_minor *minor);
1228 #endif
1229
1230 int amdgpu_debugfs_firmware_init(struct amdgpu_device *adev);
1231
1232 /*
1233 * amdgpu smumgr functions
1234 */
1235 struct amdgpu_smumgr_funcs {
1236 int (*check_fw_load_finish)(struct amdgpu_device *adev, uint32_t fwtype);
1237 int (*request_smu_load_fw)(struct amdgpu_device *adev);
1238 int (*request_smu_specific_fw)(struct amdgpu_device *adev, uint32_t fwtype);
1239 };
1240
1241 /*
1242 * amdgpu smumgr
1243 */
1244 struct amdgpu_smumgr {
1245 struct amdgpu_bo *toc_buf;
1246 struct amdgpu_bo *smu_buf;
1247 /* asic priv smu data */
1248 void *priv;
1249 spinlock_t smu_lock;
1250 /* smumgr functions */
1251 const struct amdgpu_smumgr_funcs *smumgr_funcs;
1252 /* ucode loading complete flag */
1253 uint32_t fw_flags;
1254 };
1255
1256 /*
1257 * ASIC specific register table accessible by UMD
1258 */
1259 struct amdgpu_allowed_register_entry {
1260 uint32_t reg_offset;
1261 bool grbm_indexed;
1262 };
1263
1264 /*
1265 * ASIC specific functions.
1266 */
1267 struct amdgpu_asic_funcs {
1268 bool (*read_disabled_bios)(struct amdgpu_device *adev);
1269 bool (*read_bios_from_rom)(struct amdgpu_device *adev,
1270 u8 *bios, u32 length_bytes);
1271 int (*read_register)(struct amdgpu_device *adev, u32 se_num,
1272 u32 sh_num, u32 reg_offset, u32 *value);
1273 void (*set_vga_state)(struct amdgpu_device *adev, bool state);
1274 int (*reset)(struct amdgpu_device *adev);
1275 /* get the reference clock */
1276 u32 (*get_xclk)(struct amdgpu_device *adev);
1277 /* MM block clocks */
1278 int (*set_uvd_clocks)(struct amdgpu_device *adev, u32 vclk, u32 dclk);
1279 int (*set_vce_clocks)(struct amdgpu_device *adev, u32 evclk, u32 ecclk);
1280 /* static power management */
1281 int (*get_pcie_lanes)(struct amdgpu_device *adev);
1282 void (*set_pcie_lanes)(struct amdgpu_device *adev, int lanes);
1283 /* get config memsize register */
1284 u32 (*get_config_memsize)(struct amdgpu_device *adev);
1285 };
1286
1287 /*
1288 * IOCTL.
1289 */
1290 int amdgpu_gem_create_ioctl(struct drm_device *dev, void *data,
1291 struct drm_file *filp);
1292 int amdgpu_bo_list_ioctl(struct drm_device *dev, void *data,
1293 struct drm_file *filp);
1294
1295 int amdgpu_gem_info_ioctl(struct drm_device *dev, void *data,
1296 struct drm_file *filp);
1297 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data,
1298 struct drm_file *filp);
1299 int amdgpu_gem_mmap_ioctl(struct drm_device *dev, void *data,
1300 struct drm_file *filp);
1301 int amdgpu_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
1302 struct drm_file *filp);
1303 int amdgpu_gem_va_ioctl(struct drm_device *dev, void *data,
1304 struct drm_file *filp);
1305 int amdgpu_gem_op_ioctl(struct drm_device *dev, void *data,
1306 struct drm_file *filp);
1307 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1308 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
1309 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1310 struct drm_file *filp);
1311
1312 int amdgpu_gem_metadata_ioctl(struct drm_device *dev, void *data,
1313 struct drm_file *filp);
1314
1315 /* VRAM scratch page for HDP bug, default vram page */
1316 struct amdgpu_vram_scratch {
1317 struct amdgpu_bo *robj;
1318 volatile uint32_t *ptr;
1319 u64 gpu_addr;
1320 };
1321
1322 /*
1323 * ACPI
1324 */
1325 struct amdgpu_atif_notification_cfg {
1326 bool enabled;
1327 int command_code;
1328 };
1329
1330 struct amdgpu_atif_notifications {
1331 bool display_switch;
1332 bool expansion_mode_change;
1333 bool thermal_state;
1334 bool forced_power_state;
1335 bool system_power_state;
1336 bool display_conf_change;
1337 bool px_gfx_switch;
1338 bool brightness_change;
1339 bool dgpu_display_event;
1340 };
1341
1342 struct amdgpu_atif_functions {
1343 bool system_params;
1344 bool sbios_requests;
1345 bool select_active_disp;
1346 bool lid_state;
1347 bool get_tv_standard;
1348 bool set_tv_standard;
1349 bool get_panel_expansion_mode;
1350 bool set_panel_expansion_mode;
1351 bool temperature_change;
1352 bool graphics_device_types;
1353 };
1354
1355 struct amdgpu_atif {
1356 struct amdgpu_atif_notifications notifications;
1357 struct amdgpu_atif_functions functions;
1358 struct amdgpu_atif_notification_cfg notification_cfg;
1359 struct amdgpu_encoder *encoder_for_bl;
1360 };
1361
1362 struct amdgpu_atcs_functions {
1363 bool get_ext_state;
1364 bool pcie_perf_req;
1365 bool pcie_dev_rdy;
1366 bool pcie_bus_width;
1367 };
1368
1369 struct amdgpu_atcs {
1370 struct amdgpu_atcs_functions functions;
1371 };
1372
1373 /*
1374 * CGS
1375 */
1376 struct cgs_device *amdgpu_cgs_create_device(struct amdgpu_device *adev);
1377 void amdgpu_cgs_destroy_device(struct cgs_device *cgs_device);
1378
1379 /*
1380 * Core structure, functions and helpers.
1381 */
1382 typedef uint32_t (*amdgpu_rreg_t)(struct amdgpu_device*, uint32_t);
1383 typedef void (*amdgpu_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1384
1385 typedef uint32_t (*amdgpu_block_rreg_t)(struct amdgpu_device*, uint32_t, uint32_t);
1386 typedef void (*amdgpu_block_wreg_t)(struct amdgpu_device*, uint32_t, uint32_t, uint32_t);
1387
1388 #define AMDGPU_RESET_MAGIC_NUM 64
1389 struct amdgpu_device {
1390 struct device *dev;
1391 struct drm_device *ddev;
1392 struct pci_dev *pdev;
1393
1394 #ifdef CONFIG_DRM_AMD_ACP
1395 struct amdgpu_acp acp;
1396 #endif
1397
1398 /* ASIC */
1399 enum amd_asic_type asic_type;
1400 uint32_t family;
1401 uint32_t rev_id;
1402 uint32_t external_rev_id;
1403 unsigned long flags;
1404 int usec_timeout;
1405 const struct amdgpu_asic_funcs *asic_funcs;
1406 bool shutdown;
1407 bool need_dma32;
1408 bool accel_working;
1409 struct work_struct reset_work;
1410 struct notifier_block acpi_nb;
1411 struct amdgpu_i2c_chan *i2c_bus[AMDGPU_MAX_I2C_BUS];
1412 struct amdgpu_debugfs debugfs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1413 unsigned debugfs_count;
1414 #if defined(CONFIG_DEBUG_FS)
1415 struct dentry *debugfs_regs[AMDGPU_DEBUGFS_MAX_COMPONENTS];
1416 #endif
1417 struct amdgpu_atif atif;
1418 struct amdgpu_atcs atcs;
1419 struct mutex srbm_mutex;
1420 /* GRBM index mutex. Protects concurrent access to GRBM index */
1421 struct mutex grbm_idx_mutex;
1422 struct dev_pm_domain vga_pm_domain;
1423 bool have_disp_power_ref;
1424
1425 /* BIOS */
1426 bool is_atom_fw;
1427 uint8_t *bios;
1428 uint32_t bios_size;
1429 struct amdgpu_bo *stolen_vga_memory;
1430 uint32_t bios_scratch_reg_offset;
1431 uint32_t bios_scratch[AMDGPU_BIOS_NUM_SCRATCH];
1432
1433 /* Register/doorbell mmio */
1434 resource_size_t rmmio_base;
1435 resource_size_t rmmio_size;
1436 void __iomem *rmmio;
1437 /* protects concurrent MM_INDEX/DATA based register access */
1438 spinlock_t mmio_idx_lock;
1439 /* protects concurrent SMC based register access */
1440 spinlock_t smc_idx_lock;
1441 amdgpu_rreg_t smc_rreg;
1442 amdgpu_wreg_t smc_wreg;
1443 /* protects concurrent PCIE register access */
1444 spinlock_t pcie_idx_lock;
1445 amdgpu_rreg_t pcie_rreg;
1446 amdgpu_wreg_t pcie_wreg;
1447 amdgpu_rreg_t pciep_rreg;
1448 amdgpu_wreg_t pciep_wreg;
1449 /* protects concurrent UVD register access */
1450 spinlock_t uvd_ctx_idx_lock;
1451 amdgpu_rreg_t uvd_ctx_rreg;
1452 amdgpu_wreg_t uvd_ctx_wreg;
1453 /* protects concurrent DIDT register access */
1454 spinlock_t didt_idx_lock;
1455 amdgpu_rreg_t didt_rreg;
1456 amdgpu_wreg_t didt_wreg;
1457 /* protects concurrent gc_cac register access */
1458 spinlock_t gc_cac_idx_lock;
1459 amdgpu_rreg_t gc_cac_rreg;
1460 amdgpu_wreg_t gc_cac_wreg;
1461 /* protects concurrent se_cac register access */
1462 spinlock_t se_cac_idx_lock;
1463 amdgpu_rreg_t se_cac_rreg;
1464 amdgpu_wreg_t se_cac_wreg;
1465 /* protects concurrent ENDPOINT (audio) register access */
1466 spinlock_t audio_endpt_idx_lock;
1467 amdgpu_block_rreg_t audio_endpt_rreg;
1468 amdgpu_block_wreg_t audio_endpt_wreg;
1469 void __iomem *rio_mem;
1470 resource_size_t rio_mem_size;
1471 struct amdgpu_doorbell doorbell;
1472
1473 /* clock/pll info */
1474 struct amdgpu_clock clock;
1475
1476 /* MC */
1477 struct amdgpu_mc mc;
1478 struct amdgpu_gart gart;
1479 struct amdgpu_dummy_page dummy_page;
1480 struct amdgpu_vm_manager vm_manager;
1481 struct amdgpu_vmhub vmhub[AMDGPU_MAX_VMHUBS];
1482
1483 /* memory management */
1484 struct amdgpu_mman mman;
1485 struct amdgpu_vram_scratch vram_scratch;
1486 struct amdgpu_wb wb;
1487 atomic64_t num_bytes_moved;
1488 atomic64_t num_evictions;
1489 atomic64_t num_vram_cpu_page_faults;
1490 atomic_t gpu_reset_counter;
1491 atomic_t vram_lost_counter;
1492
1493 /* data for buffer migration throttling */
1494 struct {
1495 spinlock_t lock;
1496 s64 last_update_us;
1497 s64 accum_us; /* accumulated microseconds */
1498 s64 accum_us_vis; /* for visible VRAM */
1499 u32 log2_max_MBps;
1500 } mm_stats;
1501
1502 /* display */
1503 bool enable_virtual_display;
1504 struct amdgpu_mode_info mode_info;
1505 struct work_struct hotplug_work;
1506 struct amdgpu_irq_src crtc_irq;
1507 struct amdgpu_irq_src pageflip_irq;
1508 struct amdgpu_irq_src hpd_irq;
1509
1510 /* rings */
1511 u64 fence_context;
1512 unsigned num_rings;
1513 struct amdgpu_ring *rings[AMDGPU_MAX_RINGS];
1514 bool ib_pool_ready;
1515 struct amdgpu_sa_manager ring_tmp_bo;
1516
1517 /* interrupts */
1518 struct amdgpu_irq irq;
1519
1520 /* powerplay */
1521 struct amd_powerplay powerplay;
1522 bool pp_enabled;
1523 bool pp_force_state_enabled;
1524
1525 /* dpm */
1526 struct amdgpu_pm pm;
1527 u32 cg_flags;
1528 u32 pg_flags;
1529
1530 /* amdgpu smumgr */
1531 struct amdgpu_smumgr smu;
1532
1533 /* gfx */
1534 struct amdgpu_gfx gfx;
1535
1536 /* sdma */
1537 struct amdgpu_sdma sdma;
1538
1539 /* uvd */
1540 struct amdgpu_uvd uvd;
1541
1542 /* vce */
1543 struct amdgpu_vce vce;
1544
1545 /* vcn */
1546 struct amdgpu_vcn vcn;
1547
1548 /* firmwares */
1549 struct amdgpu_firmware firmware;
1550
1551 /* PSP */
1552 struct psp_context psp;
1553
1554 /* GDS */
1555 struct amdgpu_gds gds;
1556
1557 struct amdgpu_ip_block ip_blocks[AMDGPU_MAX_IP_NUM];
1558 int num_ip_blocks;
1559 struct mutex mn_lock;
1560 DECLARE_HASHTABLE(mn_hash, 7);
1561
1562 /* tracking pinned memory */
1563 u64 vram_pin_size;
1564 u64 invisible_pin_size;
1565 u64 gart_pin_size;
1566
1567 /* amdkfd interface */
1568 struct kfd_dev *kfd;
1569
1570 /* delayed work_func for deferring clockgating during resume */
1571 struct delayed_work late_init_work;
1572
1573 struct amdgpu_virt virt;
1574
1575 /* link all shadow bo */
1576 struct list_head shadow_list;
1577 struct mutex shadow_list_lock;
1578 /* link all gtt */
1579 spinlock_t gtt_list_lock;
1580 struct list_head gtt_list;
1581 /* keep an lru list of rings by HW IP */
1582 struct list_head ring_lru_list;
1583 spinlock_t ring_lru_list_lock;
1584
1585 /* record hw reset is performed */
1586 bool has_hw_reset;
1587 u8 reset_magic[AMDGPU_RESET_MAGIC_NUM];
1588
1589 /* record last mm index being written through WREG32*/
1590 unsigned long last_mm_index;
1591 };
1592
amdgpu_ttm_adev(struct ttm_bo_device * bdev)1593 static inline struct amdgpu_device *amdgpu_ttm_adev(struct ttm_bo_device *bdev)
1594 {
1595 return container_of(bdev, struct amdgpu_device, mman.bdev);
1596 }
1597
1598 int amdgpu_device_init(struct amdgpu_device *adev,
1599 struct drm_device *ddev,
1600 struct pci_dev *pdev,
1601 uint32_t flags);
1602 void amdgpu_device_fini(struct amdgpu_device *adev);
1603 int amdgpu_gpu_wait_for_idle(struct amdgpu_device *adev);
1604
1605 uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
1606 uint32_t acc_flags);
1607 void amdgpu_mm_wreg(struct amdgpu_device *adev, uint32_t reg, uint32_t v,
1608 uint32_t acc_flags);
1609 u32 amdgpu_io_rreg(struct amdgpu_device *adev, u32 reg);
1610 void amdgpu_io_wreg(struct amdgpu_device *adev, u32 reg, u32 v);
1611
1612 u32 amdgpu_mm_rdoorbell(struct amdgpu_device *adev, u32 index);
1613 void amdgpu_mm_wdoorbell(struct amdgpu_device *adev, u32 index, u32 v);
1614 u64 amdgpu_mm_rdoorbell64(struct amdgpu_device *adev, u32 index);
1615 void amdgpu_mm_wdoorbell64(struct amdgpu_device *adev, u32 index, u64 v);
1616
1617 /*
1618 * Registers read & write functions.
1619 */
1620
1621 #define AMDGPU_REGS_IDX (1<<0)
1622 #define AMDGPU_REGS_NO_KIQ (1<<1)
1623
1624 #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
1625 #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
1626
1627 #define RREG32(reg) amdgpu_mm_rreg(adev, (reg), 0)
1628 #define RREG32_IDX(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_IDX)
1629 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", amdgpu_mm_rreg(adev, (reg), 0))
1630 #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), 0)
1631 #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_IDX)
1632 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1633 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1634 #define RREG32_PCIE(reg) adev->pcie_rreg(adev, (reg))
1635 #define WREG32_PCIE(reg, v) adev->pcie_wreg(adev, (reg), (v))
1636 #define RREG32_PCIE_PORT(reg) adev->pciep_rreg(adev, (reg))
1637 #define WREG32_PCIE_PORT(reg, v) adev->pciep_wreg(adev, (reg), (v))
1638 #define RREG32_SMC(reg) adev->smc_rreg(adev, (reg))
1639 #define WREG32_SMC(reg, v) adev->smc_wreg(adev, (reg), (v))
1640 #define RREG32_UVD_CTX(reg) adev->uvd_ctx_rreg(adev, (reg))
1641 #define WREG32_UVD_CTX(reg, v) adev->uvd_ctx_wreg(adev, (reg), (v))
1642 #define RREG32_DIDT(reg) adev->didt_rreg(adev, (reg))
1643 #define WREG32_DIDT(reg, v) adev->didt_wreg(adev, (reg), (v))
1644 #define RREG32_GC_CAC(reg) adev->gc_cac_rreg(adev, (reg))
1645 #define WREG32_GC_CAC(reg, v) adev->gc_cac_wreg(adev, (reg), (v))
1646 #define RREG32_SE_CAC(reg) adev->se_cac_rreg(adev, (reg))
1647 #define WREG32_SE_CAC(reg, v) adev->se_cac_wreg(adev, (reg), (v))
1648 #define RREG32_AUDIO_ENDPT(block, reg) adev->audio_endpt_rreg(adev, (block), (reg))
1649 #define WREG32_AUDIO_ENDPT(block, reg, v) adev->audio_endpt_wreg(adev, (block), (reg), (v))
1650 #define WREG32_P(reg, val, mask) \
1651 do { \
1652 uint32_t tmp_ = RREG32(reg); \
1653 tmp_ &= (mask); \
1654 tmp_ |= ((val) & ~(mask)); \
1655 WREG32(reg, tmp_); \
1656 } while (0)
1657 #define WREG32_AND(reg, and) WREG32_P(reg, 0, and)
1658 #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or))
1659 #define WREG32_PLL_P(reg, val, mask) \
1660 do { \
1661 uint32_t tmp_ = RREG32_PLL(reg); \
1662 tmp_ &= (mask); \
1663 tmp_ |= ((val) & ~(mask)); \
1664 WREG32_PLL(reg, tmp_); \
1665 } while (0)
1666 #define DREG32_SYS(sqf, adev, reg) seq_printf((sqf), #reg " : 0x%08X\n", amdgpu_mm_rreg((adev), (reg), false))
1667 #define RREG32_IO(reg) amdgpu_io_rreg(adev, (reg))
1668 #define WREG32_IO(reg, v) amdgpu_io_wreg(adev, (reg), (v))
1669
1670 #define RDOORBELL32(index) amdgpu_mm_rdoorbell(adev, (index))
1671 #define WDOORBELL32(index, v) amdgpu_mm_wdoorbell(adev, (index), (v))
1672 #define RDOORBELL64(index) amdgpu_mm_rdoorbell64(adev, (index))
1673 #define WDOORBELL64(index, v) amdgpu_mm_wdoorbell64(adev, (index), (v))
1674
1675 #define REG_FIELD_SHIFT(reg, field) reg##__##field##__SHIFT
1676 #define REG_FIELD_MASK(reg, field) reg##__##field##_MASK
1677
1678 #define REG_SET_FIELD(orig_val, reg, field, field_val) \
1679 (((orig_val) & ~REG_FIELD_MASK(reg, field)) | \
1680 (REG_FIELD_MASK(reg, field) & ((field_val) << REG_FIELD_SHIFT(reg, field))))
1681
1682 #define REG_GET_FIELD(value, reg, field) \
1683 (((value) & REG_FIELD_MASK(reg, field)) >> REG_FIELD_SHIFT(reg, field))
1684
1685 #define WREG32_FIELD(reg, field, val) \
1686 WREG32(mm##reg, (RREG32(mm##reg) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1687
1688 #define WREG32_FIELD_OFFSET(reg, offset, field, val) \
1689 WREG32(mm##reg + offset, (RREG32(mm##reg + offset) & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
1690
1691 /*
1692 * BIOS helpers.
1693 */
1694 #define RBIOS8(i) (adev->bios[i])
1695 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1696 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1697
1698 static inline struct amdgpu_sdma_instance *
amdgpu_get_sdma_instance(struct amdgpu_ring * ring)1699 amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
1700 {
1701 struct amdgpu_device *adev = ring->adev;
1702 int i;
1703
1704 for (i = 0; i < adev->sdma.num_instances; i++)
1705 if (&adev->sdma.instance[i].ring == ring)
1706 break;
1707
1708 if (i < AMDGPU_MAX_SDMA_INSTANCES)
1709 return &adev->sdma.instance[i];
1710 else
1711 return NULL;
1712 }
1713
1714 /*
1715 * ASICs macro.
1716 */
1717 #define amdgpu_asic_set_vga_state(adev, state) (adev)->asic_funcs->set_vga_state((adev), (state))
1718 #define amdgpu_asic_reset(adev) (adev)->asic_funcs->reset((adev))
1719 #define amdgpu_asic_get_xclk(adev) (adev)->asic_funcs->get_xclk((adev))
1720 #define amdgpu_asic_set_uvd_clocks(adev, v, d) (adev)->asic_funcs->set_uvd_clocks((adev), (v), (d))
1721 #define amdgpu_asic_set_vce_clocks(adev, ev, ec) (adev)->asic_funcs->set_vce_clocks((adev), (ev), (ec))
1722 #define amdgpu_get_pcie_lanes(adev) (adev)->asic_funcs->get_pcie_lanes((adev))
1723 #define amdgpu_set_pcie_lanes(adev, l) (adev)->asic_funcs->set_pcie_lanes((adev), (l))
1724 #define amdgpu_asic_get_gpu_clock_counter(adev) (adev)->asic_funcs->get_gpu_clock_counter((adev))
1725 #define amdgpu_asic_read_disabled_bios(adev) (adev)->asic_funcs->read_disabled_bios((adev))
1726 #define amdgpu_asic_read_bios_from_rom(adev, b, l) (adev)->asic_funcs->read_bios_from_rom((adev), (b), (l))
1727 #define amdgpu_asic_read_register(adev, se, sh, offset, v)((adev)->asic_funcs->read_register((adev), (se), (sh), (offset), (v)))
1728 #define amdgpu_asic_get_config_memsize(adev) (adev)->asic_funcs->get_config_memsize((adev))
1729 #define amdgpu_gart_flush_gpu_tlb(adev, vmid) (adev)->gart.gart_funcs->flush_gpu_tlb((adev), (vmid))
1730 #define amdgpu_gart_set_pte_pde(adev, pt, idx, addr, flags) (adev)->gart.gart_funcs->set_pte_pde((adev), (pt), (idx), (addr), (flags))
1731 #define amdgpu_gart_get_vm_pde(adev, addr) (adev)->gart.gart_funcs->get_vm_pde((adev), (addr))
1732 #define amdgpu_vm_copy_pte(adev, ib, pe, src, count) ((adev)->vm_manager.vm_pte_funcs->copy_pte((ib), (pe), (src), (count)))
1733 #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
1734 #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
1735 #define amdgpu_vm_get_pte_flags(adev, flags) (adev)->gart.gart_funcs->get_vm_pte_flags((adev),(flags))
1736 #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
1737 #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
1738 #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
1739 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
1740 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
1741 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
1742 #define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
1743 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
1744 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
1745 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))
1746 #define amdgpu_ring_emit_gds_switch(r, v, db, ds, wb, ws, ab, as) (r)->funcs->emit_gds_switch((r), (v), (db), (ds), (wb), (ws), (ab), (as))
1747 #define amdgpu_ring_emit_hdp_flush(r) (r)->funcs->emit_hdp_flush((r))
1748 #define amdgpu_ring_emit_hdp_invalidate(r) (r)->funcs->emit_hdp_invalidate((r))
1749 #define amdgpu_ring_emit_switch_buffer(r) (r)->funcs->emit_switch_buffer((r))
1750 #define amdgpu_ring_emit_cntxcntl(r, d) (r)->funcs->emit_cntxcntl((r), (d))
1751 #define amdgpu_ring_emit_rreg(r, d) (r)->funcs->emit_rreg((r), (d))
1752 #define amdgpu_ring_emit_wreg(r, d, v) (r)->funcs->emit_wreg((r), (d), (v))
1753 #define amdgpu_ring_emit_tmz(r, b) (r)->funcs->emit_tmz((r), (b))
1754 #define amdgpu_ring_pad_ib(r, ib) ((r)->funcs->pad_ib((r), (ib)))
1755 #define amdgpu_ring_init_cond_exec(r) (r)->funcs->init_cond_exec((r))
1756 #define amdgpu_ring_patch_cond_exec(r,o) (r)->funcs->patch_cond_exec((r),(o))
1757 #define amdgpu_ih_get_wptr(adev) (adev)->irq.ih_funcs->get_wptr((adev))
1758 #define amdgpu_ih_decode_iv(adev, iv) (adev)->irq.ih_funcs->decode_iv((adev), (iv))
1759 #define amdgpu_ih_set_rptr(adev) (adev)->irq.ih_funcs->set_rptr((adev))
1760 #define amdgpu_display_vblank_get_counter(adev, crtc) (adev)->mode_info.funcs->vblank_get_counter((adev), (crtc))
1761 #define amdgpu_display_vblank_wait(adev, crtc) (adev)->mode_info.funcs->vblank_wait((adev), (crtc))
1762 #define amdgpu_display_backlight_set_level(adev, e, l) (adev)->mode_info.funcs->backlight_set_level((e), (l))
1763 #define amdgpu_display_backlight_get_level(adev, e) (adev)->mode_info.funcs->backlight_get_level((e))
1764 #define amdgpu_display_hpd_sense(adev, h) (adev)->mode_info.funcs->hpd_sense((adev), (h))
1765 #define amdgpu_display_hpd_set_polarity(adev, h) (adev)->mode_info.funcs->hpd_set_polarity((adev), (h))
1766 #define amdgpu_display_hpd_get_gpio_reg(adev) (adev)->mode_info.funcs->hpd_get_gpio_reg((adev))
1767 #define amdgpu_display_bandwidth_update(adev) (adev)->mode_info.funcs->bandwidth_update((adev))
1768 #define amdgpu_display_page_flip(adev, crtc, base, async) (adev)->mode_info.funcs->page_flip((adev), (crtc), (base), (async))
1769 #define amdgpu_display_page_flip_get_scanoutpos(adev, crtc, vbl, pos) (adev)->mode_info.funcs->page_flip_get_scanoutpos((adev), (crtc), (vbl), (pos))
1770 #define amdgpu_display_add_encoder(adev, e, s, c) (adev)->mode_info.funcs->add_encoder((adev), (e), (s), (c))
1771 #define amdgpu_display_add_connector(adev, ci, sd, ct, ib, coi, h, r) (adev)->mode_info.funcs->add_connector((adev), (ci), (sd), (ct), (ib), (coi), (h), (r))
1772 #define amdgpu_emit_copy_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_copy_buffer((ib), (s), (d), (b))
1773 #define amdgpu_emit_fill_buffer(adev, ib, s, d, b) (adev)->mman.buffer_funcs->emit_fill_buffer((ib), (s), (d), (b))
1774 #define amdgpu_gfx_get_gpu_clock_counter(adev) (adev)->gfx.funcs->get_gpu_clock_counter((adev))
1775 #define amdgpu_gfx_select_se_sh(adev, se, sh, instance) (adev)->gfx.funcs->select_se_sh((adev), (se), (sh), (instance))
1776 #define amdgpu_gds_switch(adev, r, v, d, w, a) (adev)->gds.funcs->patch_gds_switch((r), (v), (d), (w), (a))
1777 #define amdgpu_psp_check_fw_loading_status(adev, i) (adev)->firmware.funcs->check_fw_loading_status((adev), (i))
1778
1779 /* Common functions */
1780 int amdgpu_gpu_reset(struct amdgpu_device *adev);
1781 bool amdgpu_need_backup(struct amdgpu_device *adev);
1782 void amdgpu_pci_config_reset(struct amdgpu_device *adev);
1783 bool amdgpu_need_post(struct amdgpu_device *adev);
1784 void amdgpu_update_display_priority(struct amdgpu_device *adev);
1785
1786 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
1787 u64 num_vis_bytes);
1788 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain);
1789 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo);
1790 int amdgpu_ttm_tt_get_user_pages(struct ttm_tt *ttm, struct page **pages);
1791 int amdgpu_ttm_tt_set_userptr(struct ttm_tt *ttm, uint64_t addr,
1792 uint32_t flags);
1793 bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
1794 struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
1795 bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
1796 unsigned long end);
1797 bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
1798 int *last_invalidated);
1799 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
1800 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
1801 struct ttm_mem_reg *mem);
1802 void amdgpu_vram_location(struct amdgpu_device *adev, struct amdgpu_mc *mc, u64 base);
1803 void amdgpu_gart_location(struct amdgpu_device *adev, struct amdgpu_mc *mc);
1804 void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
1805 int amdgpu_ttm_init(struct amdgpu_device *adev);
1806 void amdgpu_ttm_fini(struct amdgpu_device *adev);
1807 void amdgpu_program_register_sequence(struct amdgpu_device *adev,
1808 const u32 *registers,
1809 const u32 array_size);
1810
1811 bool amdgpu_device_is_px(struct drm_device *dev);
1812 /* atpx handler */
1813 #if defined(CONFIG_VGA_SWITCHEROO)
1814 void amdgpu_register_atpx_handler(void);
1815 void amdgpu_unregister_atpx_handler(void);
1816 bool amdgpu_has_atpx_dgpu_power_cntl(void);
1817 bool amdgpu_is_atpx_hybrid(void);
1818 bool amdgpu_atpx_dgpu_req_power_for_displays(void);
1819 bool amdgpu_has_atpx(void);
1820 #else
amdgpu_register_atpx_handler(void)1821 static inline void amdgpu_register_atpx_handler(void) {}
amdgpu_unregister_atpx_handler(void)1822 static inline void amdgpu_unregister_atpx_handler(void) {}
amdgpu_has_atpx_dgpu_power_cntl(void)1823 static inline bool amdgpu_has_atpx_dgpu_power_cntl(void) { return false; }
amdgpu_is_atpx_hybrid(void)1824 static inline bool amdgpu_is_atpx_hybrid(void) { return false; }
amdgpu_atpx_dgpu_req_power_for_displays(void)1825 static inline bool amdgpu_atpx_dgpu_req_power_for_displays(void) { return false; }
amdgpu_has_atpx(void)1826 static inline bool amdgpu_has_atpx(void) { return false; }
1827 #endif
1828
1829 /*
1830 * KMS
1831 */
1832 extern const struct drm_ioctl_desc amdgpu_ioctls_kms[];
1833 extern const int amdgpu_max_kms_ioctl;
1834
1835 bool amdgpu_kms_vram_lost(struct amdgpu_device *adev,
1836 struct amdgpu_fpriv *fpriv);
1837 int amdgpu_driver_load_kms(struct drm_device *dev, unsigned long flags);
1838 void amdgpu_driver_unload_kms(struct drm_device *dev);
1839 void amdgpu_driver_lastclose_kms(struct drm_device *dev);
1840 int amdgpu_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
1841 void amdgpu_driver_postclose_kms(struct drm_device *dev,
1842 struct drm_file *file_priv);
1843 int amdgpu_suspend(struct amdgpu_device *adev);
1844 int amdgpu_device_suspend(struct drm_device *dev, bool suspend, bool fbcon);
1845 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon);
1846 u32 amdgpu_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
1847 int amdgpu_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1848 void amdgpu_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
1849 long amdgpu_kms_compat_ioctl(struct file *filp, unsigned int cmd,
1850 unsigned long arg);
1851
1852 /*
1853 * functions used by amdgpu_encoder.c
1854 */
1855 struct amdgpu_afmt_acr {
1856 u32 clock;
1857
1858 int n_32khz;
1859 int cts_32khz;
1860
1861 int n_44_1khz;
1862 int cts_44_1khz;
1863
1864 int n_48khz;
1865 int cts_48khz;
1866
1867 };
1868
1869 struct amdgpu_afmt_acr amdgpu_afmt_acr(uint32_t clock);
1870
1871 /* amdgpu_acpi.c */
1872 #if defined(CONFIG_ACPI)
1873 int amdgpu_acpi_init(struct amdgpu_device *adev);
1874 void amdgpu_acpi_fini(struct amdgpu_device *adev);
1875 bool amdgpu_acpi_is_pcie_performance_request_supported(struct amdgpu_device *adev);
1876 int amdgpu_acpi_pcie_performance_request(struct amdgpu_device *adev,
1877 u8 perf_req, bool advertise);
1878 int amdgpu_acpi_pcie_notify_device_ready(struct amdgpu_device *adev);
1879 #else
amdgpu_acpi_init(struct amdgpu_device * adev)1880 static inline int amdgpu_acpi_init(struct amdgpu_device *adev) { return 0; }
amdgpu_acpi_fini(struct amdgpu_device * adev)1881 static inline void amdgpu_acpi_fini(struct amdgpu_device *adev) { }
1882 #endif
1883
1884 struct amdgpu_bo_va_mapping *
1885 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1886 uint64_t addr, struct amdgpu_bo **bo);
1887 int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser);
1888
1889 #include "amdgpu_object.h"
1890 #endif
1891