1 /* 2 * This file is part of the Chelsio T4 Ethernet driver for Linux. 3 * 4 * Copyright (c) 2003-2014 Chelsio Communications, Inc. All rights reserved. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef __T4_MSG_H 36 #define __T4_MSG_H 37 38 #include <linux/types.h> 39 40 enum { 41 CPL_PASS_OPEN_REQ = 0x1, 42 CPL_PASS_ACCEPT_RPL = 0x2, 43 CPL_ACT_OPEN_REQ = 0x3, 44 CPL_SET_TCB_FIELD = 0x5, 45 CPL_GET_TCB = 0x6, 46 CPL_CLOSE_CON_REQ = 0x8, 47 CPL_CLOSE_LISTSRV_REQ = 0x9, 48 CPL_ABORT_REQ = 0xA, 49 CPL_ABORT_RPL = 0xB, 50 CPL_RX_DATA_ACK = 0xD, 51 CPL_TX_PKT = 0xE, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_TID_RELEASE = 0x1A, 54 CPL_TX_DATA_ISO = 0x1F, 55 56 CPL_CLOSE_LISTSRV_RPL = 0x20, 57 CPL_L2T_WRITE_RPL = 0x23, 58 CPL_PASS_OPEN_RPL = 0x24, 59 CPL_ACT_OPEN_RPL = 0x25, 60 CPL_PEER_CLOSE = 0x26, 61 CPL_ABORT_REQ_RSS = 0x2B, 62 CPL_ABORT_RPL_RSS = 0x2D, 63 64 CPL_RX_PHYS_ADDR = 0x30, 65 CPL_CLOSE_CON_RPL = 0x32, 66 CPL_ISCSI_HDR = 0x33, 67 CPL_RDMA_CQE = 0x35, 68 CPL_RDMA_CQE_READ_RSP = 0x36, 69 CPL_RDMA_CQE_ERR = 0x37, 70 CPL_RX_DATA = 0x39, 71 CPL_SET_TCB_RPL = 0x3A, 72 CPL_RX_PKT = 0x3B, 73 CPL_RX_DDP_COMPLETE = 0x3F, 74 75 CPL_ACT_ESTABLISH = 0x40, 76 CPL_PASS_ESTABLISH = 0x41, 77 CPL_RX_DATA_DDP = 0x42, 78 CPL_PASS_ACCEPT_REQ = 0x44, 79 CPL_RX_ISCSI_CMP = 0x45, 80 CPL_TRACE_PKT_T5 = 0x48, 81 CPL_RX_ISCSI_DDP = 0x49, 82 83 CPL_RDMA_READ_REQ = 0x60, 84 85 CPL_PASS_OPEN_REQ6 = 0x81, 86 CPL_ACT_OPEN_REQ6 = 0x83, 87 88 CPL_TX_TLS_PDU = 0x88, 89 CPL_TX_SEC_PDU = 0x8A, 90 CPL_TX_TLS_ACK = 0x8B, 91 92 CPL_RDMA_TERMINATE = 0xA2, 93 CPL_RDMA_WRITE = 0xA4, 94 CPL_SGE_EGR_UPDATE = 0xA5, 95 CPL_RX_MPS_PKT = 0xAF, 96 97 CPL_TRACE_PKT = 0xB0, 98 CPL_ISCSI_DATA = 0xB2, 99 100 CPL_FW4_MSG = 0xC0, 101 CPL_FW4_PLD = 0xC1, 102 CPL_FW4_ACK = 0xC3, 103 104 CPL_RX_PHYS_DSGL = 0xD0, 105 106 CPL_FW6_MSG = 0xE0, 107 CPL_FW6_PLD = 0xE1, 108 CPL_TX_PKT_LSO = 0xED, 109 CPL_TX_PKT_XT = 0xEE, 110 111 NUM_CPL_CMDS 112 }; 113 114 enum CPL_error { 115 CPL_ERR_NONE = 0, 116 CPL_ERR_TCAM_PARITY = 1, 117 CPL_ERR_TCAM_MISS = 2, 118 CPL_ERR_TCAM_FULL = 3, 119 CPL_ERR_BAD_LENGTH = 15, 120 CPL_ERR_BAD_ROUTE = 18, 121 CPL_ERR_CONN_RESET = 20, 122 CPL_ERR_CONN_EXIST_SYNRECV = 21, 123 CPL_ERR_CONN_EXIST = 22, 124 CPL_ERR_ARP_MISS = 23, 125 CPL_ERR_BAD_SYN = 24, 126 CPL_ERR_CONN_TIMEDOUT = 30, 127 CPL_ERR_XMIT_TIMEDOUT = 31, 128 CPL_ERR_PERSIST_TIMEDOUT = 32, 129 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 130 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 131 CPL_ERR_RTX_NEG_ADVICE = 35, 132 CPL_ERR_PERSIST_NEG_ADVICE = 36, 133 CPL_ERR_KEEPALV_NEG_ADVICE = 37, 134 CPL_ERR_ABORT_FAILED = 42, 135 CPL_ERR_IWARP_FLM = 50, 136 }; 137 138 enum { 139 CPL_CONN_POLICY_AUTO = 0, 140 CPL_CONN_POLICY_ASK = 1, 141 CPL_CONN_POLICY_FILTER = 2, 142 CPL_CONN_POLICY_DENY = 3 143 }; 144 145 enum { 146 ULP_MODE_NONE = 0, 147 ULP_MODE_ISCSI = 2, 148 ULP_MODE_RDMA = 4, 149 ULP_MODE_TCPDDP = 5, 150 ULP_MODE_FCOE = 6, 151 }; 152 153 enum { 154 ULP_CRC_HEADER = 1 << 0, 155 ULP_CRC_DATA = 1 << 1 156 }; 157 158 enum { 159 CPL_ABORT_SEND_RST = 0, 160 CPL_ABORT_NO_RST, 161 }; 162 163 enum { /* TX_PKT_XT checksum types */ 164 TX_CSUM_TCP = 0, 165 TX_CSUM_UDP = 1, 166 TX_CSUM_CRC16 = 4, 167 TX_CSUM_CRC32 = 5, 168 TX_CSUM_CRC32C = 6, 169 TX_CSUM_FCOE = 7, 170 TX_CSUM_TCPIP = 8, 171 TX_CSUM_UDPIP = 9, 172 TX_CSUM_TCPIP6 = 10, 173 TX_CSUM_UDPIP6 = 11, 174 TX_CSUM_IP = 12, 175 }; 176 177 union opcode_tid { 178 __be32 opcode_tid; 179 u8 opcode; 180 }; 181 182 #define CPL_OPCODE_S 24 183 #define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S) 184 #define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF) 185 #define TID_G(x) ((x) & 0xFFFFFF) 186 187 /* tid is assumed to be 24-bits */ 188 #define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid)) 189 190 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 191 192 /* extract the TID from a CPL command */ 193 #define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd)))) 194 195 /* partitioning of TID fields that also carry a queue id */ 196 #define TID_TID_S 0 197 #define TID_TID_M 0x3fff 198 #define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M) 199 200 #define TID_QID_S 14 201 #define TID_QID_M 0x3ff 202 #define TID_QID_V(x) ((x) << TID_QID_S) 203 #define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M) 204 205 struct rss_header { 206 u8 opcode; 207 #if defined(__LITTLE_ENDIAN_BITFIELD) 208 u8 channel:2; 209 u8 filter_hit:1; 210 u8 filter_tid:1; 211 u8 hash_type:2; 212 u8 ipv6:1; 213 u8 send2fw:1; 214 #else 215 u8 send2fw:1; 216 u8 ipv6:1; 217 u8 hash_type:2; 218 u8 filter_tid:1; 219 u8 filter_hit:1; 220 u8 channel:2; 221 #endif 222 __be16 qid; 223 __be32 hash_val; 224 }; 225 226 struct work_request_hdr { 227 __be32 wr_hi; 228 __be32 wr_mid; 229 __be64 wr_lo; 230 }; 231 232 /* wr_hi fields */ 233 #define WR_OP_S 24 234 #define WR_OP_V(x) ((__u64)(x) << WR_OP_S) 235 236 #define WR_HDR struct work_request_hdr wr 237 238 /* option 0 fields */ 239 #define TX_CHAN_S 2 240 #define TX_CHAN_V(x) ((x) << TX_CHAN_S) 241 242 #define ULP_MODE_S 8 243 #define ULP_MODE_V(x) ((x) << ULP_MODE_S) 244 245 #define RCV_BUFSIZ_S 12 246 #define RCV_BUFSIZ_M 0x3FFU 247 #define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S) 248 249 #define SMAC_SEL_S 28 250 #define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S) 251 252 #define L2T_IDX_S 36 253 #define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S) 254 255 #define WND_SCALE_S 50 256 #define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S) 257 258 #define KEEP_ALIVE_S 54 259 #define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S) 260 #define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL) 261 262 #define MSS_IDX_S 60 263 #define MSS_IDX_M 0xF 264 #define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S) 265 #define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M) 266 267 /* option 2 fields */ 268 #define RSS_QUEUE_S 0 269 #define RSS_QUEUE_M 0x3FF 270 #define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S) 271 #define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M) 272 273 #define RSS_QUEUE_VALID_S 10 274 #define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S) 275 #define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U) 276 277 #define RX_FC_DISABLE_S 20 278 #define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S) 279 #define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U) 280 281 #define RX_FC_VALID_S 22 282 #define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S) 283 #define RX_FC_VALID_F RX_FC_VALID_V(1U) 284 285 #define RX_CHANNEL_S 26 286 #define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S) 287 288 #define WND_SCALE_EN_S 28 289 #define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S) 290 #define WND_SCALE_EN_F WND_SCALE_EN_V(1U) 291 292 #define T5_OPT_2_VALID_S 31 293 #define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S) 294 #define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U) 295 296 struct cpl_pass_open_req { 297 WR_HDR; 298 union opcode_tid ot; 299 __be16 local_port; 300 __be16 peer_port; 301 __be32 local_ip; 302 __be32 peer_ip; 303 __be64 opt0; 304 __be64 opt1; 305 }; 306 307 /* option 0 fields */ 308 #define NO_CONG_S 4 309 #define NO_CONG_V(x) ((x) << NO_CONG_S) 310 #define NO_CONG_F NO_CONG_V(1U) 311 312 #define DELACK_S 5 313 #define DELACK_V(x) ((x) << DELACK_S) 314 #define DELACK_F DELACK_V(1U) 315 316 #define DSCP_S 22 317 #define DSCP_M 0x3F 318 #define DSCP_V(x) ((x) << DSCP_S) 319 #define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M) 320 321 #define TCAM_BYPASS_S 48 322 #define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S) 323 #define TCAM_BYPASS_F TCAM_BYPASS_V(1ULL) 324 325 #define NAGLE_S 49 326 #define NAGLE_V(x) ((__u64)(x) << NAGLE_S) 327 #define NAGLE_F NAGLE_V(1ULL) 328 329 /* option 1 fields */ 330 #define SYN_RSS_ENABLE_S 0 331 #define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S) 332 #define SYN_RSS_ENABLE_F SYN_RSS_ENABLE_V(1U) 333 334 #define SYN_RSS_QUEUE_S 2 335 #define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S) 336 337 #define CONN_POLICY_S 22 338 #define CONN_POLICY_V(x) ((x) << CONN_POLICY_S) 339 340 struct cpl_pass_open_req6 { 341 WR_HDR; 342 union opcode_tid ot; 343 __be16 local_port; 344 __be16 peer_port; 345 __be64 local_ip_hi; 346 __be64 local_ip_lo; 347 __be64 peer_ip_hi; 348 __be64 peer_ip_lo; 349 __be64 opt0; 350 __be64 opt1; 351 }; 352 353 struct cpl_pass_open_rpl { 354 union opcode_tid ot; 355 u8 rsvd[3]; 356 u8 status; 357 }; 358 359 struct tcp_options { 360 __be16 mss; 361 __u8 wsf; 362 #if defined(__LITTLE_ENDIAN_BITFIELD) 363 __u8:4; 364 __u8 unknown:1; 365 __u8:1; 366 __u8 sack:1; 367 __u8 tstamp:1; 368 #else 369 __u8 tstamp:1; 370 __u8 sack:1; 371 __u8:1; 372 __u8 unknown:1; 373 __u8:4; 374 #endif 375 }; 376 377 struct cpl_pass_accept_req { 378 union opcode_tid ot; 379 __be16 rsvd; 380 __be16 len; 381 __be32 hdr_len; 382 __be16 vlan; 383 __be16 l2info; 384 __be32 tos_stid; 385 struct tcp_options tcpopt; 386 }; 387 388 /* cpl_pass_accept_req.hdr_len fields */ 389 #define SYN_RX_CHAN_S 0 390 #define SYN_RX_CHAN_M 0xF 391 #define SYN_RX_CHAN_V(x) ((x) << SYN_RX_CHAN_S) 392 #define SYN_RX_CHAN_G(x) (((x) >> SYN_RX_CHAN_S) & SYN_RX_CHAN_M) 393 394 #define TCP_HDR_LEN_S 10 395 #define TCP_HDR_LEN_M 0x3F 396 #define TCP_HDR_LEN_V(x) ((x) << TCP_HDR_LEN_S) 397 #define TCP_HDR_LEN_G(x) (((x) >> TCP_HDR_LEN_S) & TCP_HDR_LEN_M) 398 399 #define IP_HDR_LEN_S 16 400 #define IP_HDR_LEN_M 0x3FF 401 #define IP_HDR_LEN_V(x) ((x) << IP_HDR_LEN_S) 402 #define IP_HDR_LEN_G(x) (((x) >> IP_HDR_LEN_S) & IP_HDR_LEN_M) 403 404 #define ETH_HDR_LEN_S 26 405 #define ETH_HDR_LEN_M 0x1F 406 #define ETH_HDR_LEN_V(x) ((x) << ETH_HDR_LEN_S) 407 #define ETH_HDR_LEN_G(x) (((x) >> ETH_HDR_LEN_S) & ETH_HDR_LEN_M) 408 409 /* cpl_pass_accept_req.l2info fields */ 410 #define SYN_MAC_IDX_S 0 411 #define SYN_MAC_IDX_M 0x1FF 412 #define SYN_MAC_IDX_V(x) ((x) << SYN_MAC_IDX_S) 413 #define SYN_MAC_IDX_G(x) (((x) >> SYN_MAC_IDX_S) & SYN_MAC_IDX_M) 414 415 #define SYN_XACT_MATCH_S 9 416 #define SYN_XACT_MATCH_V(x) ((x) << SYN_XACT_MATCH_S) 417 #define SYN_XACT_MATCH_F SYN_XACT_MATCH_V(1U) 418 419 #define SYN_INTF_S 12 420 #define SYN_INTF_M 0xF 421 #define SYN_INTF_V(x) ((x) << SYN_INTF_S) 422 #define SYN_INTF_G(x) (((x) >> SYN_INTF_S) & SYN_INTF_M) 423 424 enum { /* TCP congestion control algorithms */ 425 CONG_ALG_RENO, 426 CONG_ALG_TAHOE, 427 CONG_ALG_NEWRENO, 428 CONG_ALG_HIGHSPEED 429 }; 430 431 #define CONG_CNTRL_S 14 432 #define CONG_CNTRL_M 0x3 433 #define CONG_CNTRL_V(x) ((x) << CONG_CNTRL_S) 434 #define CONG_CNTRL_G(x) (((x) >> CONG_CNTRL_S) & CONG_CNTRL_M) 435 436 #define T5_ISS_S 18 437 #define T5_ISS_V(x) ((x) << T5_ISS_S) 438 #define T5_ISS_F T5_ISS_V(1U) 439 440 struct cpl_pass_accept_rpl { 441 WR_HDR; 442 union opcode_tid ot; 443 __be32 opt2; 444 __be64 opt0; 445 }; 446 447 /* option 2 fields */ 448 #define RX_COALESCE_VALID_S 11 449 #define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S) 450 #define RX_COALESCE_VALID_F RX_COALESCE_VALID_V(1U) 451 452 #define RX_COALESCE_S 12 453 #define RX_COALESCE_V(x) ((x) << RX_COALESCE_S) 454 455 #define PACE_S 16 456 #define PACE_V(x) ((x) << PACE_S) 457 458 #define TX_QUEUE_S 23 459 #define TX_QUEUE_M 0x7 460 #define TX_QUEUE_V(x) ((x) << TX_QUEUE_S) 461 #define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M) 462 463 #define CCTRL_ECN_S 27 464 #define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S) 465 #define CCTRL_ECN_F CCTRL_ECN_V(1U) 466 467 #define TSTAMPS_EN_S 29 468 #define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S) 469 #define TSTAMPS_EN_F TSTAMPS_EN_V(1U) 470 471 #define SACK_EN_S 30 472 #define SACK_EN_V(x) ((x) << SACK_EN_S) 473 #define SACK_EN_F SACK_EN_V(1U) 474 475 struct cpl_t5_pass_accept_rpl { 476 WR_HDR; 477 union opcode_tid ot; 478 __be32 opt2; 479 __be64 opt0; 480 __be32 iss; 481 __be32 rsvd; 482 }; 483 484 struct cpl_act_open_req { 485 WR_HDR; 486 union opcode_tid ot; 487 __be16 local_port; 488 __be16 peer_port; 489 __be32 local_ip; 490 __be32 peer_ip; 491 __be64 opt0; 492 __be32 params; 493 __be32 opt2; 494 }; 495 496 #define FILTER_TUPLE_S 24 497 #define FILTER_TUPLE_M 0xFFFFFFFFFF 498 #define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S) 499 #define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M) 500 struct cpl_t5_act_open_req { 501 WR_HDR; 502 union opcode_tid ot; 503 __be16 local_port; 504 __be16 peer_port; 505 __be32 local_ip; 506 __be32 peer_ip; 507 __be64 opt0; 508 __be32 rsvd; 509 __be32 opt2; 510 __be64 params; 511 }; 512 513 struct cpl_t6_act_open_req { 514 WR_HDR; 515 union opcode_tid ot; 516 __be16 local_port; 517 __be16 peer_port; 518 __be32 local_ip; 519 __be32 peer_ip; 520 __be64 opt0; 521 __be32 rsvd; 522 __be32 opt2; 523 __be64 params; 524 __be32 rsvd2; 525 __be32 opt3; 526 }; 527 528 struct cpl_act_open_req6 { 529 WR_HDR; 530 union opcode_tid ot; 531 __be16 local_port; 532 __be16 peer_port; 533 __be64 local_ip_hi; 534 __be64 local_ip_lo; 535 __be64 peer_ip_hi; 536 __be64 peer_ip_lo; 537 __be64 opt0; 538 __be32 params; 539 __be32 opt2; 540 }; 541 542 struct cpl_t5_act_open_req6 { 543 WR_HDR; 544 union opcode_tid ot; 545 __be16 local_port; 546 __be16 peer_port; 547 __be64 local_ip_hi; 548 __be64 local_ip_lo; 549 __be64 peer_ip_hi; 550 __be64 peer_ip_lo; 551 __be64 opt0; 552 __be32 rsvd; 553 __be32 opt2; 554 __be64 params; 555 }; 556 557 struct cpl_t6_act_open_req6 { 558 WR_HDR; 559 union opcode_tid ot; 560 __be16 local_port; 561 __be16 peer_port; 562 __be64 local_ip_hi; 563 __be64 local_ip_lo; 564 __be64 peer_ip_hi; 565 __be64 peer_ip_lo; 566 __be64 opt0; 567 __be32 rsvd; 568 __be32 opt2; 569 __be64 params; 570 __be32 rsvd2; 571 __be32 opt3; 572 }; 573 574 struct cpl_act_open_rpl { 575 union opcode_tid ot; 576 __be32 atid_status; 577 }; 578 579 /* cpl_act_open_rpl.atid_status fields */ 580 #define AOPEN_STATUS_S 0 581 #define AOPEN_STATUS_M 0xFF 582 #define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M) 583 584 #define AOPEN_ATID_S 8 585 #define AOPEN_ATID_M 0xFFFFFF 586 #define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M) 587 588 struct cpl_pass_establish { 589 union opcode_tid ot; 590 __be32 rsvd; 591 __be32 tos_stid; 592 __be16 mac_idx; 593 __be16 tcp_opt; 594 __be32 snd_isn; 595 __be32 rcv_isn; 596 }; 597 598 /* cpl_pass_establish.tos_stid fields */ 599 #define PASS_OPEN_TID_S 0 600 #define PASS_OPEN_TID_M 0xFFFFFF 601 #define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S) 602 #define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M) 603 604 #define PASS_OPEN_TOS_S 24 605 #define PASS_OPEN_TOS_M 0xFF 606 #define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S) 607 #define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M) 608 609 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */ 610 #define TCPOPT_WSCALE_OK_S 5 611 #define TCPOPT_WSCALE_OK_M 0x1 612 #define TCPOPT_WSCALE_OK_G(x) \ 613 (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M) 614 615 #define TCPOPT_SACK_S 6 616 #define TCPOPT_SACK_M 0x1 617 #define TCPOPT_SACK_G(x) (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M) 618 619 #define TCPOPT_TSTAMP_S 7 620 #define TCPOPT_TSTAMP_M 0x1 621 #define TCPOPT_TSTAMP_G(x) (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M) 622 623 #define TCPOPT_SND_WSCALE_S 8 624 #define TCPOPT_SND_WSCALE_M 0xF 625 #define TCPOPT_SND_WSCALE_G(x) \ 626 (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M) 627 628 #define TCPOPT_MSS_S 12 629 #define TCPOPT_MSS_M 0xF 630 #define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M) 631 632 #define T6_TCP_HDR_LEN_S 8 633 #define T6_TCP_HDR_LEN_V(x) ((x) << T6_TCP_HDR_LEN_S) 634 #define T6_TCP_HDR_LEN_G(x) (((x) >> T6_TCP_HDR_LEN_S) & TCP_HDR_LEN_M) 635 636 #define T6_IP_HDR_LEN_S 14 637 #define T6_IP_HDR_LEN_V(x) ((x) << T6_IP_HDR_LEN_S) 638 #define T6_IP_HDR_LEN_G(x) (((x) >> T6_IP_HDR_LEN_S) & IP_HDR_LEN_M) 639 640 #define T6_ETH_HDR_LEN_S 24 641 #define T6_ETH_HDR_LEN_M 0xFF 642 #define T6_ETH_HDR_LEN_V(x) ((x) << T6_ETH_HDR_LEN_S) 643 #define T6_ETH_HDR_LEN_G(x) (((x) >> T6_ETH_HDR_LEN_S) & T6_ETH_HDR_LEN_M) 644 645 struct cpl_act_establish { 646 union opcode_tid ot; 647 __be32 rsvd; 648 __be32 tos_atid; 649 __be16 mac_idx; 650 __be16 tcp_opt; 651 __be32 snd_isn; 652 __be32 rcv_isn; 653 }; 654 655 struct cpl_get_tcb { 656 WR_HDR; 657 union opcode_tid ot; 658 __be16 reply_ctrl; 659 __be16 cookie; 660 }; 661 662 /* cpl_get_tcb.reply_ctrl fields */ 663 #define QUEUENO_S 0 664 #define QUEUENO_V(x) ((x) << QUEUENO_S) 665 666 #define REPLY_CHAN_S 14 667 #define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S) 668 #define REPLY_CHAN_F REPLY_CHAN_V(1U) 669 670 #define NO_REPLY_S 15 671 #define NO_REPLY_V(x) ((x) << NO_REPLY_S) 672 #define NO_REPLY_F NO_REPLY_V(1U) 673 674 struct cpl_set_tcb_field { 675 WR_HDR; 676 union opcode_tid ot; 677 __be16 reply_ctrl; 678 __be16 word_cookie; 679 __be64 mask; 680 __be64 val; 681 }; 682 683 /* cpl_set_tcb_field.word_cookie fields */ 684 #define TCB_WORD_S 0 685 #define TCB_WORD(x) ((x) << TCB_WORD_S) 686 687 #define TCB_COOKIE_S 5 688 #define TCB_COOKIE_M 0x7 689 #define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S) 690 #define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M) 691 692 struct cpl_set_tcb_rpl { 693 union opcode_tid ot; 694 __be16 rsvd; 695 u8 cookie; 696 u8 status; 697 __be64 oldval; 698 }; 699 700 struct cpl_close_con_req { 701 WR_HDR; 702 union opcode_tid ot; 703 __be32 rsvd; 704 }; 705 706 struct cpl_close_con_rpl { 707 union opcode_tid ot; 708 u8 rsvd[3]; 709 u8 status; 710 __be32 snd_nxt; 711 __be32 rcv_nxt; 712 }; 713 714 struct cpl_close_listsvr_req { 715 WR_HDR; 716 union opcode_tid ot; 717 __be16 reply_ctrl; 718 __be16 rsvd; 719 }; 720 721 /* additional cpl_close_listsvr_req.reply_ctrl field */ 722 #define LISTSVR_IPV6_S 14 723 #define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S) 724 #define LISTSVR_IPV6_F LISTSVR_IPV6_V(1U) 725 726 struct cpl_close_listsvr_rpl { 727 union opcode_tid ot; 728 u8 rsvd[3]; 729 u8 status; 730 }; 731 732 struct cpl_abort_req_rss { 733 union opcode_tid ot; 734 u8 rsvd[3]; 735 u8 status; 736 }; 737 738 struct cpl_abort_req { 739 WR_HDR; 740 union opcode_tid ot; 741 __be32 rsvd0; 742 u8 rsvd1; 743 u8 cmd; 744 u8 rsvd2[6]; 745 }; 746 747 struct cpl_abort_rpl_rss { 748 union opcode_tid ot; 749 u8 rsvd[3]; 750 u8 status; 751 }; 752 753 struct cpl_abort_rpl { 754 WR_HDR; 755 union opcode_tid ot; 756 __be32 rsvd0; 757 u8 rsvd1; 758 u8 cmd; 759 u8 rsvd2[6]; 760 }; 761 762 struct cpl_peer_close { 763 union opcode_tid ot; 764 __be32 rcv_nxt; 765 }; 766 767 struct cpl_tid_release { 768 WR_HDR; 769 union opcode_tid ot; 770 __be32 rsvd; 771 }; 772 773 struct cpl_tx_pkt_core { 774 __be32 ctrl0; 775 __be16 pack; 776 __be16 len; 777 __be64 ctrl1; 778 }; 779 780 struct cpl_tx_pkt { 781 WR_HDR; 782 struct cpl_tx_pkt_core c; 783 }; 784 785 #define cpl_tx_pkt_xt cpl_tx_pkt 786 787 /* cpl_tx_pkt_core.ctrl0 fields */ 788 #define TXPKT_VF_S 0 789 #define TXPKT_VF_V(x) ((x) << TXPKT_VF_S) 790 791 #define TXPKT_PF_S 8 792 #define TXPKT_PF_V(x) ((x) << TXPKT_PF_S) 793 794 #define TXPKT_VF_VLD_S 11 795 #define TXPKT_VF_VLD_V(x) ((x) << TXPKT_VF_VLD_S) 796 #define TXPKT_VF_VLD_F TXPKT_VF_VLD_V(1U) 797 798 #define TXPKT_OVLAN_IDX_S 12 799 #define TXPKT_OVLAN_IDX_V(x) ((x) << TXPKT_OVLAN_IDX_S) 800 801 #define TXPKT_T5_OVLAN_IDX_S 12 802 #define TXPKT_T5_OVLAN_IDX_V(x) ((x) << TXPKT_T5_OVLAN_IDX_S) 803 804 #define TXPKT_INTF_S 16 805 #define TXPKT_INTF_V(x) ((x) << TXPKT_INTF_S) 806 807 #define TXPKT_INS_OVLAN_S 21 808 #define TXPKT_INS_OVLAN_V(x) ((x) << TXPKT_INS_OVLAN_S) 809 #define TXPKT_INS_OVLAN_F TXPKT_INS_OVLAN_V(1U) 810 811 #define TXPKT_TSTAMP_S 23 812 #define TXPKT_TSTAMP_V(x) ((x) << TXPKT_TSTAMP_S) 813 #define TXPKT_TSTAMP_F TXPKT_TSTAMP_V(1ULL) 814 815 #define TXPKT_OPCODE_S 24 816 #define TXPKT_OPCODE_V(x) ((x) << TXPKT_OPCODE_S) 817 818 /* cpl_tx_pkt_core.ctrl1 fields */ 819 #define TXPKT_CSUM_END_S 12 820 #define TXPKT_CSUM_END_V(x) ((x) << TXPKT_CSUM_END_S) 821 822 #define TXPKT_CSUM_START_S 20 823 #define TXPKT_CSUM_START_V(x) ((x) << TXPKT_CSUM_START_S) 824 825 #define TXPKT_IPHDR_LEN_S 20 826 #define TXPKT_IPHDR_LEN_V(x) ((__u64)(x) << TXPKT_IPHDR_LEN_S) 827 828 #define TXPKT_CSUM_LOC_S 30 829 #define TXPKT_CSUM_LOC_V(x) ((__u64)(x) << TXPKT_CSUM_LOC_S) 830 831 #define TXPKT_ETHHDR_LEN_S 34 832 #define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S) 833 834 #define T6_TXPKT_ETHHDR_LEN_S 32 835 #define T6_TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << T6_TXPKT_ETHHDR_LEN_S) 836 837 #define TXPKT_CSUM_TYPE_S 40 838 #define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S) 839 840 #define TXPKT_VLAN_S 44 841 #define TXPKT_VLAN_V(x) ((__u64)(x) << TXPKT_VLAN_S) 842 843 #define TXPKT_VLAN_VLD_S 60 844 #define TXPKT_VLAN_VLD_V(x) ((__u64)(x) << TXPKT_VLAN_VLD_S) 845 #define TXPKT_VLAN_VLD_F TXPKT_VLAN_VLD_V(1ULL) 846 847 #define TXPKT_IPCSUM_DIS_S 62 848 #define TXPKT_IPCSUM_DIS_V(x) ((__u64)(x) << TXPKT_IPCSUM_DIS_S) 849 #define TXPKT_IPCSUM_DIS_F TXPKT_IPCSUM_DIS_V(1ULL) 850 851 #define TXPKT_L4CSUM_DIS_S 63 852 #define TXPKT_L4CSUM_DIS_V(x) ((__u64)(x) << TXPKT_L4CSUM_DIS_S) 853 #define TXPKT_L4CSUM_DIS_F TXPKT_L4CSUM_DIS_V(1ULL) 854 855 struct cpl_tx_pkt_lso_core { 856 __be32 lso_ctrl; 857 __be16 ipid_ofst; 858 __be16 mss; 859 __be32 seqno_offset; 860 __be32 len; 861 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 862 }; 863 864 /* cpl_tx_pkt_lso_core.lso_ctrl fields */ 865 #define LSO_TCPHDR_LEN_S 0 866 #define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S) 867 868 #define LSO_IPHDR_LEN_S 4 869 #define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S) 870 871 #define LSO_ETHHDR_LEN_S 16 872 #define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S) 873 874 #define LSO_IPV6_S 20 875 #define LSO_IPV6_V(x) ((x) << LSO_IPV6_S) 876 #define LSO_IPV6_F LSO_IPV6_V(1U) 877 878 #define LSO_LAST_SLICE_S 22 879 #define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S) 880 #define LSO_LAST_SLICE_F LSO_LAST_SLICE_V(1U) 881 882 #define LSO_FIRST_SLICE_S 23 883 #define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S) 884 #define LSO_FIRST_SLICE_F LSO_FIRST_SLICE_V(1U) 885 886 #define LSO_OPCODE_S 24 887 #define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S) 888 889 #define LSO_T5_XFER_SIZE_S 0 890 #define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S) 891 892 struct cpl_tx_pkt_lso { 893 WR_HDR; 894 struct cpl_tx_pkt_lso_core c; 895 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */ 896 }; 897 898 struct cpl_iscsi_hdr { 899 union opcode_tid ot; 900 __be16 pdu_len_ddp; 901 __be16 len; 902 __be32 seq; 903 __be16 urg; 904 u8 rsvd; 905 u8 status; 906 }; 907 908 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 909 #define ISCSI_PDU_LEN_S 0 910 #define ISCSI_PDU_LEN_M 0x7FFF 911 #define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S) 912 #define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M) 913 914 #define ISCSI_DDP_S 15 915 #define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S) 916 #define ISCSI_DDP_F ISCSI_DDP_V(1U) 917 918 struct cpl_rx_data_ddp { 919 union opcode_tid ot; 920 __be16 urg; 921 __be16 len; 922 __be32 seq; 923 union { 924 __be32 nxt_seq; 925 __be32 ddp_report; 926 }; 927 __be32 ulp_crc; 928 __be32 ddpvld; 929 }; 930 931 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp 932 933 struct cpl_iscsi_data { 934 union opcode_tid ot; 935 __u8 rsvd0[2]; 936 __be16 len; 937 __be32 seq; 938 __be16 urg; 939 __u8 rsvd1; 940 __u8 status; 941 }; 942 943 struct cpl_rx_iscsi_cmp { 944 union opcode_tid ot; 945 __be16 pdu_len_ddp; 946 __be16 len; 947 __be32 seq; 948 __be16 urg; 949 __u8 rsvd; 950 __u8 status; 951 __be32 ulp_crc; 952 __be32 ddpvld; 953 }; 954 955 struct cpl_tx_data_iso { 956 __be32 op_to_scsi; 957 __u8 reserved1; 958 __u8 ahs_len; 959 __be16 mpdu; 960 __be32 burst_size; 961 __be32 len; 962 __be32 reserved2_seglen_offset; 963 __be32 datasn_offset; 964 __be32 buffer_offset; 965 __be32 reserved3; 966 967 /* encapsulated CPL_TX_DATA follows here */ 968 }; 969 970 /* cpl_tx_data_iso.op_to_scsi fields */ 971 #define CPL_TX_DATA_ISO_OP_S 24 972 #define CPL_TX_DATA_ISO_OP_M 0xff 973 #define CPL_TX_DATA_ISO_OP_V(x) ((x) << CPL_TX_DATA_ISO_OP_S) 974 #define CPL_TX_DATA_ISO_OP_G(x) \ 975 (((x) >> CPL_TX_DATA_ISO_OP_S) & CPL_TX_DATA_ISO_OP_M) 976 977 #define CPL_TX_DATA_ISO_FIRST_S 23 978 #define CPL_TX_DATA_ISO_FIRST_M 0x1 979 #define CPL_TX_DATA_ISO_FIRST_V(x) ((x) << CPL_TX_DATA_ISO_FIRST_S) 980 #define CPL_TX_DATA_ISO_FIRST_G(x) \ 981 (((x) >> CPL_TX_DATA_ISO_FIRST_S) & CPL_TX_DATA_ISO_FIRST_M) 982 #define CPL_TX_DATA_ISO_FIRST_F CPL_TX_DATA_ISO_FIRST_V(1U) 983 984 #define CPL_TX_DATA_ISO_LAST_S 22 985 #define CPL_TX_DATA_ISO_LAST_M 0x1 986 #define CPL_TX_DATA_ISO_LAST_V(x) ((x) << CPL_TX_DATA_ISO_LAST_S) 987 #define CPL_TX_DATA_ISO_LAST_G(x) \ 988 (((x) >> CPL_TX_DATA_ISO_LAST_S) & CPL_TX_DATA_ISO_LAST_M) 989 #define CPL_TX_DATA_ISO_LAST_F CPL_TX_DATA_ISO_LAST_V(1U) 990 991 #define CPL_TX_DATA_ISO_CPLHDRLEN_S 21 992 #define CPL_TX_DATA_ISO_CPLHDRLEN_M 0x1 993 #define CPL_TX_DATA_ISO_CPLHDRLEN_V(x) ((x) << CPL_TX_DATA_ISO_CPLHDRLEN_S) 994 #define CPL_TX_DATA_ISO_CPLHDRLEN_G(x) \ 995 (((x) >> CPL_TX_DATA_ISO_CPLHDRLEN_S) & CPL_TX_DATA_ISO_CPLHDRLEN_M) 996 #define CPL_TX_DATA_ISO_CPLHDRLEN_F CPL_TX_DATA_ISO_CPLHDRLEN_V(1U) 997 998 #define CPL_TX_DATA_ISO_HDRCRC_S 20 999 #define CPL_TX_DATA_ISO_HDRCRC_M 0x1 1000 #define CPL_TX_DATA_ISO_HDRCRC_V(x) ((x) << CPL_TX_DATA_ISO_HDRCRC_S) 1001 #define CPL_TX_DATA_ISO_HDRCRC_G(x) \ 1002 (((x) >> CPL_TX_DATA_ISO_HDRCRC_S) & CPL_TX_DATA_ISO_HDRCRC_M) 1003 #define CPL_TX_DATA_ISO_HDRCRC_F CPL_TX_DATA_ISO_HDRCRC_V(1U) 1004 1005 #define CPL_TX_DATA_ISO_PLDCRC_S 19 1006 #define CPL_TX_DATA_ISO_PLDCRC_M 0x1 1007 #define CPL_TX_DATA_ISO_PLDCRC_V(x) ((x) << CPL_TX_DATA_ISO_PLDCRC_S) 1008 #define CPL_TX_DATA_ISO_PLDCRC_G(x) \ 1009 (((x) >> CPL_TX_DATA_ISO_PLDCRC_S) & CPL_TX_DATA_ISO_PLDCRC_M) 1010 #define CPL_TX_DATA_ISO_PLDCRC_F CPL_TX_DATA_ISO_PLDCRC_V(1U) 1011 1012 #define CPL_TX_DATA_ISO_IMMEDIATE_S 18 1013 #define CPL_TX_DATA_ISO_IMMEDIATE_M 0x1 1014 #define CPL_TX_DATA_ISO_IMMEDIATE_V(x) ((x) << CPL_TX_DATA_ISO_IMMEDIATE_S) 1015 #define CPL_TX_DATA_ISO_IMMEDIATE_G(x) \ 1016 (((x) >> CPL_TX_DATA_ISO_IMMEDIATE_S) & CPL_TX_DATA_ISO_IMMEDIATE_M) 1017 #define CPL_TX_DATA_ISO_IMMEDIATE_F CPL_TX_DATA_ISO_IMMEDIATE_V(1U) 1018 1019 #define CPL_TX_DATA_ISO_SCSI_S 16 1020 #define CPL_TX_DATA_ISO_SCSI_M 0x3 1021 #define CPL_TX_DATA_ISO_SCSI_V(x) ((x) << CPL_TX_DATA_ISO_SCSI_S) 1022 #define CPL_TX_DATA_ISO_SCSI_G(x) \ 1023 (((x) >> CPL_TX_DATA_ISO_SCSI_S) & CPL_TX_DATA_ISO_SCSI_M) 1024 1025 /* cpl_tx_data_iso.reserved2_seglen_offset fields */ 1026 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_S 0 1027 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_M 0xffffff 1028 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_V(x) \ 1029 ((x) << CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) 1030 #define CPL_TX_DATA_ISO_SEGLEN_OFFSET_G(x) \ 1031 (((x) >> CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) & \ 1032 CPL_TX_DATA_ISO_SEGLEN_OFFSET_M) 1033 1034 struct cpl_rx_data { 1035 union opcode_tid ot; 1036 __be16 rsvd; 1037 __be16 len; 1038 __be32 seq; 1039 __be16 urg; 1040 #if defined(__LITTLE_ENDIAN_BITFIELD) 1041 u8 dack_mode:2; 1042 u8 psh:1; 1043 u8 heartbeat:1; 1044 u8 ddp_off:1; 1045 u8 :3; 1046 #else 1047 u8 :3; 1048 u8 ddp_off:1; 1049 u8 heartbeat:1; 1050 u8 psh:1; 1051 u8 dack_mode:2; 1052 #endif 1053 u8 status; 1054 }; 1055 1056 struct cpl_rx_data_ack { 1057 WR_HDR; 1058 union opcode_tid ot; 1059 __be32 credit_dack; 1060 }; 1061 1062 /* cpl_rx_data_ack.ack_seq fields */ 1063 #define RX_CREDITS_S 0 1064 #define RX_CREDITS_V(x) ((x) << RX_CREDITS_S) 1065 1066 #define RX_FORCE_ACK_S 28 1067 #define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S) 1068 #define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U) 1069 1070 #define RX_DACK_MODE_S 29 1071 #define RX_DACK_MODE_M 0x3 1072 #define RX_DACK_MODE_V(x) ((x) << RX_DACK_MODE_S) 1073 #define RX_DACK_MODE_G(x) (((x) >> RX_DACK_MODE_S) & RX_DACK_MODE_M) 1074 1075 #define RX_DACK_CHANGE_S 31 1076 #define RX_DACK_CHANGE_V(x) ((x) << RX_DACK_CHANGE_S) 1077 #define RX_DACK_CHANGE_F RX_DACK_CHANGE_V(1U) 1078 1079 struct cpl_rx_pkt { 1080 struct rss_header rsshdr; 1081 u8 opcode; 1082 #if defined(__LITTLE_ENDIAN_BITFIELD) 1083 u8 iff:4; 1084 u8 csum_calc:1; 1085 u8 ipmi_pkt:1; 1086 u8 vlan_ex:1; 1087 u8 ip_frag:1; 1088 #else 1089 u8 ip_frag:1; 1090 u8 vlan_ex:1; 1091 u8 ipmi_pkt:1; 1092 u8 csum_calc:1; 1093 u8 iff:4; 1094 #endif 1095 __be16 csum; 1096 __be16 vlan; 1097 __be16 len; 1098 __be32 l2info; 1099 __be16 hdr_len; 1100 __be16 err_vec; 1101 }; 1102 1103 #define RX_T6_ETHHDR_LEN_M 0xFF 1104 #define RX_T6_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_T6_ETHHDR_LEN_M) 1105 1106 #define RXF_PSH_S 20 1107 #define RXF_PSH_V(x) ((x) << RXF_PSH_S) 1108 #define RXF_PSH_F RXF_PSH_V(1U) 1109 1110 #define RXF_SYN_S 21 1111 #define RXF_SYN_V(x) ((x) << RXF_SYN_S) 1112 #define RXF_SYN_F RXF_SYN_V(1U) 1113 1114 #define RXF_UDP_S 22 1115 #define RXF_UDP_V(x) ((x) << RXF_UDP_S) 1116 #define RXF_UDP_F RXF_UDP_V(1U) 1117 1118 #define RXF_TCP_S 23 1119 #define RXF_TCP_V(x) ((x) << RXF_TCP_S) 1120 #define RXF_TCP_F RXF_TCP_V(1U) 1121 1122 #define RXF_IP_S 24 1123 #define RXF_IP_V(x) ((x) << RXF_IP_S) 1124 #define RXF_IP_F RXF_IP_V(1U) 1125 1126 #define RXF_IP6_S 25 1127 #define RXF_IP6_V(x) ((x) << RXF_IP6_S) 1128 #define RXF_IP6_F RXF_IP6_V(1U) 1129 1130 #define RXF_SYN_COOKIE_S 26 1131 #define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S) 1132 #define RXF_SYN_COOKIE_F RXF_SYN_COOKIE_V(1U) 1133 1134 #define RXF_FCOE_S 26 1135 #define RXF_FCOE_V(x) ((x) << RXF_FCOE_S) 1136 #define RXF_FCOE_F RXF_FCOE_V(1U) 1137 1138 #define RXF_LRO_S 27 1139 #define RXF_LRO_V(x) ((x) << RXF_LRO_S) 1140 #define RXF_LRO_F RXF_LRO_V(1U) 1141 1142 /* rx_pkt.l2info fields */ 1143 #define RX_ETHHDR_LEN_S 0 1144 #define RX_ETHHDR_LEN_M 0x1F 1145 #define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S) 1146 #define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M) 1147 1148 #define RX_T5_ETHHDR_LEN_S 0 1149 #define RX_T5_ETHHDR_LEN_M 0x3F 1150 #define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S) 1151 #define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M) 1152 1153 #define RX_MACIDX_S 8 1154 #define RX_MACIDX_M 0x1FF 1155 #define RX_MACIDX_V(x) ((x) << RX_MACIDX_S) 1156 #define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M) 1157 1158 #define RXF_SYN_S 21 1159 #define RXF_SYN_V(x) ((x) << RXF_SYN_S) 1160 #define RXF_SYN_F RXF_SYN_V(1U) 1161 1162 #define RX_CHAN_S 28 1163 #define RX_CHAN_M 0xF 1164 #define RX_CHAN_V(x) ((x) << RX_CHAN_S) 1165 #define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M) 1166 1167 /* rx_pkt.hdr_len fields */ 1168 #define RX_TCPHDR_LEN_S 0 1169 #define RX_TCPHDR_LEN_M 0x3F 1170 #define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S) 1171 #define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M) 1172 1173 #define RX_IPHDR_LEN_S 6 1174 #define RX_IPHDR_LEN_M 0x3FF 1175 #define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S) 1176 #define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M) 1177 1178 /* rx_pkt.err_vec fields */ 1179 #define RXERR_CSUM_S 13 1180 #define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S) 1181 #define RXERR_CSUM_F RXERR_CSUM_V(1U) 1182 1183 #define T6_COMPR_RXERR_LEN_S 1 1184 #define T6_COMPR_RXERR_LEN_V(x) ((x) << T6_COMPR_RXERR_LEN_S) 1185 #define T6_COMPR_RXERR_LEN_F T6_COMPR_RXERR_LEN_V(1U) 1186 1187 #define T6_COMPR_RXERR_VEC_S 0 1188 #define T6_COMPR_RXERR_VEC_M 0x3F 1189 #define T6_COMPR_RXERR_VEC_V(x) ((x) << T6_COMPR_RXERR_LEN_S) 1190 #define T6_COMPR_RXERR_VEC_G(x) \ 1191 (((x) >> T6_COMPR_RXERR_VEC_S) & T6_COMPR_RXERR_VEC_M) 1192 1193 /* Logical OR of RX_ERROR_CSUM, RX_ERROR_CSIP */ 1194 #define T6_COMPR_RXERR_SUM_S 4 1195 #define T6_COMPR_RXERR_SUM_V(x) ((x) << T6_COMPR_RXERR_SUM_S) 1196 #define T6_COMPR_RXERR_SUM_F T6_COMPR_RXERR_SUM_V(1U) 1197 1198 struct cpl_trace_pkt { 1199 u8 opcode; 1200 u8 intf; 1201 #if defined(__LITTLE_ENDIAN_BITFIELD) 1202 u8 runt:4; 1203 u8 filter_hit:4; 1204 u8 :6; 1205 u8 err:1; 1206 u8 trunc:1; 1207 #else 1208 u8 filter_hit:4; 1209 u8 runt:4; 1210 u8 trunc:1; 1211 u8 err:1; 1212 u8 :6; 1213 #endif 1214 __be16 rsvd; 1215 __be16 len; 1216 __be64 tstamp; 1217 }; 1218 1219 struct cpl_t5_trace_pkt { 1220 __u8 opcode; 1221 __u8 intf; 1222 #if defined(__LITTLE_ENDIAN_BITFIELD) 1223 __u8 runt:4; 1224 __u8 filter_hit:4; 1225 __u8:6; 1226 __u8 err:1; 1227 __u8 trunc:1; 1228 #else 1229 __u8 filter_hit:4; 1230 __u8 runt:4; 1231 __u8 trunc:1; 1232 __u8 err:1; 1233 __u8:6; 1234 #endif 1235 __be16 rsvd; 1236 __be16 len; 1237 __be64 tstamp; 1238 __be64 rsvd1; 1239 }; 1240 1241 struct cpl_l2t_write_req { 1242 WR_HDR; 1243 union opcode_tid ot; 1244 __be16 params; 1245 __be16 l2t_idx; 1246 __be16 vlan; 1247 u8 dst_mac[6]; 1248 }; 1249 1250 /* cpl_l2t_write_req.params fields */ 1251 #define L2T_W_INFO_S 2 1252 #define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S) 1253 1254 #define L2T_W_PORT_S 8 1255 #define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S) 1256 1257 #define L2T_W_NOREPLY_S 15 1258 #define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S) 1259 #define L2T_W_NOREPLY_F L2T_W_NOREPLY_V(1U) 1260 1261 #define CPL_L2T_VLAN_NONE 0xfff 1262 1263 struct cpl_l2t_write_rpl { 1264 union opcode_tid ot; 1265 u8 status; 1266 u8 rsvd[3]; 1267 }; 1268 1269 struct cpl_rdma_terminate { 1270 union opcode_tid ot; 1271 __be16 rsvd; 1272 __be16 len; 1273 }; 1274 1275 struct cpl_sge_egr_update { 1276 __be32 opcode_qid; 1277 __be16 cidx; 1278 __be16 pidx; 1279 }; 1280 1281 /* cpl_sge_egr_update.ot fields */ 1282 #define EGR_QID_S 0 1283 #define EGR_QID_M 0x1FFFF 1284 #define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M) 1285 1286 /* cpl_fw*.type values */ 1287 enum { 1288 FW_TYPE_CMD_RPL = 0, 1289 FW_TYPE_WR_RPL = 1, 1290 FW_TYPE_CQE = 2, 1291 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3, 1292 FW_TYPE_RSSCPL = 4, 1293 }; 1294 1295 struct cpl_fw4_pld { 1296 u8 opcode; 1297 u8 rsvd0[3]; 1298 u8 type; 1299 u8 rsvd1; 1300 __be16 len; 1301 __be64 data; 1302 __be64 rsvd2; 1303 }; 1304 1305 struct cpl_fw6_pld { 1306 u8 opcode; 1307 u8 rsvd[5]; 1308 __be16 len; 1309 __be64 data[4]; 1310 }; 1311 1312 struct cpl_fw4_msg { 1313 u8 opcode; 1314 u8 type; 1315 __be16 rsvd0; 1316 __be32 rsvd1; 1317 __be64 data[2]; 1318 }; 1319 1320 struct cpl_fw4_ack { 1321 union opcode_tid ot; 1322 u8 credits; 1323 u8 rsvd0[2]; 1324 u8 seq_vld; 1325 __be32 snd_nxt; 1326 __be32 snd_una; 1327 __be64 rsvd1; 1328 }; 1329 1330 enum { 1331 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */ 1332 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */ 1333 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */ 1334 }; 1335 1336 struct cpl_fw6_msg { 1337 u8 opcode; 1338 u8 type; 1339 __be16 rsvd0; 1340 __be32 rsvd1; 1341 __be64 data[4]; 1342 }; 1343 1344 /* cpl_fw6_msg.type values */ 1345 enum { 1346 FW6_TYPE_CMD_RPL = 0, 1347 FW6_TYPE_WR_RPL = 1, 1348 FW6_TYPE_CQE = 2, 1349 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3, 1350 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL, 1351 }; 1352 1353 struct cpl_fw6_msg_ofld_connection_wr_rpl { 1354 __u64 cookie; 1355 __be32 tid; /* or atid in case of active failure */ 1356 __u8 t_state; 1357 __u8 retval; 1358 __u8 rsvd[2]; 1359 }; 1360 1361 struct cpl_tx_data { 1362 union opcode_tid ot; 1363 __be32 len; 1364 __be32 rsvd; 1365 __be32 flags; 1366 }; 1367 1368 /* cpl_tx_data.flags field */ 1369 #define TX_FORCE_S 13 1370 #define TX_FORCE_V(x) ((x) << TX_FORCE_S) 1371 1372 #define T6_TX_FORCE_S 20 1373 #define T6_TX_FORCE_V(x) ((x) << T6_TX_FORCE_S) 1374 #define T6_TX_FORCE_F T6_TX_FORCE_V(1U) 1375 1376 enum { 1377 ULP_TX_MEM_READ = 2, 1378 ULP_TX_MEM_WRITE = 3, 1379 ULP_TX_PKT = 4 1380 }; 1381 1382 enum { 1383 ULP_TX_SC_NOOP = 0x80, 1384 ULP_TX_SC_IMM = 0x81, 1385 ULP_TX_SC_DSGL = 0x82, 1386 ULP_TX_SC_ISGL = 0x83 1387 }; 1388 1389 #define ULPTX_CMD_S 24 1390 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S) 1391 1392 struct ulptx_sge_pair { 1393 __be32 len[2]; 1394 __be64 addr[2]; 1395 }; 1396 1397 struct ulptx_sgl { 1398 __be32 cmd_nsge; 1399 __be32 len0; 1400 __be64 addr0; 1401 struct ulptx_sge_pair sge[0]; 1402 }; 1403 1404 struct ulptx_idata { 1405 __be32 cmd_more; 1406 __be32 len; 1407 }; 1408 1409 struct ulp_txpkt { 1410 __be32 cmd_dest; 1411 __be32 len; 1412 }; 1413 1414 #define ULPTX_CMD_S 24 1415 #define ULPTX_CMD_M 0xFF 1416 #define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S) 1417 1418 #define ULPTX_NSGE_S 0 1419 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S) 1420 1421 #define ULPTX_MORE_S 23 1422 #define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S) 1423 #define ULPTX_MORE_F ULPTX_MORE_V(1U) 1424 1425 #define ULP_TXPKT_DEST_S 16 1426 #define ULP_TXPKT_DEST_M 0x3 1427 #define ULP_TXPKT_DEST_V(x) ((x) << ULP_TXPKT_DEST_S) 1428 1429 #define ULP_TXPKT_FID_S 4 1430 #define ULP_TXPKT_FID_M 0x7ff 1431 #define ULP_TXPKT_FID_V(x) ((x) << ULP_TXPKT_FID_S) 1432 1433 #define ULP_TXPKT_RO_S 3 1434 #define ULP_TXPKT_RO_V(x) ((x) << ULP_TXPKT_RO_S) 1435 #define ULP_TXPKT_RO_F ULP_TXPKT_RO_V(1U) 1436 1437 #define ULP_TX_SC_MORE_S 23 1438 #define ULP_TX_SC_MORE_V(x) ((x) << ULP_TX_SC_MORE_S) 1439 #define ULP_TX_SC_MORE_F ULP_TX_SC_MORE_V(1U) 1440 1441 struct ulp_mem_io { 1442 WR_HDR; 1443 __be32 cmd; 1444 __be32 len16; /* command length */ 1445 __be32 dlen; /* data length in 32-byte units */ 1446 __be32 lock_addr; 1447 }; 1448 1449 #define ULP_MEMIO_LOCK_S 31 1450 #define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S) 1451 #define ULP_MEMIO_LOCK_F ULP_MEMIO_LOCK_V(1U) 1452 1453 /* additional ulp_mem_io.cmd fields */ 1454 #define ULP_MEMIO_ORDER_S 23 1455 #define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S) 1456 #define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U) 1457 1458 #define T5_ULP_MEMIO_IMM_S 23 1459 #define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S) 1460 #define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U) 1461 1462 #define T5_ULP_MEMIO_ORDER_S 22 1463 #define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S) 1464 #define T5_ULP_MEMIO_ORDER_F T5_ULP_MEMIO_ORDER_V(1U) 1465 1466 #define T5_ULP_MEMIO_FID_S 4 1467 #define T5_ULP_MEMIO_FID_M 0x7ff 1468 #define T5_ULP_MEMIO_FID_V(x) ((x) << T5_ULP_MEMIO_FID_S) 1469 1470 /* ulp_mem_io.lock_addr fields */ 1471 #define ULP_MEMIO_ADDR_S 0 1472 #define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S) 1473 1474 /* ulp_mem_io.dlen fields */ 1475 #define ULP_MEMIO_DATA_LEN_S 0 1476 #define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S) 1477 1478 #define ULPTX_NSGE_S 0 1479 #define ULPTX_NSGE_M 0xFFFF 1480 #define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S) 1481 #define ULPTX_NSGE_G(x) (((x) >> ULPTX_NSGE_S) & ULPTX_NSGE_M) 1482 1483 struct ulptx_sc_memrd { 1484 __be32 cmd_to_len; 1485 __be32 addr; 1486 }; 1487 1488 #define ULP_TXPKT_DATAMODIFY_S 23 1489 #define ULP_TXPKT_DATAMODIFY_M 0x1 1490 #define ULP_TXPKT_DATAMODIFY_V(x) ((x) << ULP_TXPKT_DATAMODIFY_S) 1491 #define ULP_TXPKT_DATAMODIFY_G(x) \ 1492 (((x) >> ULP_TXPKT_DATAMODIFY_S) & ULP_TXPKT_DATAMODIFY__M) 1493 #define ULP_TXPKT_DATAMODIFY_F ULP_TXPKT_DATAMODIFY_V(1U) 1494 1495 #define ULP_TXPKT_CHANNELID_S 22 1496 #define ULP_TXPKT_CHANNELID_M 0x1 1497 #define ULP_TXPKT_CHANNELID_V(x) ((x) << ULP_TXPKT_CHANNELID_S) 1498 #define ULP_TXPKT_CHANNELID_G(x) \ 1499 (((x) >> ULP_TXPKT_CHANNELID_S) & ULP_TXPKT_CHANNELID_M) 1500 #define ULP_TXPKT_CHANNELID_F ULP_TXPKT_CHANNELID_V(1U) 1501 1502 #define SCMD_SEQ_NO_CTRL_S 29 1503 #define SCMD_SEQ_NO_CTRL_M 0x3 1504 #define SCMD_SEQ_NO_CTRL_V(x) ((x) << SCMD_SEQ_NO_CTRL_S) 1505 #define SCMD_SEQ_NO_CTRL_G(x) \ 1506 (((x) >> SCMD_SEQ_NO_CTRL_S) & SCMD_SEQ_NO_CTRL_M) 1507 1508 /* StsFieldPrsnt- Status field at the end of the TLS PDU */ 1509 #define SCMD_STATUS_PRESENT_S 28 1510 #define SCMD_STATUS_PRESENT_M 0x1 1511 #define SCMD_STATUS_PRESENT_V(x) ((x) << SCMD_STATUS_PRESENT_S) 1512 #define SCMD_STATUS_PRESENT_G(x) \ 1513 (((x) >> SCMD_STATUS_PRESENT_S) & SCMD_STATUS_PRESENT_M) 1514 #define SCMD_STATUS_PRESENT_F SCMD_STATUS_PRESENT_V(1U) 1515 1516 /* ProtoVersion - Protocol Version 0: 1.2, 1:1.1, 2:DTLS, 3:Generic, 1517 * 3-15: Reserved. 1518 */ 1519 #define SCMD_PROTO_VERSION_S 24 1520 #define SCMD_PROTO_VERSION_M 0xf 1521 #define SCMD_PROTO_VERSION_V(x) ((x) << SCMD_PROTO_VERSION_S) 1522 #define SCMD_PROTO_VERSION_G(x) \ 1523 (((x) >> SCMD_PROTO_VERSION_S) & SCMD_PROTO_VERSION_M) 1524 1525 /* EncDecCtrl - Encryption/Decryption Control. 0: Encrypt, 1: Decrypt */ 1526 #define SCMD_ENC_DEC_CTRL_S 23 1527 #define SCMD_ENC_DEC_CTRL_M 0x1 1528 #define SCMD_ENC_DEC_CTRL_V(x) ((x) << SCMD_ENC_DEC_CTRL_S) 1529 #define SCMD_ENC_DEC_CTRL_G(x) \ 1530 (((x) >> SCMD_ENC_DEC_CTRL_S) & SCMD_ENC_DEC_CTRL_M) 1531 #define SCMD_ENC_DEC_CTRL_F SCMD_ENC_DEC_CTRL_V(1U) 1532 1533 /* CipherAuthSeqCtrl - Cipher Authentication Sequence Control. */ 1534 #define SCMD_CIPH_AUTH_SEQ_CTRL_S 22 1535 #define SCMD_CIPH_AUTH_SEQ_CTRL_M 0x1 1536 #define SCMD_CIPH_AUTH_SEQ_CTRL_V(x) \ 1537 ((x) << SCMD_CIPH_AUTH_SEQ_CTRL_S) 1538 #define SCMD_CIPH_AUTH_SEQ_CTRL_G(x) \ 1539 (((x) >> SCMD_CIPH_AUTH_SEQ_CTRL_S) & SCMD_CIPH_AUTH_SEQ_CTRL_M) 1540 #define SCMD_CIPH_AUTH_SEQ_CTRL_F SCMD_CIPH_AUTH_SEQ_CTRL_V(1U) 1541 1542 /* CiphMode - Cipher Mode. 0: NOP, 1:AES-CBC, 2:AES-GCM, 3:AES-CTR, 1543 * 4:Generic-AES, 5-15: Reserved. 1544 */ 1545 #define SCMD_CIPH_MODE_S 18 1546 #define SCMD_CIPH_MODE_M 0xf 1547 #define SCMD_CIPH_MODE_V(x) ((x) << SCMD_CIPH_MODE_S) 1548 #define SCMD_CIPH_MODE_G(x) \ 1549 (((x) >> SCMD_CIPH_MODE_S) & SCMD_CIPH_MODE_M) 1550 1551 /* AuthMode - Auth Mode. 0: NOP, 1:SHA1, 2:SHA2-224, 3:SHA2-256 1552 * 4-15: Reserved 1553 */ 1554 #define SCMD_AUTH_MODE_S 14 1555 #define SCMD_AUTH_MODE_M 0xf 1556 #define SCMD_AUTH_MODE_V(x) ((x) << SCMD_AUTH_MODE_S) 1557 #define SCMD_AUTH_MODE_G(x) \ 1558 (((x) >> SCMD_AUTH_MODE_S) & SCMD_AUTH_MODE_M) 1559 1560 /* HmacCtrl - HMAC Control. 0:NOP, 1:No truncation, 2:Support HMAC Truncation 1561 * per RFC 4366, 3:IPSec 96 bits, 4-7:Reserved 1562 */ 1563 #define SCMD_HMAC_CTRL_S 11 1564 #define SCMD_HMAC_CTRL_M 0x7 1565 #define SCMD_HMAC_CTRL_V(x) ((x) << SCMD_HMAC_CTRL_S) 1566 #define SCMD_HMAC_CTRL_G(x) \ 1567 (((x) >> SCMD_HMAC_CTRL_S) & SCMD_HMAC_CTRL_M) 1568 1569 /* IvSize - IV size in units of 2 bytes */ 1570 #define SCMD_IV_SIZE_S 7 1571 #define SCMD_IV_SIZE_M 0xf 1572 #define SCMD_IV_SIZE_V(x) ((x) << SCMD_IV_SIZE_S) 1573 #define SCMD_IV_SIZE_G(x) \ 1574 (((x) >> SCMD_IV_SIZE_S) & SCMD_IV_SIZE_M) 1575 1576 /* NumIVs - Number of IVs */ 1577 #define SCMD_NUM_IVS_S 0 1578 #define SCMD_NUM_IVS_M 0x7f 1579 #define SCMD_NUM_IVS_V(x) ((x) << SCMD_NUM_IVS_S) 1580 #define SCMD_NUM_IVS_G(x) \ 1581 (((x) >> SCMD_NUM_IVS_S) & SCMD_NUM_IVS_M) 1582 1583 /* EnbDbgId - If this is enabled upper 20 (63:44) bits if SeqNumber 1584 * (below) are used as Cid (connection id for debug status), these 1585 * bits are padded to zero for forming the 64 bit 1586 * sequence number for TLS 1587 */ 1588 #define SCMD_ENB_DBGID_S 31 1589 #define SCMD_ENB_DBGID_M 0x1 1590 #define SCMD_ENB_DBGID_V(x) ((x) << SCMD_ENB_DBGID_S) 1591 #define SCMD_ENB_DBGID_G(x) \ 1592 (((x) >> SCMD_ENB_DBGID_S) & SCMD_ENB_DBGID_M) 1593 1594 /* IV generation in SW. */ 1595 #define SCMD_IV_GEN_CTRL_S 30 1596 #define SCMD_IV_GEN_CTRL_M 0x1 1597 #define SCMD_IV_GEN_CTRL_V(x) ((x) << SCMD_IV_GEN_CTRL_S) 1598 #define SCMD_IV_GEN_CTRL_G(x) \ 1599 (((x) >> SCMD_IV_GEN_CTRL_S) & SCMD_IV_GEN_CTRL_M) 1600 #define SCMD_IV_GEN_CTRL_F SCMD_IV_GEN_CTRL_V(1U) 1601 1602 /* More frags */ 1603 #define SCMD_MORE_FRAGS_S 20 1604 #define SCMD_MORE_FRAGS_M 0x1 1605 #define SCMD_MORE_FRAGS_V(x) ((x) << SCMD_MORE_FRAGS_S) 1606 #define SCMD_MORE_FRAGS_G(x) (((x) >> SCMD_MORE_FRAGS_S) & SCMD_MORE_FRAGS_M) 1607 1608 /*last frag */ 1609 #define SCMD_LAST_FRAG_S 19 1610 #define SCMD_LAST_FRAG_M 0x1 1611 #define SCMD_LAST_FRAG_V(x) ((x) << SCMD_LAST_FRAG_S) 1612 #define SCMD_LAST_FRAG_G(x) (((x) >> SCMD_LAST_FRAG_S) & SCMD_LAST_FRAG_M) 1613 1614 /* TlsCompPdu */ 1615 #define SCMD_TLS_COMPPDU_S 18 1616 #define SCMD_TLS_COMPPDU_M 0x1 1617 #define SCMD_TLS_COMPPDU_V(x) ((x) << SCMD_TLS_COMPPDU_S) 1618 #define SCMD_TLS_COMPPDU_G(x) (((x) >> SCMD_TLS_COMPPDU_S) & SCMD_TLS_COMPPDU_M) 1619 1620 /* KeyCntxtInline - Key context inline after the scmd OR PayloadOnly*/ 1621 #define SCMD_KEY_CTX_INLINE_S 17 1622 #define SCMD_KEY_CTX_INLINE_M 0x1 1623 #define SCMD_KEY_CTX_INLINE_V(x) ((x) << SCMD_KEY_CTX_INLINE_S) 1624 #define SCMD_KEY_CTX_INLINE_G(x) \ 1625 (((x) >> SCMD_KEY_CTX_INLINE_S) & SCMD_KEY_CTX_INLINE_M) 1626 #define SCMD_KEY_CTX_INLINE_F SCMD_KEY_CTX_INLINE_V(1U) 1627 1628 /* TLSFragEnable - 0: Host created TLS PDUs, 1: TLS Framgmentation in ASIC */ 1629 #define SCMD_TLS_FRAG_ENABLE_S 16 1630 #define SCMD_TLS_FRAG_ENABLE_M 0x1 1631 #define SCMD_TLS_FRAG_ENABLE_V(x) ((x) << SCMD_TLS_FRAG_ENABLE_S) 1632 #define SCMD_TLS_FRAG_ENABLE_G(x) \ 1633 (((x) >> SCMD_TLS_FRAG_ENABLE_S) & SCMD_TLS_FRAG_ENABLE_M) 1634 #define SCMD_TLS_FRAG_ENABLE_F SCMD_TLS_FRAG_ENABLE_V(1U) 1635 1636 /* MacOnly - Only send the MAC and discard PDU. This is valid for hash only 1637 * modes, in this case TLS_TX will drop the PDU and only 1638 * send back the MAC bytes. 1639 */ 1640 #define SCMD_MAC_ONLY_S 15 1641 #define SCMD_MAC_ONLY_M 0x1 1642 #define SCMD_MAC_ONLY_V(x) ((x) << SCMD_MAC_ONLY_S) 1643 #define SCMD_MAC_ONLY_G(x) \ 1644 (((x) >> SCMD_MAC_ONLY_S) & SCMD_MAC_ONLY_M) 1645 #define SCMD_MAC_ONLY_F SCMD_MAC_ONLY_V(1U) 1646 1647 /* AadIVDrop - Drop the AAD and IV fields. Useful in protocols 1648 * which have complex AAD and IV formations Eg:AES-CCM 1649 */ 1650 #define SCMD_AADIVDROP_S 14 1651 #define SCMD_AADIVDROP_M 0x1 1652 #define SCMD_AADIVDROP_V(x) ((x) << SCMD_AADIVDROP_S) 1653 #define SCMD_AADIVDROP_G(x) \ 1654 (((x) >> SCMD_AADIVDROP_S) & SCMD_AADIVDROP_M) 1655 #define SCMD_AADIVDROP_F SCMD_AADIVDROP_V(1U) 1656 1657 /* HdrLength - Length of all headers excluding TLS header 1658 * present before start of crypto PDU/payload. 1659 */ 1660 #define SCMD_HDR_LEN_S 0 1661 #define SCMD_HDR_LEN_M 0x3fff 1662 #define SCMD_HDR_LEN_V(x) ((x) << SCMD_HDR_LEN_S) 1663 #define SCMD_HDR_LEN_G(x) \ 1664 (((x) >> SCMD_HDR_LEN_S) & SCMD_HDR_LEN_M) 1665 1666 struct cpl_tx_sec_pdu { 1667 __be32 op_ivinsrtofst; 1668 __be32 pldlen; 1669 __be32 aadstart_cipherstop_hi; 1670 __be32 cipherstop_lo_authinsert; 1671 __be32 seqno_numivs; 1672 __be32 ivgen_hdrlen; 1673 __be64 scmd1; 1674 }; 1675 1676 #define CPL_TX_SEC_PDU_OPCODE_S 24 1677 #define CPL_TX_SEC_PDU_OPCODE_M 0xff 1678 #define CPL_TX_SEC_PDU_OPCODE_V(x) ((x) << CPL_TX_SEC_PDU_OPCODE_S) 1679 #define CPL_TX_SEC_PDU_OPCODE_G(x) \ 1680 (((x) >> CPL_TX_SEC_PDU_OPCODE_S) & CPL_TX_SEC_PDU_OPCODE_M) 1681 1682 /* RX Channel Id */ 1683 #define CPL_TX_SEC_PDU_RXCHID_S 22 1684 #define CPL_TX_SEC_PDU_RXCHID_M 0x1 1685 #define CPL_TX_SEC_PDU_RXCHID_V(x) ((x) << CPL_TX_SEC_PDU_RXCHID_S) 1686 #define CPL_TX_SEC_PDU_RXCHID_G(x) \ 1687 (((x) >> CPL_TX_SEC_PDU_RXCHID_S) & CPL_TX_SEC_PDU_RXCHID_M) 1688 #define CPL_TX_SEC_PDU_RXCHID_F CPL_TX_SEC_PDU_RXCHID_V(1U) 1689 1690 /* Ack Follows */ 1691 #define CPL_TX_SEC_PDU_ACKFOLLOWS_S 21 1692 #define CPL_TX_SEC_PDU_ACKFOLLOWS_M 0x1 1693 #define CPL_TX_SEC_PDU_ACKFOLLOWS_V(x) ((x) << CPL_TX_SEC_PDU_ACKFOLLOWS_S) 1694 #define CPL_TX_SEC_PDU_ACKFOLLOWS_G(x) \ 1695 (((x) >> CPL_TX_SEC_PDU_ACKFOLLOWS_S) & CPL_TX_SEC_PDU_ACKFOLLOWS_M) 1696 #define CPL_TX_SEC_PDU_ACKFOLLOWS_F CPL_TX_SEC_PDU_ACKFOLLOWS_V(1U) 1697 1698 /* Loopback bit in cpl_tx_sec_pdu */ 1699 #define CPL_TX_SEC_PDU_ULPTXLPBK_S 20 1700 #define CPL_TX_SEC_PDU_ULPTXLPBK_M 0x1 1701 #define CPL_TX_SEC_PDU_ULPTXLPBK_V(x) ((x) << CPL_TX_SEC_PDU_ULPTXLPBK_S) 1702 #define CPL_TX_SEC_PDU_ULPTXLPBK_G(x) \ 1703 (((x) >> CPL_TX_SEC_PDU_ULPTXLPBK_S) & CPL_TX_SEC_PDU_ULPTXLPBK_M) 1704 #define CPL_TX_SEC_PDU_ULPTXLPBK_F CPL_TX_SEC_PDU_ULPTXLPBK_V(1U) 1705 1706 /* Length of cpl header encapsulated */ 1707 #define CPL_TX_SEC_PDU_CPLLEN_S 16 1708 #define CPL_TX_SEC_PDU_CPLLEN_M 0xf 1709 #define CPL_TX_SEC_PDU_CPLLEN_V(x) ((x) << CPL_TX_SEC_PDU_CPLLEN_S) 1710 #define CPL_TX_SEC_PDU_CPLLEN_G(x) \ 1711 (((x) >> CPL_TX_SEC_PDU_CPLLEN_S) & CPL_TX_SEC_PDU_CPLLEN_M) 1712 1713 /* PlaceHolder */ 1714 #define CPL_TX_SEC_PDU_PLACEHOLDER_S 10 1715 #define CPL_TX_SEC_PDU_PLACEHOLDER_M 0x1 1716 #define CPL_TX_SEC_PDU_PLACEHOLDER_V(x) ((x) << CPL_TX_SEC_PDU_PLACEHOLDER_S) 1717 #define CPL_TX_SEC_PDU_PLACEHOLDER_G(x) \ 1718 (((x) >> CPL_TX_SEC_PDU_PLACEHOLDER_S) & \ 1719 CPL_TX_SEC_PDU_PLACEHOLDER_M) 1720 1721 /* IvInsrtOffset: Insertion location for IV */ 1722 #define CPL_TX_SEC_PDU_IVINSRTOFST_S 0 1723 #define CPL_TX_SEC_PDU_IVINSRTOFST_M 0x3ff 1724 #define CPL_TX_SEC_PDU_IVINSRTOFST_V(x) ((x) << CPL_TX_SEC_PDU_IVINSRTOFST_S) 1725 #define CPL_TX_SEC_PDU_IVINSRTOFST_G(x) \ 1726 (((x) >> CPL_TX_SEC_PDU_IVINSRTOFST_S) & \ 1727 CPL_TX_SEC_PDU_IVINSRTOFST_M) 1728 1729 /* AadStartOffset: Offset in bytes for AAD start from 1730 * the first byte following the pkt headers (0-255 bytes) 1731 */ 1732 #define CPL_TX_SEC_PDU_AADSTART_S 24 1733 #define CPL_TX_SEC_PDU_AADSTART_M 0xff 1734 #define CPL_TX_SEC_PDU_AADSTART_V(x) ((x) << CPL_TX_SEC_PDU_AADSTART_S) 1735 #define CPL_TX_SEC_PDU_AADSTART_G(x) \ 1736 (((x) >> CPL_TX_SEC_PDU_AADSTART_S) & \ 1737 CPL_TX_SEC_PDU_AADSTART_M) 1738 1739 /* AadStopOffset: offset in bytes for AAD stop/end from the first byte following 1740 * the pkt headers (0-511 bytes) 1741 */ 1742 #define CPL_TX_SEC_PDU_AADSTOP_S 15 1743 #define CPL_TX_SEC_PDU_AADSTOP_M 0x1ff 1744 #define CPL_TX_SEC_PDU_AADSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AADSTOP_S) 1745 #define CPL_TX_SEC_PDU_AADSTOP_G(x) \ 1746 (((x) >> CPL_TX_SEC_PDU_AADSTOP_S) & CPL_TX_SEC_PDU_AADSTOP_M) 1747 1748 /* CipherStartOffset: offset in bytes for encryption/decryption start from the 1749 * first byte following the pkt headers (0-1023 bytes) 1750 */ 1751 #define CPL_TX_SEC_PDU_CIPHERSTART_S 5 1752 #define CPL_TX_SEC_PDU_CIPHERSTART_M 0x3ff 1753 #define CPL_TX_SEC_PDU_CIPHERSTART_V(x) ((x) << CPL_TX_SEC_PDU_CIPHERSTART_S) 1754 #define CPL_TX_SEC_PDU_CIPHERSTART_G(x) \ 1755 (((x) >> CPL_TX_SEC_PDU_CIPHERSTART_S) & \ 1756 CPL_TX_SEC_PDU_CIPHERSTART_M) 1757 1758 /* CipherStopOffset: offset in bytes for encryption/decryption end 1759 * from end of the payload of this command (0-511 bytes) 1760 */ 1761 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_S 0 1762 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_M 0x1f 1763 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_V(x) \ 1764 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_HI_S) 1765 #define CPL_TX_SEC_PDU_CIPHERSTOP_HI_G(x) \ 1766 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_HI_S) & \ 1767 CPL_TX_SEC_PDU_CIPHERSTOP_HI_M) 1768 1769 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_S 28 1770 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_M 0xf 1771 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_V(x) \ 1772 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_LO_S) 1773 #define CPL_TX_SEC_PDU_CIPHERSTOP_LO_G(x) \ 1774 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_LO_S) & \ 1775 CPL_TX_SEC_PDU_CIPHERSTOP_LO_M) 1776 1777 /* AuthStartOffset: offset in bytes for authentication start from 1778 * the first byte following the pkt headers (0-1023) 1779 */ 1780 #define CPL_TX_SEC_PDU_AUTHSTART_S 18 1781 #define CPL_TX_SEC_PDU_AUTHSTART_M 0x3ff 1782 #define CPL_TX_SEC_PDU_AUTHSTART_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTART_S) 1783 #define CPL_TX_SEC_PDU_AUTHSTART_G(x) \ 1784 (((x) >> CPL_TX_SEC_PDU_AUTHSTART_S) & \ 1785 CPL_TX_SEC_PDU_AUTHSTART_M) 1786 1787 /* AuthStopOffset: offset in bytes for authentication 1788 * end from end of the payload of this command (0-511 Bytes) 1789 */ 1790 #define CPL_TX_SEC_PDU_AUTHSTOP_S 9 1791 #define CPL_TX_SEC_PDU_AUTHSTOP_M 0x1ff 1792 #define CPL_TX_SEC_PDU_AUTHSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTOP_S) 1793 #define CPL_TX_SEC_PDU_AUTHSTOP_G(x) \ 1794 (((x) >> CPL_TX_SEC_PDU_AUTHSTOP_S) & \ 1795 CPL_TX_SEC_PDU_AUTHSTOP_M) 1796 1797 /* AuthInsrtOffset: offset in bytes for authentication insertion 1798 * from end of the payload of this command (0-511 bytes) 1799 */ 1800 #define CPL_TX_SEC_PDU_AUTHINSERT_S 0 1801 #define CPL_TX_SEC_PDU_AUTHINSERT_M 0x1ff 1802 #define CPL_TX_SEC_PDU_AUTHINSERT_V(x) ((x) << CPL_TX_SEC_PDU_AUTHINSERT_S) 1803 #define CPL_TX_SEC_PDU_AUTHINSERT_G(x) \ 1804 (((x) >> CPL_TX_SEC_PDU_AUTHINSERT_S) & \ 1805 CPL_TX_SEC_PDU_AUTHINSERT_M) 1806 1807 struct cpl_rx_phys_dsgl { 1808 __be32 op_to_tid; 1809 __be32 pcirlxorder_to_noofsgentr; 1810 struct rss_header rss_hdr_int; 1811 }; 1812 1813 #define CPL_RX_PHYS_DSGL_OPCODE_S 24 1814 #define CPL_RX_PHYS_DSGL_OPCODE_M 0xff 1815 #define CPL_RX_PHYS_DSGL_OPCODE_V(x) ((x) << CPL_RX_PHYS_DSGL_OPCODE_S) 1816 #define CPL_RX_PHYS_DSGL_OPCODE_G(x) \ 1817 (((x) >> CPL_RX_PHYS_DSGL_OPCODE_S) & CPL_RX_PHYS_DSGL_OPCODE_M) 1818 1819 #define CPL_RX_PHYS_DSGL_ISRDMA_S 23 1820 #define CPL_RX_PHYS_DSGL_ISRDMA_M 0x1 1821 #define CPL_RX_PHYS_DSGL_ISRDMA_V(x) ((x) << CPL_RX_PHYS_DSGL_ISRDMA_S) 1822 #define CPL_RX_PHYS_DSGL_ISRDMA_G(x) \ 1823 (((x) >> CPL_RX_PHYS_DSGL_ISRDMA_S) & CPL_RX_PHYS_DSGL_ISRDMA_M) 1824 #define CPL_RX_PHYS_DSGL_ISRDMA_F CPL_RX_PHYS_DSGL_ISRDMA_V(1U) 1825 1826 #define CPL_RX_PHYS_DSGL_RSVD1_S 20 1827 #define CPL_RX_PHYS_DSGL_RSVD1_M 0x7 1828 #define CPL_RX_PHYS_DSGL_RSVD1_V(x) ((x) << CPL_RX_PHYS_DSGL_RSVD1_S) 1829 #define CPL_RX_PHYS_DSGL_RSVD1_G(x) \ 1830 (((x) >> CPL_RX_PHYS_DSGL_RSVD1_S) & \ 1831 CPL_RX_PHYS_DSGL_RSVD1_M) 1832 1833 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_S 31 1834 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_M 0x1 1835 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_V(x) \ 1836 ((x) << CPL_RX_PHYS_DSGL_PCIRLXORDER_S) 1837 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_G(x) \ 1838 (((x) >> CPL_RX_PHYS_DSGL_PCIRLXORDER_S) & \ 1839 CPL_RX_PHYS_DSGL_PCIRLXORDER_M) 1840 #define CPL_RX_PHYS_DSGL_PCIRLXORDER_F CPL_RX_PHYS_DSGL_PCIRLXORDER_V(1U) 1841 1842 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_S 30 1843 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_M 0x1 1844 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_V(x) \ 1845 ((x) << CPL_RX_PHYS_DSGL_PCINOSNOOP_S) 1846 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_G(x) \ 1847 (((x) >> CPL_RX_PHYS_DSGL_PCINOSNOOP_S) & \ 1848 CPL_RX_PHYS_DSGL_PCINOSNOOP_M) 1849 1850 #define CPL_RX_PHYS_DSGL_PCINOSNOOP_F CPL_RX_PHYS_DSGL_PCINOSNOOP_V(1U) 1851 1852 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_S 29 1853 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_M 0x1 1854 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_V(x) \ 1855 ((x) << CPL_RX_PHYS_DSGL_PCITPHNTENB_S) 1856 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_G(x) \ 1857 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNTENB_S) & \ 1858 CPL_RX_PHYS_DSGL_PCITPHNTENB_M) 1859 #define CPL_RX_PHYS_DSGL_PCITPHNTENB_F CPL_RX_PHYS_DSGL_PCITPHNTENB_V(1U) 1860 1861 #define CPL_RX_PHYS_DSGL_PCITPHNT_S 27 1862 #define CPL_RX_PHYS_DSGL_PCITPHNT_M 0x3 1863 #define CPL_RX_PHYS_DSGL_PCITPHNT_V(x) ((x) << CPL_RX_PHYS_DSGL_PCITPHNT_S) 1864 #define CPL_RX_PHYS_DSGL_PCITPHNT_G(x) \ 1865 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNT_S) & \ 1866 CPL_RX_PHYS_DSGL_PCITPHNT_M) 1867 1868 #define CPL_RX_PHYS_DSGL_DCAID_S 16 1869 #define CPL_RX_PHYS_DSGL_DCAID_M 0x7ff 1870 #define CPL_RX_PHYS_DSGL_DCAID_V(x) ((x) << CPL_RX_PHYS_DSGL_DCAID_S) 1871 #define CPL_RX_PHYS_DSGL_DCAID_G(x) \ 1872 (((x) >> CPL_RX_PHYS_DSGL_DCAID_S) & \ 1873 CPL_RX_PHYS_DSGL_DCAID_M) 1874 1875 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_S 0 1876 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_M 0xffff 1877 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_V(x) \ 1878 ((x) << CPL_RX_PHYS_DSGL_NOOFSGENTR_S) 1879 #define CPL_RX_PHYS_DSGL_NOOFSGENTR_G(x) \ 1880 (((x) >> CPL_RX_PHYS_DSGL_NOOFSGENTR_S) & \ 1881 CPL_RX_PHYS_DSGL_NOOFSGENTR_M) 1882 1883 struct cpl_rx_mps_pkt { 1884 __be32 op_to_r1_hi; 1885 __be32 r1_lo_length; 1886 }; 1887 1888 #define CPL_RX_MPS_PKT_OP_S 24 1889 #define CPL_RX_MPS_PKT_OP_M 0xff 1890 #define CPL_RX_MPS_PKT_OP_V(x) ((x) << CPL_RX_MPS_PKT_OP_S) 1891 #define CPL_RX_MPS_PKT_OP_G(x) \ 1892 (((x) >> CPL_RX_MPS_PKT_OP_S) & CPL_RX_MPS_PKT_OP_M) 1893 1894 #define CPL_RX_MPS_PKT_TYPE_S 20 1895 #define CPL_RX_MPS_PKT_TYPE_M 0xf 1896 #define CPL_RX_MPS_PKT_TYPE_V(x) ((x) << CPL_RX_MPS_PKT_TYPE_S) 1897 #define CPL_RX_MPS_PKT_TYPE_G(x) \ 1898 (((x) >> CPL_RX_MPS_PKT_TYPE_S) & CPL_RX_MPS_PKT_TYPE_M) 1899 1900 enum { 1901 X_CPL_RX_MPS_PKT_TYPE_PAUSE = 1 << 0, 1902 X_CPL_RX_MPS_PKT_TYPE_PPP = 1 << 1, 1903 X_CPL_RX_MPS_PKT_TYPE_QFC = 1 << 2, 1904 X_CPL_RX_MPS_PKT_TYPE_PTP = 1 << 3 1905 }; 1906 #endif /* __T4_MSG_H */ 1907