1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __ASM_POWERPC_CPUTABLE_H
3 #define __ASM_POWERPC_CPUTABLE_H
4
5
6 #include <linux/types.h>
7 #include <asm/asm-compat.h>
8 #include <asm/feature-fixups.h>
9 #include <uapi/asm/cputable.h>
10
11 #ifndef __ASSEMBLY__
12
13 /* This structure can grow, it's real size is used by head.S code
14 * via the mkdefs mechanism.
15 */
16 struct cpu_spec;
17
18 typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
19 typedef void (*cpu_restore_t)(void);
20
21 enum powerpc_oprofile_type {
22 PPC_OPROFILE_INVALID = 0,
23 PPC_OPROFILE_RS64 = 1,
24 PPC_OPROFILE_POWER4 = 2,
25 PPC_OPROFILE_G4 = 3,
26 PPC_OPROFILE_FSL_EMB = 4,
27 PPC_OPROFILE_CELL = 5,
28 PPC_OPROFILE_PA6T = 6,
29 };
30
31 enum powerpc_pmc_type {
32 PPC_PMC_DEFAULT = 0,
33 PPC_PMC_IBM = 1,
34 PPC_PMC_PA6T = 2,
35 PPC_PMC_G4 = 3,
36 };
37
38 struct pt_regs;
39
40 extern int machine_check_generic(struct pt_regs *regs);
41 extern int machine_check_4xx(struct pt_regs *regs);
42 extern int machine_check_440A(struct pt_regs *regs);
43 extern int machine_check_e500mc(struct pt_regs *regs);
44 extern int machine_check_e500(struct pt_regs *regs);
45 extern int machine_check_e200(struct pt_regs *regs);
46 extern int machine_check_47x(struct pt_regs *regs);
47 int machine_check_8xx(struct pt_regs *regs);
48 int machine_check_83xx(struct pt_regs *regs);
49
50 extern void cpu_down_flush_e500v2(void);
51 extern void cpu_down_flush_e500mc(void);
52 extern void cpu_down_flush_e5500(void);
53 extern void cpu_down_flush_e6500(void);
54
55 /* NOTE WELL: Update identify_cpu() if fields are added or removed! */
56 struct cpu_spec {
57 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
58 unsigned int pvr_mask;
59 unsigned int pvr_value;
60
61 char *cpu_name;
62 unsigned long cpu_features; /* Kernel features */
63 unsigned int cpu_user_features; /* Userland features */
64 unsigned int cpu_user_features2; /* Userland features v2 */
65 unsigned int mmu_features; /* MMU features */
66
67 /* cache line sizes */
68 unsigned int icache_bsize;
69 unsigned int dcache_bsize;
70
71 /* flush caches inside the current cpu */
72 void (*cpu_down_flush)(void);
73
74 /* number of performance monitor counters */
75 unsigned int num_pmcs;
76 enum powerpc_pmc_type pmc_type;
77
78 /* this is called to initialize various CPU bits like L1 cache,
79 * BHT, SPD, etc... from head.S before branching to identify_machine
80 */
81 cpu_setup_t cpu_setup;
82 /* Used to restore cpu setup on secondary processors and at resume */
83 cpu_restore_t cpu_restore;
84
85 /* Used by oprofile userspace to select the right counters */
86 char *oprofile_cpu_type;
87
88 /* Processor specific oprofile operations */
89 enum powerpc_oprofile_type oprofile_type;
90
91 /* Bit locations inside the mmcra change */
92 unsigned long oprofile_mmcra_sihv;
93 unsigned long oprofile_mmcra_sipr;
94
95 /* Bits to clear during an oprofile exception */
96 unsigned long oprofile_mmcra_clear;
97
98 /* Name of processor class, for the ELF AT_PLATFORM entry */
99 char *platform;
100
101 /* Processor specific machine check handling. Return negative
102 * if the error is fatal, 1 if it was fully recovered and 0 to
103 * pass up (not CPU originated) */
104 int (*machine_check)(struct pt_regs *regs);
105
106 /*
107 * Processor specific early machine check handler which is
108 * called in real mode to handle SLB and TLB errors.
109 */
110 long (*machine_check_early)(struct pt_regs *regs);
111
112 /*
113 * Processor specific routine to flush tlbs.
114 */
115 void (*flush_tlb)(unsigned int action);
116
117 };
118
119 extern struct cpu_spec *cur_cpu_spec;
120
121 extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
122
123 extern void set_cur_cpu_spec(struct cpu_spec *s);
124 extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
125 extern void identify_cpu_name(unsigned int pvr);
126 extern void do_feature_fixups(unsigned long value, void *fixup_start,
127 void *fixup_end);
128
129 extern const char *powerpc_base_platform;
130
131 #ifdef CONFIG_JUMP_LABEL_FEATURE_CHECKS
132 extern void cpu_feature_keys_init(void);
133 #else
cpu_feature_keys_init(void)134 static inline void cpu_feature_keys_init(void) { }
135 #endif
136
137 /* TLB flush actions. Used as argument to cpu_spec.flush_tlb() hook */
138 enum {
139 TLB_INVAL_SCOPE_GLOBAL = 0, /* invalidate all TLBs */
140 TLB_INVAL_SCOPE_LPID = 1, /* invalidate TLBs for current LPID */
141 };
142
143 #endif /* __ASSEMBLY__ */
144
145 /* CPU kernel features */
146
147 /* Retain the 32b definitions all use bottom half of word */
148 #define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
149 #define CPU_FTR_L2CR ASM_CONST(0x00000002)
150 #define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
151 #define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
152 #define CPU_FTR_TAU ASM_CONST(0x00000010)
153 #define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
154 #define CPU_FTR_USE_TB ASM_CONST(0x00000040)
155 #define CPU_FTR_L2CSR ASM_CONST(0x00000080)
156 #define CPU_FTR_601 ASM_CONST(0x00000100)
157 #define CPU_FTR_DBELL ASM_CONST(0x00000200)
158 #define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
159 #define CPU_FTR_L3CR ASM_CONST(0x00000800)
160 #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
161 #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
162 #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
163 #define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
164 #define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
165 #define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
166 #define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
167 #define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
168 #define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
169 #define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
170 #define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
171 #define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
172 #define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
173 #define CPU_FTR_SPE ASM_CONST(0x02000000)
174 #define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
175 #define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
176 #define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
177 #define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
178 #define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
179
180 /*
181 * Add the 64-bit processor unique features in the top half of the word;
182 * on 32-bit, make the names available but defined to be 0.
183 */
184 #ifdef __powerpc64__
185 #define LONG_ASM_CONST(x) ASM_CONST(x)
186 #else
187 #define LONG_ASM_CONST(x) 0
188 #endif
189
190 #define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000)
191 #define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000)
192 #define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000)
193 #define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000)
194 #define CPU_FTR_ARCH_300 LONG_ASM_CONST(0x0000001000000000)
195 #define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000)
196 #define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000)
197 #define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000)
198 #define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000)
199 #define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000)
200 #define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000)
201 #define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000)
202 #define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000)
203 #define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000)
204 #define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000)
205 #define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000)
206 #define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000)
207 #define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000)
208 #define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
209 #define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
210 #define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
211 #define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000)
212 #define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
213 #define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
214 #define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000)
215 #define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
216 #define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
217 #define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000)
218 #define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x1000000000000000)
219 #define CPU_FTR_P9_TLBIE_STQ_BUG LONG_ASM_CONST(0x0000400000000000)
220 #define CPU_FTR_POWER9_DD1 LONG_ASM_CONST(0x4000000000000000)
221 #define CPU_FTR_P9_TLBIE_ERAT_BUG LONG_ASM_CONST(0x0001000000000000)
222
223 #ifndef __ASSEMBLY__
224
225 #define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
226
227 #define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
228
229 /* We only set the altivec features if the kernel was compiled with altivec
230 * support
231 */
232 #ifdef CONFIG_ALTIVEC
233 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
234 #define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
235 #else
236 #define CPU_FTR_ALTIVEC_COMP 0
237 #define PPC_FEATURE_HAS_ALTIVEC_COMP 0
238 #endif
239
240 /* We only set the VSX features if the kernel was compiled with VSX
241 * support
242 */
243 #ifdef CONFIG_VSX
244 #define CPU_FTR_VSX_COMP CPU_FTR_VSX
245 #define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
246 #else
247 #define CPU_FTR_VSX_COMP 0
248 #define PPC_FEATURE_HAS_VSX_COMP 0
249 #endif
250
251 /* We only set the spe features if the kernel was compiled with spe
252 * support
253 */
254 #ifdef CONFIG_SPE
255 #define CPU_FTR_SPE_COMP CPU_FTR_SPE
256 #define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
257 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
258 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
259 #else
260 #define CPU_FTR_SPE_COMP 0
261 #define PPC_FEATURE_HAS_SPE_COMP 0
262 #define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
263 #define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
264 #endif
265
266 /* We only set the TM feature if the kernel was compiled with TM supprt */
267 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
268 #define CPU_FTR_TM_COMP CPU_FTR_TM
269 #define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
270 #define PPC_FEATURE2_HTM_NOSC_COMP PPC_FEATURE2_HTM_NOSC
271 #else
272 #define CPU_FTR_TM_COMP 0
273 #define PPC_FEATURE2_HTM_COMP 0
274 #define PPC_FEATURE2_HTM_NOSC_COMP 0
275 #endif
276
277 /* We need to mark all pages as being coherent if we're SMP or we have a
278 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
279 * require it for PCI "streaming/prefetch" to work properly.
280 * This is also required by 52xx family.
281 */
282 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
283 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
284 || defined(CONFIG_PPC_MPC52xx)
285 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
286 #else
287 #define CPU_FTR_COMMON 0
288 #endif
289
290 /* The powersave features NAP & DOZE seems to confuse BDI when
291 debugging. So if a BDI is used, disable theses
292 */
293 #ifndef CONFIG_BDI_SWITCH
294 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
295 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
296 #else
297 #define CPU_FTR_MAYBE_CAN_DOZE 0
298 #define CPU_FTR_MAYBE_CAN_NAP 0
299 #endif
300
301 #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
302 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
303 #define CPU_FTRS_603 (CPU_FTR_COMMON | \
304 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
305 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
306 #define CPU_FTRS_604 (CPU_FTR_COMMON | \
307 CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
308 #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
309 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
310 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
311 #define CPU_FTRS_740 (CPU_FTR_COMMON | \
312 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
313 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
314 CPU_FTR_PPC_LE)
315 #define CPU_FTRS_750 (CPU_FTR_COMMON | \
316 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
317 CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
318 CPU_FTR_PPC_LE)
319 #define CPU_FTRS_750CL (CPU_FTRS_750)
320 #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
321 #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
322 #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
323 #define CPU_FTRS_750GX (CPU_FTRS_750FX)
324 #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
325 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
326 CPU_FTR_ALTIVEC_COMP | \
327 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
328 #define CPU_FTRS_7400 (CPU_FTR_COMMON | \
329 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
330 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
331 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
332 #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
333 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
334 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
335 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
336 #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
337 CPU_FTR_USE_TB | \
338 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
339 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
340 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
341 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
342 #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
343 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
344 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
345 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
346 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
347 #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
348 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
349 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
350 CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
351 #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
352 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
353 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
354 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
355 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
356 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
357 #define CPU_FTRS_7455 (CPU_FTR_COMMON | \
358 CPU_FTR_USE_TB | \
359 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
360 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
361 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
362 #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
363 CPU_FTR_USE_TB | \
364 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
365 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
366 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
367 CPU_FTR_NEED_PAIRED_STWCX)
368 #define CPU_FTRS_7447 (CPU_FTR_COMMON | \
369 CPU_FTR_USE_TB | \
370 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
371 CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
372 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
373 #define CPU_FTRS_7447A (CPU_FTR_COMMON | \
374 CPU_FTR_USE_TB | \
375 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
376 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
377 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
378 #define CPU_FTRS_7448 (CPU_FTR_COMMON | \
379 CPU_FTR_USE_TB | \
380 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
381 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
382 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
383 #define CPU_FTRS_82XX (CPU_FTR_COMMON | \
384 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
385 #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
386 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
387 #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
388 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
389 CPU_FTR_COMMON)
390 #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
391 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
392 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
393 #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB)
394 #define CPU_FTRS_8XX (CPU_FTR_USE_TB | CPU_FTR_NOEXECUTE)
395 #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
396 #define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
397 #define CPU_FTRS_440x6 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
398 CPU_FTR_INDEXED_DCR)
399 #define CPU_FTRS_47X (CPU_FTRS_440x6)
400 #define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
401 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
402 CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
403 CPU_FTR_DEBUG_LVL_EXC)
404 #define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
405 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
406 CPU_FTR_NOEXECUTE)
407 #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
408 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
409 CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
410 #define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
411 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
412 CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
413 /*
414 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
415 * same workaround as CPU_FTR_CELL_TB_BUG.
416 */
417 #define CPU_FTRS_E5500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
418 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
419 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
420 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
421 #define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
422 CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
423 CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
424 CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
425 CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
426 #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
427
428 /* 64-bit CPUs */
429 #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
430 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
431 CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
432 CPU_FTR_STCX_CHECKS_ADDRESS)
433 #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
434 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
435 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
436 CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
437 CPU_FTR_HVMODE | CPU_FTR_DABRX)
438 #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
439 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
440 CPU_FTR_MMCRA | CPU_FTR_SMT | \
441 CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
442 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
443 #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
444 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
445 CPU_FTR_MMCRA | CPU_FTR_SMT | \
446 CPU_FTR_COHERENT_ICACHE | \
447 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
448 CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
449 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
450 CPU_FTR_DABRX)
451 #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
452 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
453 CPU_FTR_MMCRA | CPU_FTR_SMT | \
454 CPU_FTR_COHERENT_ICACHE | \
455 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
456 CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
457 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
458 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
459 CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
460 #define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
461 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
462 CPU_FTR_MMCRA | CPU_FTR_SMT | \
463 CPU_FTR_COHERENT_ICACHE | \
464 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
465 CPU_FTR_DSCR | CPU_FTR_SAO | \
466 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
467 CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
468 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
469 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP)
470 #define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
471 #define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)
472 #define CPU_FTRS_POWER9 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
473 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
474 CPU_FTR_MMCRA | CPU_FTR_SMT | \
475 CPU_FTR_COHERENT_ICACHE | \
476 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
477 CPU_FTR_DSCR | CPU_FTR_SAO | \
478 CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
479 CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
480 CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
481 CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_ARCH_300 | \
482 CPU_FTR_P9_TLBIE_STQ_BUG | CPU_FTR_P9_TLBIE_ERAT_BUG)
483 #define CPU_FTRS_POWER9_DD1 ((CPU_FTRS_POWER9 | CPU_FTR_POWER9_DD1) & \
484 (~CPU_FTR_SAO))
485 #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
486 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
487 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
488 CPU_FTR_PAUSE_ZERO | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
489 CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
490 #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
491 CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
492 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
493 #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
494
495 #ifdef __powerpc64__
496 #ifdef CONFIG_PPC_BOOK3E
497 #define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 | CPU_FTRS_E5500)
498 #else
499 #define CPU_FTRS_POSSIBLE \
500 (CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
501 CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
502 CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \
503 CPU_FTRS_PA6T | CPU_FTR_VSX | CPU_FTRS_POWER9 | CPU_FTRS_POWER9_DD1)
504 #endif
505 #else
506 enum {
507 CPU_FTRS_POSSIBLE =
508 #ifdef CONFIG_PPC_BOOK3S_32
509 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
510 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
511 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
512 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
513 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
514 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
515 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
516 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
517 CPU_FTRS_CLASSIC32 |
518 #else
519 CPU_FTRS_GENERIC_32 |
520 #endif
521 #ifdef CONFIG_PPC_8xx
522 CPU_FTRS_8XX |
523 #endif
524 #ifdef CONFIG_40x
525 CPU_FTRS_40X |
526 #endif
527 #ifdef CONFIG_44x
528 CPU_FTRS_44X | CPU_FTRS_440x6 |
529 #endif
530 #ifdef CONFIG_PPC_47x
531 CPU_FTRS_47X | CPU_FTR_476_DD2 |
532 #endif
533 #ifdef CONFIG_E200
534 CPU_FTRS_E200 |
535 #endif
536 #ifdef CONFIG_E500
537 CPU_FTRS_E500 | CPU_FTRS_E500_2 |
538 #endif
539 #ifdef CONFIG_PPC_E500MC
540 CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
541 #endif
542 0,
543 };
544 #endif /* __powerpc64__ */
545
546 #ifdef __powerpc64__
547 #ifdef CONFIG_PPC_BOOK3E
548 #define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500)
549 #else
550 #define CPU_FTRS_ALWAYS \
551 (CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
552 CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
553 CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
554 CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & \
555 CPU_FTRS_POWER9)
556 #endif
557 #else
558 enum {
559 CPU_FTRS_ALWAYS =
560 #ifdef CONFIG_PPC_BOOK3S_32
561 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
562 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
563 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
564 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
565 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
566 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
567 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
568 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
569 CPU_FTRS_CLASSIC32 &
570 #else
571 CPU_FTRS_GENERIC_32 &
572 #endif
573 #ifdef CONFIG_PPC_8xx
574 CPU_FTRS_8XX &
575 #endif
576 #ifdef CONFIG_40x
577 CPU_FTRS_40X &
578 #endif
579 #ifdef CONFIG_44x
580 CPU_FTRS_44X & CPU_FTRS_440x6 &
581 #endif
582 #ifdef CONFIG_E200
583 CPU_FTRS_E200 &
584 #endif
585 #ifdef CONFIG_E500
586 CPU_FTRS_E500 & CPU_FTRS_E500_2 &
587 #endif
588 #ifdef CONFIG_PPC_E500MC
589 CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
590 #endif
591 ~CPU_FTR_EMB_HV & /* can be removed at runtime */
592 CPU_FTRS_POSSIBLE,
593 };
594 #endif /* __powerpc64__ */
595
596 #define HBP_NUM 1
597
598 #endif /* !__ASSEMBLY__ */
599
600 #endif /* __ASM_POWERPC_CPUTABLE_H */
601