1 /*
2 * Copyright 2014 IBM Corp.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 */
9
10 #ifndef _CXL_H_
11 #define _CXL_H_
12
13 #include <linux/interrupt.h>
14 #include <linux/semaphore.h>
15 #include <linux/device.h>
16 #include <linux/types.h>
17 #include <linux/cdev.h>
18 #include <linux/pid.h>
19 #include <linux/io.h>
20 #include <linux/pci.h>
21 #include <linux/fs.h>
22 #include <asm/cputable.h>
23 #include <asm/mmu.h>
24 #include <asm/reg.h>
25 #include <misc/cxl-base.h>
26
27 #include <misc/cxl.h>
28 #include <uapi/misc/cxl.h>
29
30 extern uint cxl_verbose;
31
32 #define CXL_TIMEOUT 5
33
34 /*
35 * Bump version each time a user API change is made, whether it is
36 * backwards compatible ot not.
37 */
38 #define CXL_API_VERSION 3
39 #define CXL_API_VERSION_COMPATIBLE 1
40
41 /*
42 * Opaque types to avoid accidentally passing registers for the wrong MMIO
43 *
44 * At the end of the day, I'm not married to using typedef here, but it might
45 * (and has!) help avoid bugs like mixing up CXL_PSL_CtxTime and
46 * CXL_PSL_CtxTime_An, or calling cxl_p1n_write instead of cxl_p1_write.
47 *
48 * I'm quite happy if these are changed back to #defines before upstreaming, it
49 * should be little more than a regexp search+replace operation in this file.
50 */
51 typedef struct {
52 const int x;
53 } cxl_p1_reg_t;
54 typedef struct {
55 const int x;
56 } cxl_p1n_reg_t;
57 typedef struct {
58 const int x;
59 } cxl_p2n_reg_t;
60 #define cxl_reg_off(reg) \
61 (reg.x)
62
63 /* Memory maps. Ref CXL Appendix A */
64
65 /* PSL Privilege 1 Memory Map */
66 /* Configuration and Control area - CAIA 1&2 */
67 static const cxl_p1_reg_t CXL_PSL_CtxTime = {0x0000};
68 static const cxl_p1_reg_t CXL_PSL_ErrIVTE = {0x0008};
69 static const cxl_p1_reg_t CXL_PSL_KEY1 = {0x0010};
70 static const cxl_p1_reg_t CXL_PSL_KEY2 = {0x0018};
71 static const cxl_p1_reg_t CXL_PSL_Control = {0x0020};
72 /* Downloading */
73 static const cxl_p1_reg_t CXL_PSL_DLCNTL = {0x0060};
74 static const cxl_p1_reg_t CXL_PSL_DLADDR = {0x0068};
75
76 /* PSL Lookaside Buffer Management Area - CAIA 1 */
77 static const cxl_p1_reg_t CXL_PSL_LBISEL = {0x0080};
78 static const cxl_p1_reg_t CXL_PSL_SLBIE = {0x0088};
79 static const cxl_p1_reg_t CXL_PSL_SLBIA = {0x0090};
80 static const cxl_p1_reg_t CXL_PSL_TLBIE = {0x00A0};
81 static const cxl_p1_reg_t CXL_PSL_TLBIA = {0x00A8};
82 static const cxl_p1_reg_t CXL_PSL_AFUSEL = {0x00B0};
83
84 /* 0x00C0:7EFF Implementation dependent area */
85 /* PSL registers - CAIA 1 */
86 static const cxl_p1_reg_t CXL_PSL_FIR1 = {0x0100};
87 static const cxl_p1_reg_t CXL_PSL_FIR2 = {0x0108};
88 static const cxl_p1_reg_t CXL_PSL_Timebase = {0x0110};
89 static const cxl_p1_reg_t CXL_PSL_VERSION = {0x0118};
90 static const cxl_p1_reg_t CXL_PSL_RESLCKTO = {0x0128};
91 static const cxl_p1_reg_t CXL_PSL_TB_CTLSTAT = {0x0140};
92 static const cxl_p1_reg_t CXL_PSL_FIR_CNTL = {0x0148};
93 static const cxl_p1_reg_t CXL_PSL_DSNDCTL = {0x0150};
94 static const cxl_p1_reg_t CXL_PSL_SNWRALLOC = {0x0158};
95 static const cxl_p1_reg_t CXL_PSL_TRACE = {0x0170};
96 /* XSL registers (Mellanox CX4) */
97 static const cxl_p1_reg_t CXL_XSL_Timebase = {0x0100};
98 static const cxl_p1_reg_t CXL_XSL_TB_CTLSTAT = {0x0108};
99 static const cxl_p1_reg_t CXL_XSL_FEC = {0x0158};
100 static const cxl_p1_reg_t CXL_XSL_DSNCTL = {0x0168};
101 /* PSL registers - CAIA 2 */
102 static const cxl_p1_reg_t CXL_PSL9_CONTROL = {0x0020};
103 static const cxl_p1_reg_t CXL_XSL9_DSNCTL = {0x0168};
104 static const cxl_p1_reg_t CXL_PSL9_FIR1 = {0x0300};
105 static const cxl_p1_reg_t CXL_PSL9_FIR2 = {0x0308};
106 static const cxl_p1_reg_t CXL_PSL9_Timebase = {0x0310};
107 static const cxl_p1_reg_t CXL_PSL9_DEBUG = {0x0320};
108 static const cxl_p1_reg_t CXL_PSL9_FIR_CNTL = {0x0348};
109 static const cxl_p1_reg_t CXL_PSL9_DSNDCTL = {0x0350};
110 static const cxl_p1_reg_t CXL_PSL9_TB_CTLSTAT = {0x0340};
111 static const cxl_p1_reg_t CXL_PSL9_TRACECFG = {0x0368};
112 static const cxl_p1_reg_t CXL_PSL9_APCDEDALLOC = {0x0378};
113 static const cxl_p1_reg_t CXL_PSL9_APCDEDTYPE = {0x0380};
114 static const cxl_p1_reg_t CXL_PSL9_TNR_ADDR = {0x0388};
115 static const cxl_p1_reg_t CXL_PSL9_GP_CT = {0x0398};
116 static const cxl_p1_reg_t CXL_XSL9_IERAT = {0x0588};
117 static const cxl_p1_reg_t CXL_XSL9_ILPP = {0x0590};
118
119 /* 0x7F00:7FFF Reserved PCIe MSI-X Pending Bit Array area */
120 /* 0x8000:FFFF Reserved PCIe MSI-X Table Area */
121
122 /* PSL Slice Privilege 1 Memory Map */
123 /* Configuration Area - CAIA 1&2 */
124 static const cxl_p1n_reg_t CXL_PSL_SR_An = {0x00};
125 static const cxl_p1n_reg_t CXL_PSL_LPID_An = {0x08};
126 static const cxl_p1n_reg_t CXL_PSL_AMBAR_An = {0x10};
127 static const cxl_p1n_reg_t CXL_PSL_SPOffset_An = {0x18};
128 static const cxl_p1n_reg_t CXL_PSL_ID_An = {0x20};
129 static const cxl_p1n_reg_t CXL_PSL_SERR_An = {0x28};
130 /* Memory Management and Lookaside Buffer Management - CAIA 1*/
131 static const cxl_p1n_reg_t CXL_PSL_SDR_An = {0x30};
132 /* Memory Management and Lookaside Buffer Management - CAIA 1&2 */
133 static const cxl_p1n_reg_t CXL_PSL_AMOR_An = {0x38};
134 /* Pointer Area - CAIA 1&2 */
135 static const cxl_p1n_reg_t CXL_HAURP_An = {0x80};
136 static const cxl_p1n_reg_t CXL_PSL_SPAP_An = {0x88};
137 static const cxl_p1n_reg_t CXL_PSL_LLCMD_An = {0x90};
138 /* Control Area - CAIA 1&2 */
139 static const cxl_p1n_reg_t CXL_PSL_SCNTL_An = {0xA0};
140 static const cxl_p1n_reg_t CXL_PSL_CtxTime_An = {0xA8};
141 static const cxl_p1n_reg_t CXL_PSL_IVTE_Offset_An = {0xB0};
142 static const cxl_p1n_reg_t CXL_PSL_IVTE_Limit_An = {0xB8};
143 /* 0xC0:FF Implementation Dependent Area - CAIA 1&2 */
144 static const cxl_p1n_reg_t CXL_PSL_FIR_SLICE_An = {0xC0};
145 static const cxl_p1n_reg_t CXL_AFU_DEBUG_An = {0xC8};
146 /* 0xC0:FF Implementation Dependent Area - CAIA 1 */
147 static const cxl_p1n_reg_t CXL_PSL_APCALLOC_A = {0xD0};
148 static const cxl_p1n_reg_t CXL_PSL_COALLOC_A = {0xD8};
149 static const cxl_p1n_reg_t CXL_PSL_RXCTL_A = {0xE0};
150 static const cxl_p1n_reg_t CXL_PSL_SLICE_TRACE = {0xE8};
151
152 /* PSL Slice Privilege 2 Memory Map */
153 /* Configuration and Control Area - CAIA 1&2 */
154 static const cxl_p2n_reg_t CXL_PSL_PID_TID_An = {0x000};
155 static const cxl_p2n_reg_t CXL_CSRP_An = {0x008};
156 /* Configuration and Control Area - CAIA 1 */
157 static const cxl_p2n_reg_t CXL_AURP0_An = {0x010};
158 static const cxl_p2n_reg_t CXL_AURP1_An = {0x018};
159 static const cxl_p2n_reg_t CXL_SSTP0_An = {0x020};
160 static const cxl_p2n_reg_t CXL_SSTP1_An = {0x028};
161 /* Configuration and Control Area - CAIA 1 */
162 static const cxl_p2n_reg_t CXL_PSL_AMR_An = {0x030};
163 /* Segment Lookaside Buffer Management - CAIA 1 */
164 static const cxl_p2n_reg_t CXL_SLBIE_An = {0x040};
165 static const cxl_p2n_reg_t CXL_SLBIA_An = {0x048};
166 static const cxl_p2n_reg_t CXL_SLBI_Select_An = {0x050};
167 /* Interrupt Registers - CAIA 1&2 */
168 static const cxl_p2n_reg_t CXL_PSL_DSISR_An = {0x060};
169 static const cxl_p2n_reg_t CXL_PSL_DAR_An = {0x068};
170 static const cxl_p2n_reg_t CXL_PSL_DSR_An = {0x070};
171 static const cxl_p2n_reg_t CXL_PSL_TFC_An = {0x078};
172 static const cxl_p2n_reg_t CXL_PSL_PEHandle_An = {0x080};
173 static const cxl_p2n_reg_t CXL_PSL_ErrStat_An = {0x088};
174 /* AFU Registers - CAIA 1&2 */
175 static const cxl_p2n_reg_t CXL_AFU_Cntl_An = {0x090};
176 static const cxl_p2n_reg_t CXL_AFU_ERR_An = {0x098};
177 /* Work Element Descriptor - CAIA 1&2 */
178 static const cxl_p2n_reg_t CXL_PSL_WED_An = {0x0A0};
179 /* 0x0C0:FFF Implementation Dependent Area */
180
181 #define CXL_PSL_SPAP_Addr 0x0ffffffffffff000ULL
182 #define CXL_PSL_SPAP_Size 0x0000000000000ff0ULL
183 #define CXL_PSL_SPAP_Size_Shift 4
184 #define CXL_PSL_SPAP_V 0x0000000000000001ULL
185
186 /****** CXL_PSL_Control ****************************************************/
187 #define CXL_PSL_Control_tb (0x1ull << (63-63))
188 #define CXL_PSL_Control_Fr (0x1ull << (63-31))
189 #define CXL_PSL_Control_Fs_MASK (0x3ull << (63-29))
190 #define CXL_PSL_Control_Fs_Complete (0x3ull << (63-29))
191
192 /****** CXL_PSL_DLCNTL *****************************************************/
193 #define CXL_PSL_DLCNTL_D (0x1ull << (63-28))
194 #define CXL_PSL_DLCNTL_C (0x1ull << (63-29))
195 #define CXL_PSL_DLCNTL_E (0x1ull << (63-30))
196 #define CXL_PSL_DLCNTL_S (0x1ull << (63-31))
197 #define CXL_PSL_DLCNTL_CE (CXL_PSL_DLCNTL_C | CXL_PSL_DLCNTL_E)
198 #define CXL_PSL_DLCNTL_DCES (CXL_PSL_DLCNTL_D | CXL_PSL_DLCNTL_CE | CXL_PSL_DLCNTL_S)
199
200 /****** CXL_PSL_SR_An ******************************************************/
201 #define CXL_PSL_SR_An_SF MSR_SF /* 64bit */
202 #define CXL_PSL_SR_An_TA (1ull << (63-1)) /* Tags active, GA1: 0 */
203 #define CXL_PSL_SR_An_HV MSR_HV /* Hypervisor, GA1: 0 */
204 #define CXL_PSL_SR_An_XLAT_hpt (0ull << (63-6))/* Hashed page table (HPT) mode */
205 #define CXL_PSL_SR_An_XLAT_roh (2ull << (63-6))/* Radix on HPT mode */
206 #define CXL_PSL_SR_An_XLAT_ror (3ull << (63-6))/* Radix on Radix mode */
207 #define CXL_PSL_SR_An_BOT (1ull << (63-10)) /* Use the in-memory segment table */
208 #define CXL_PSL_SR_An_PR MSR_PR /* Problem state, GA1: 1 */
209 #define CXL_PSL_SR_An_ISL (1ull << (63-53)) /* Ignore Segment Large Page */
210 #define CXL_PSL_SR_An_TC (1ull << (63-54)) /* Page Table secondary hash */
211 #define CXL_PSL_SR_An_US (1ull << (63-56)) /* User state, GA1: X */
212 #define CXL_PSL_SR_An_SC (1ull << (63-58)) /* Segment Table secondary hash */
213 #define CXL_PSL_SR_An_R MSR_DR /* Relocate, GA1: 1 */
214 #define CXL_PSL_SR_An_MP (1ull << (63-62)) /* Master Process */
215 #define CXL_PSL_SR_An_LE (1ull << (63-63)) /* Little Endian */
216
217 /****** CXL_PSL_ID_An ****************************************************/
218 #define CXL_PSL_ID_An_F (1ull << (63-31))
219 #define CXL_PSL_ID_An_L (1ull << (63-30))
220
221 /****** CXL_PSL_SERR_An ****************************************************/
222 #define CXL_PSL_SERR_An_afuto (1ull << (63-0))
223 #define CXL_PSL_SERR_An_afudis (1ull << (63-1))
224 #define CXL_PSL_SERR_An_afuov (1ull << (63-2))
225 #define CXL_PSL_SERR_An_badsrc (1ull << (63-3))
226 #define CXL_PSL_SERR_An_badctx (1ull << (63-4))
227 #define CXL_PSL_SERR_An_llcmdis (1ull << (63-5))
228 #define CXL_PSL_SERR_An_llcmdto (1ull << (63-6))
229 #define CXL_PSL_SERR_An_afupar (1ull << (63-7))
230 #define CXL_PSL_SERR_An_afudup (1ull << (63-8))
231 #define CXL_PSL_SERR_An_IRQS ( \
232 CXL_PSL_SERR_An_afuto | CXL_PSL_SERR_An_afudis | CXL_PSL_SERR_An_afuov | \
233 CXL_PSL_SERR_An_badsrc | CXL_PSL_SERR_An_badctx | CXL_PSL_SERR_An_llcmdis | \
234 CXL_PSL_SERR_An_llcmdto | CXL_PSL_SERR_An_afupar | CXL_PSL_SERR_An_afudup)
235 #define CXL_PSL_SERR_An_afuto_mask (1ull << (63-32))
236 #define CXL_PSL_SERR_An_afudis_mask (1ull << (63-33))
237 #define CXL_PSL_SERR_An_afuov_mask (1ull << (63-34))
238 #define CXL_PSL_SERR_An_badsrc_mask (1ull << (63-35))
239 #define CXL_PSL_SERR_An_badctx_mask (1ull << (63-36))
240 #define CXL_PSL_SERR_An_llcmdis_mask (1ull << (63-37))
241 #define CXL_PSL_SERR_An_llcmdto_mask (1ull << (63-38))
242 #define CXL_PSL_SERR_An_afupar_mask (1ull << (63-39))
243 #define CXL_PSL_SERR_An_afudup_mask (1ull << (63-40))
244 #define CXL_PSL_SERR_An_IRQ_MASKS ( \
245 CXL_PSL_SERR_An_afuto_mask | CXL_PSL_SERR_An_afudis_mask | CXL_PSL_SERR_An_afuov_mask | \
246 CXL_PSL_SERR_An_badsrc_mask | CXL_PSL_SERR_An_badctx_mask | CXL_PSL_SERR_An_llcmdis_mask | \
247 CXL_PSL_SERR_An_llcmdto_mask | CXL_PSL_SERR_An_afupar_mask | CXL_PSL_SERR_An_afudup_mask)
248
249 #define CXL_PSL_SERR_An_AE (1ull << (63-30))
250
251 /****** CXL_PSL_SCNTL_An ****************************************************/
252 #define CXL_PSL_SCNTL_An_CR (0x1ull << (63-15))
253 /* Programming Modes: */
254 #define CXL_PSL_SCNTL_An_PM_MASK (0xffffull << (63-31))
255 #define CXL_PSL_SCNTL_An_PM_Shared (0x0000ull << (63-31))
256 #define CXL_PSL_SCNTL_An_PM_OS (0x0001ull << (63-31))
257 #define CXL_PSL_SCNTL_An_PM_Process (0x0002ull << (63-31))
258 #define CXL_PSL_SCNTL_An_PM_AFU (0x0004ull << (63-31))
259 #define CXL_PSL_SCNTL_An_PM_AFU_PBT (0x0104ull << (63-31))
260 /* Purge Status (ro) */
261 #define CXL_PSL_SCNTL_An_Ps_MASK (0x3ull << (63-39))
262 #define CXL_PSL_SCNTL_An_Ps_Pending (0x1ull << (63-39))
263 #define CXL_PSL_SCNTL_An_Ps_Complete (0x3ull << (63-39))
264 /* Purge */
265 #define CXL_PSL_SCNTL_An_Pc (0x1ull << (63-48))
266 /* Suspend Status (ro) */
267 #define CXL_PSL_SCNTL_An_Ss_MASK (0x3ull << (63-55))
268 #define CXL_PSL_SCNTL_An_Ss_Pending (0x1ull << (63-55))
269 #define CXL_PSL_SCNTL_An_Ss_Complete (0x3ull << (63-55))
270 /* Suspend Control */
271 #define CXL_PSL_SCNTL_An_Sc (0x1ull << (63-63))
272
273 /* AFU Slice Enable Status (ro) */
274 #define CXL_AFU_Cntl_An_ES_MASK (0x7ull << (63-2))
275 #define CXL_AFU_Cntl_An_ES_Disabled (0x0ull << (63-2))
276 #define CXL_AFU_Cntl_An_ES_Enabled (0x4ull << (63-2))
277 /* AFU Slice Enable */
278 #define CXL_AFU_Cntl_An_E (0x1ull << (63-3))
279 /* AFU Slice Reset status (ro) */
280 #define CXL_AFU_Cntl_An_RS_MASK (0x3ull << (63-5))
281 #define CXL_AFU_Cntl_An_RS_Pending (0x1ull << (63-5))
282 #define CXL_AFU_Cntl_An_RS_Complete (0x2ull << (63-5))
283 /* AFU Slice Reset */
284 #define CXL_AFU_Cntl_An_RA (0x1ull << (63-7))
285
286 /****** CXL_SSTP0/1_An ******************************************************/
287 /* These top bits are for the segment that CONTAINS the segment table */
288 #define CXL_SSTP0_An_B_SHIFT SLB_VSID_SSIZE_SHIFT
289 #define CXL_SSTP0_An_KS (1ull << (63-2))
290 #define CXL_SSTP0_An_KP (1ull << (63-3))
291 #define CXL_SSTP0_An_N (1ull << (63-4))
292 #define CXL_SSTP0_An_L (1ull << (63-5))
293 #define CXL_SSTP0_An_C (1ull << (63-6))
294 #define CXL_SSTP0_An_TA (1ull << (63-7))
295 #define CXL_SSTP0_An_LP_SHIFT (63-9) /* 2 Bits */
296 /* And finally, the virtual address & size of the segment table: */
297 #define CXL_SSTP0_An_SegTableSize_SHIFT (63-31) /* 12 Bits */
298 #define CXL_SSTP0_An_SegTableSize_MASK \
299 (((1ull << 12) - 1) << CXL_SSTP0_An_SegTableSize_SHIFT)
300 #define CXL_SSTP0_An_STVA_U_MASK ((1ull << (63-49))-1)
301 #define CXL_SSTP1_An_STVA_L_MASK (~((1ull << (63-55))-1))
302 #define CXL_SSTP1_An_V (1ull << (63-63))
303
304 /****** CXL_PSL_SLBIE_[An] - CAIA 1 **************************************************/
305 /* write: */
306 #define CXL_SLBIE_C PPC_BIT(36) /* Class */
307 #define CXL_SLBIE_SS PPC_BITMASK(37, 38) /* Segment Size */
308 #define CXL_SLBIE_SS_SHIFT PPC_BITLSHIFT(38)
309 #define CXL_SLBIE_TA PPC_BIT(38) /* Tags Active */
310 /* read: */
311 #define CXL_SLBIE_MAX PPC_BITMASK(24, 31)
312 #define CXL_SLBIE_PENDING PPC_BITMASK(56, 63)
313
314 /****** Common to all CXL_TLBIA/SLBIA_[An] - CAIA 1 **********************************/
315 #define CXL_TLB_SLB_P (1ull) /* Pending (read) */
316
317 /****** Common to all CXL_TLB/SLB_IA/IE_[An] registers - CAIA 1 **********************/
318 #define CXL_TLB_SLB_IQ_ALL (0ull) /* Inv qualifier */
319 #define CXL_TLB_SLB_IQ_LPID (1ull) /* Inv qualifier */
320 #define CXL_TLB_SLB_IQ_LPIDPID (3ull) /* Inv qualifier */
321
322 /****** CXL_PSL_AFUSEL ******************************************************/
323 #define CXL_PSL_AFUSEL_A (1ull << (63-55)) /* Adapter wide invalidates affect all AFUs */
324
325 /****** CXL_PSL_DSISR_An - CAIA 1 ****************************************************/
326 #define CXL_PSL_DSISR_An_DS (1ull << (63-0)) /* Segment not found */
327 #define CXL_PSL_DSISR_An_DM (1ull << (63-1)) /* PTE not found (See also: M) or protection fault */
328 #define CXL_PSL_DSISR_An_ST (1ull << (63-2)) /* Segment Table PTE not found */
329 #define CXL_PSL_DSISR_An_UR (1ull << (63-3)) /* AURP PTE not found */
330 #define CXL_PSL_DSISR_TRANS (CXL_PSL_DSISR_An_DS | CXL_PSL_DSISR_An_DM | CXL_PSL_DSISR_An_ST | CXL_PSL_DSISR_An_UR)
331 #define CXL_PSL_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
332 #define CXL_PSL_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
333 #define CXL_PSL_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
334 #define CXL_PSL_DSISR_PENDING (CXL_PSL_DSISR_TRANS | CXL_PSL_DSISR_An_PE | CXL_PSL_DSISR_An_AE | CXL_PSL_DSISR_An_OC)
335 /* NOTE: Bits 32:63 are undefined if DSISR[DS] = 1 */
336 #define CXL_PSL_DSISR_An_M DSISR_NOHPTE /* PTE not found */
337 #define CXL_PSL_DSISR_An_P DSISR_PROTFAULT /* Storage protection violation */
338 #define CXL_PSL_DSISR_An_A (1ull << (63-37)) /* AFU lock access to write through or cache inhibited storage */
339 #define CXL_PSL_DSISR_An_S DSISR_ISSTORE /* Access was afu_wr or afu_zero */
340 #define CXL_PSL_DSISR_An_K DSISR_KEYFAULT /* Access not permitted by virtual page class key protection */
341
342 /****** CXL_PSL_DSISR_An - CAIA 2 ****************************************************/
343 #define CXL_PSL9_DSISR_An_TF (1ull << (63-3)) /* Translation fault */
344 #define CXL_PSL9_DSISR_An_PE (1ull << (63-4)) /* PSL Error (implementation specific) */
345 #define CXL_PSL9_DSISR_An_AE (1ull << (63-5)) /* AFU Error */
346 #define CXL_PSL9_DSISR_An_OC (1ull << (63-6)) /* OS Context Warning */
347 #define CXL_PSL9_DSISR_An_S (1ull << (63-38)) /* TF for a write operation */
348 #define CXL_PSL9_DSISR_PENDING (CXL_PSL9_DSISR_An_TF | CXL_PSL9_DSISR_An_PE | CXL_PSL9_DSISR_An_AE | CXL_PSL9_DSISR_An_OC)
349 /*
350 * NOTE: Bits 56:63 (Checkout Response Status) are valid when DSISR_An[TF] = 1
351 * Status (0:7) Encoding
352 */
353 #define CXL_PSL9_DSISR_An_CO_MASK 0x00000000000000ffULL
354 #define CXL_PSL9_DSISR_An_SF 0x0000000000000080ULL /* Segment Fault 0b10000000 */
355 #define CXL_PSL9_DSISR_An_PF_SLR 0x0000000000000088ULL /* PTE not found (Single Level Radix) 0b10001000 */
356 #define CXL_PSL9_DSISR_An_PF_RGC 0x000000000000008CULL /* PTE not found (Radix Guest (child)) 0b10001100 */
357 #define CXL_PSL9_DSISR_An_PF_RGP 0x0000000000000090ULL /* PTE not found (Radix Guest (parent)) 0b10010000 */
358 #define CXL_PSL9_DSISR_An_PF_HRH 0x0000000000000094ULL /* PTE not found (HPT/Radix Host) 0b10010100 */
359 #define CXL_PSL9_DSISR_An_PF_STEG 0x000000000000009CULL /* PTE not found (STEG VA) 0b10011100 */
360 #define CXL_PSL9_DSISR_An_URTCH 0x00000000000000B4ULL /* Unsupported Radix Tree Configuration 0b10110100 */
361
362 /****** CXL_PSL_TFC_An ******************************************************/
363 #define CXL_PSL_TFC_An_A (1ull << (63-28)) /* Acknowledge non-translation fault */
364 #define CXL_PSL_TFC_An_C (1ull << (63-29)) /* Continue (abort transaction) */
365 #define CXL_PSL_TFC_An_AE (1ull << (63-30)) /* Restart PSL with address error */
366 #define CXL_PSL_TFC_An_R (1ull << (63-31)) /* Restart PSL transaction */
367
368 /****** CXL_PSL_DEBUG *****************************************************/
369 #define CXL_PSL_DEBUG_CDC (1ull << (63-27)) /* Coherent Data cache support */
370
371 /****** CXL_XSL9_IERAT_ERAT - CAIA 2 **********************************/
372 #define CXL_XSL9_IERAT_MLPID (1ull << (63-0)) /* Match LPID */
373 #define CXL_XSL9_IERAT_MPID (1ull << (63-1)) /* Match PID */
374 #define CXL_XSL9_IERAT_PRS (1ull << (63-4)) /* PRS bit for Radix invalidations */
375 #define CXL_XSL9_IERAT_INVR (1ull << (63-3)) /* Invalidate Radix */
376 #define CXL_XSL9_IERAT_IALL (1ull << (63-8)) /* Invalidate All */
377 #define CXL_XSL9_IERAT_IINPROG (1ull << (63-63)) /* Invalidate in progress */
378
379 /* cxl_process_element->software_status */
380 #define CXL_PE_SOFTWARE_STATE_V (1ul << (31 - 0)) /* Valid */
381 #define CXL_PE_SOFTWARE_STATE_C (1ul << (31 - 29)) /* Complete */
382 #define CXL_PE_SOFTWARE_STATE_S (1ul << (31 - 30)) /* Suspend */
383 #define CXL_PE_SOFTWARE_STATE_T (1ul << (31 - 31)) /* Terminate */
384
385 /****** CXL_PSL_RXCTL_An (Implementation Specific) **************************
386 * Controls AFU Hang Pulse, which sets the timeout for the AFU to respond to
387 * the PSL for any response (except MMIO). Timeouts will occur between 1x to 2x
388 * of the hang pulse frequency.
389 */
390 #define CXL_PSL_RXCTL_AFUHP_4S 0x7000000000000000ULL
391
392 /* SPA->sw_command_status */
393 #define CXL_SPA_SW_CMD_MASK 0xffff000000000000ULL
394 #define CXL_SPA_SW_CMD_TERMINATE 0x0001000000000000ULL
395 #define CXL_SPA_SW_CMD_REMOVE 0x0002000000000000ULL
396 #define CXL_SPA_SW_CMD_SUSPEND 0x0003000000000000ULL
397 #define CXL_SPA_SW_CMD_RESUME 0x0004000000000000ULL
398 #define CXL_SPA_SW_CMD_ADD 0x0005000000000000ULL
399 #define CXL_SPA_SW_CMD_UPDATE 0x0006000000000000ULL
400 #define CXL_SPA_SW_STATE_MASK 0x0000ffff00000000ULL
401 #define CXL_SPA_SW_STATE_TERMINATED 0x0000000100000000ULL
402 #define CXL_SPA_SW_STATE_REMOVED 0x0000000200000000ULL
403 #define CXL_SPA_SW_STATE_SUSPENDED 0x0000000300000000ULL
404 #define CXL_SPA_SW_STATE_RESUMED 0x0000000400000000ULL
405 #define CXL_SPA_SW_STATE_ADDED 0x0000000500000000ULL
406 #define CXL_SPA_SW_STATE_UPDATED 0x0000000600000000ULL
407 #define CXL_SPA_SW_PSL_ID_MASK 0x00000000ffff0000ULL
408 #define CXL_SPA_SW_LINK_MASK 0x000000000000ffffULL
409
410 #define CXL_MAX_SLICES 4
411 #define MAX_AFU_MMIO_REGS 3
412
413 #define CXL_MODE_TIME_SLICED 0x4
414 #define CXL_SUPPORTED_MODES (CXL_MODE_DEDICATED | CXL_MODE_DIRECTED)
415
416 #define CXL_DEV_MINORS 13 /* 1 control + 4 AFUs * 3 (dedicated/master/shared) */
417 #define CXL_CARD_MINOR(adapter) (adapter->adapter_num * CXL_DEV_MINORS)
418 #define CXL_DEVT_ADAPTER(dev) (MINOR(dev) / CXL_DEV_MINORS)
419
420 enum cxl_context_status {
421 CLOSED,
422 OPENED,
423 STARTED
424 };
425
426 enum prefault_modes {
427 CXL_PREFAULT_NONE,
428 CXL_PREFAULT_WED,
429 CXL_PREFAULT_ALL,
430 };
431
432 enum cxl_attrs {
433 CXL_ADAPTER_ATTRS,
434 CXL_AFU_MASTER_ATTRS,
435 CXL_AFU_ATTRS,
436 };
437
438 struct cxl_sste {
439 __be64 esid_data;
440 __be64 vsid_data;
441 };
442
443 #define to_cxl_adapter(d) container_of(d, struct cxl, dev)
444 #define to_cxl_afu(d) container_of(d, struct cxl_afu, dev)
445
446 struct cxl_afu_native {
447 void __iomem *p1n_mmio;
448 void __iomem *afu_desc_mmio;
449 irq_hw_number_t psl_hwirq;
450 unsigned int psl_virq;
451 struct mutex spa_mutex;
452 /*
453 * Only the first part of the SPA is used for the process element
454 * linked list. The only other part that software needs to worry about
455 * is sw_command_status, which we store a separate pointer to.
456 * Everything else in the SPA is only used by hardware
457 */
458 struct cxl_process_element *spa;
459 __be64 *sw_command_status;
460 unsigned int spa_size;
461 int spa_order;
462 int spa_max_procs;
463 u64 pp_offset;
464 };
465
466 struct cxl_afu_guest {
467 struct cxl_afu *parent;
468 u64 handle;
469 phys_addr_t p2n_phys;
470 u64 p2n_size;
471 int max_ints;
472 bool handle_err;
473 struct delayed_work work_err;
474 int previous_state;
475 };
476
477 struct cxl_afu {
478 struct cxl_afu_native *native;
479 struct cxl_afu_guest *guest;
480 irq_hw_number_t serr_hwirq;
481 unsigned int serr_virq;
482 char *psl_irq_name;
483 char *err_irq_name;
484 void __iomem *p2n_mmio;
485 phys_addr_t psn_phys;
486 u64 pp_size;
487
488 struct cxl *adapter;
489 struct device dev;
490 struct cdev afu_cdev_s, afu_cdev_m, afu_cdev_d;
491 struct device *chardev_s, *chardev_m, *chardev_d;
492 struct idr contexts_idr;
493 struct dentry *debugfs;
494 struct mutex contexts_lock;
495 spinlock_t afu_cntl_lock;
496
497 /* -1: AFU deconfigured/locked, >= 0: number of readers */
498 atomic_t configured_state;
499
500 /* AFU error buffer fields and bin attribute for sysfs */
501 u64 eb_len, eb_offset;
502 struct bin_attribute attr_eb;
503
504 /* pointer to the vphb */
505 struct pci_controller *phb;
506
507 int pp_irqs;
508 int irqs_max;
509 int num_procs;
510 int max_procs_virtualised;
511 int slice;
512 int modes_supported;
513 int current_mode;
514 int crs_num;
515 u64 crs_len;
516 u64 crs_offset;
517 struct list_head crs;
518 enum prefault_modes prefault_mode;
519 bool psa;
520 bool pp_psa;
521 bool enabled;
522 };
523
524
525 struct cxl_irq_name {
526 struct list_head list;
527 char *name;
528 };
529
530 struct irq_avail {
531 irq_hw_number_t offset;
532 irq_hw_number_t range;
533 unsigned long *bitmap;
534 };
535
536 /*
537 * This is a cxl context. If the PSL is in dedicated mode, there will be one
538 * of these per AFU. If in AFU directed there can be lots of these.
539 */
540 struct cxl_context {
541 struct cxl_afu *afu;
542
543 /* Problem state MMIO */
544 phys_addr_t psn_phys;
545 u64 psn_size;
546
547 /* Used to unmap any mmaps when force detaching */
548 struct address_space *mapping;
549 struct mutex mapping_lock;
550 struct page *ff_page;
551 bool mmio_err_ff;
552 bool kernelapi;
553
554 spinlock_t sste_lock; /* Protects segment table entries */
555 struct cxl_sste *sstp;
556 u64 sstp0, sstp1;
557 unsigned int sst_size, sst_lru;
558
559 wait_queue_head_t wq;
560 /* use mm context associated with this pid for ds faults */
561 struct pid *pid;
562 spinlock_t lock; /* Protects pending_irq_mask, pending_fault and fault_addr */
563 /* Only used in PR mode */
564 u64 process_token;
565
566 /* driver private data */
567 void *priv;
568
569 unsigned long *irq_bitmap; /* Accessed from IRQ context */
570 struct cxl_irq_ranges irqs;
571 struct list_head irq_names;
572 u64 fault_addr;
573 u64 fault_dsisr;
574 u64 afu_err;
575
576 /*
577 * This status and it's lock pretects start and detach context
578 * from racing. It also prevents detach from racing with
579 * itself
580 */
581 enum cxl_context_status status;
582 struct mutex status_mutex;
583
584
585 /* XXX: Is it possible to need multiple work items at once? */
586 struct work_struct fault_work;
587 u64 dsisr;
588 u64 dar;
589
590 struct cxl_process_element *elem;
591
592 /*
593 * pe is the process element handle, assigned by this driver when the
594 * context is initialized.
595 *
596 * external_pe is the PE shown outside of cxl.
597 * On bare-metal, pe=external_pe, because we decide what the handle is.
598 * In a guest, we only find out about the pe used by pHyp when the
599 * context is attached, and that's the value we want to report outside
600 * of cxl.
601 */
602 int pe;
603 int external_pe;
604
605 u32 irq_count;
606 bool pe_inserted;
607 bool master;
608 bool kernel;
609 bool real_mode;
610 bool pending_irq;
611 bool pending_fault;
612 bool pending_afu_err;
613
614 /* Used by AFU drivers for driver specific event delivery */
615 struct cxl_afu_driver_ops *afu_driver_ops;
616 atomic_t afu_driver_events;
617
618 struct rcu_head rcu;
619
620 /*
621 * Only used when more interrupts are allocated via
622 * pci_enable_msix_range than are supported in the default context, to
623 * use additional contexts to overcome the limitation. i.e. Mellanox
624 * CX4 only:
625 */
626 struct list_head extra_irq_contexts;
627
628 struct mm_struct *mm;
629 };
630
631 struct cxl_irq_info;
632
633 struct cxl_service_layer_ops {
634 int (*adapter_regs_init)(struct cxl *adapter, struct pci_dev *dev);
635 int (*invalidate_all)(struct cxl *adapter);
636 int (*afu_regs_init)(struct cxl_afu *afu);
637 int (*sanitise_afu_regs)(struct cxl_afu *afu);
638 int (*register_serr_irq)(struct cxl_afu *afu);
639 void (*release_serr_irq)(struct cxl_afu *afu);
640 irqreturn_t (*handle_interrupt)(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
641 irqreturn_t (*fail_irq)(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
642 int (*activate_dedicated_process)(struct cxl_afu *afu);
643 int (*attach_afu_directed)(struct cxl_context *ctx, u64 wed, u64 amr);
644 int (*attach_dedicated_process)(struct cxl_context *ctx, u64 wed, u64 amr);
645 void (*update_dedicated_ivtes)(struct cxl_context *ctx);
646 void (*debugfs_add_adapter_regs)(struct cxl *adapter, struct dentry *dir);
647 void (*debugfs_add_afu_regs)(struct cxl_afu *afu, struct dentry *dir);
648 void (*psl_irq_dump_registers)(struct cxl_context *ctx);
649 void (*err_irq_dump_registers)(struct cxl *adapter);
650 void (*debugfs_stop_trace)(struct cxl *adapter);
651 void (*write_timebase_ctrl)(struct cxl *adapter);
652 u64 (*timebase_read)(struct cxl *adapter);
653 int capi_mode;
654 bool needs_reset_before_disable;
655 };
656
657 struct cxl_native {
658 u64 afu_desc_off;
659 u64 afu_desc_size;
660 void __iomem *p1_mmio;
661 void __iomem *p2_mmio;
662 irq_hw_number_t err_hwirq;
663 unsigned int err_virq;
664 u64 ps_off;
665 bool no_data_cache; /* set if no data cache on the card */
666 const struct cxl_service_layer_ops *sl_ops;
667 };
668
669 struct cxl_guest {
670 struct platform_device *pdev;
671 int irq_nranges;
672 struct cdev cdev;
673 irq_hw_number_t irq_base_offset;
674 struct irq_avail *irq_avail;
675 spinlock_t irq_alloc_lock;
676 u64 handle;
677 char *status;
678 u16 vendor;
679 u16 device;
680 u16 subsystem_vendor;
681 u16 subsystem;
682 };
683
684 struct cxl {
685 struct cxl_native *native;
686 struct cxl_guest *guest;
687 spinlock_t afu_list_lock;
688 struct cxl_afu *afu[CXL_MAX_SLICES];
689 struct device dev;
690 struct dentry *trace;
691 struct dentry *psl_err_chk;
692 struct dentry *debugfs;
693 char *irq_name;
694 struct bin_attribute cxl_attr;
695 int adapter_num;
696 int user_irqs;
697 int min_pe;
698 u64 ps_size;
699 u16 psl_rev;
700 u16 base_image;
701 u8 vsec_status;
702 u8 caia_major;
703 u8 caia_minor;
704 u8 slices;
705 bool user_image_loaded;
706 bool perst_loads_image;
707 bool perst_select_user;
708 bool perst_same_image;
709 bool psl_timebase_synced;
710
711 /*
712 * number of contexts mapped on to this card. Possible values are:
713 * >0: Number of contexts mapped and new one can be mapped.
714 * 0: No active contexts and new ones can be mapped.
715 * -1: No contexts mapped and new ones cannot be mapped.
716 */
717 atomic_t contexts_num;
718 };
719
720 int cxl_pci_alloc_one_irq(struct cxl *adapter);
721 void cxl_pci_release_one_irq(struct cxl *adapter, int hwirq);
722 int cxl_pci_alloc_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter, unsigned int num);
723 void cxl_pci_release_irq_ranges(struct cxl_irq_ranges *irqs, struct cxl *adapter);
724 int cxl_pci_setup_irq(struct cxl *adapter, unsigned int hwirq, unsigned int virq);
725 int cxl_update_image_control(struct cxl *adapter);
726 int cxl_pci_reset(struct cxl *adapter);
727 void cxl_pci_release_afu(struct device *dev);
728 ssize_t cxl_pci_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
729
730 /* common == phyp + powernv - CAIA 1&2 */
731 struct cxl_process_element_common {
732 __be32 tid;
733 __be32 pid;
734 __be64 csrp;
735 union {
736 struct {
737 __be64 aurp0;
738 __be64 aurp1;
739 __be64 sstp0;
740 __be64 sstp1;
741 } psl8; /* CAIA 1 */
742 struct {
743 u8 reserved2[8];
744 u8 reserved3[8];
745 u8 reserved4[8];
746 u8 reserved5[8];
747 } psl9; /* CAIA 2 */
748 } u;
749 __be64 amr;
750 u8 reserved6[4];
751 __be64 wed;
752 } __packed;
753
754 /* just powernv - CAIA 1&2 */
755 struct cxl_process_element {
756 __be64 sr;
757 __be64 SPOffset;
758 union {
759 __be64 sdr; /* CAIA 1 */
760 u8 reserved1[8]; /* CAIA 2 */
761 } u;
762 __be64 haurp;
763 __be32 ctxtime;
764 __be16 ivte_offsets[4];
765 __be16 ivte_ranges[4];
766 __be32 lpid;
767 struct cxl_process_element_common common;
768 __be32 software_state;
769 } __packed;
770
cxl_adapter_link_ok(struct cxl * cxl,struct cxl_afu * afu)771 static inline bool cxl_adapter_link_ok(struct cxl *cxl, struct cxl_afu *afu)
772 {
773 struct pci_dev *pdev;
774
775 if (cpu_has_feature(CPU_FTR_HVMODE)) {
776 pdev = to_pci_dev(cxl->dev.parent);
777 return !pci_channel_offline(pdev);
778 }
779 return true;
780 }
781
_cxl_p1_addr(struct cxl * cxl,cxl_p1_reg_t reg)782 static inline void __iomem *_cxl_p1_addr(struct cxl *cxl, cxl_p1_reg_t reg)
783 {
784 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
785 return cxl->native->p1_mmio + cxl_reg_off(reg);
786 }
787
cxl_p1_write(struct cxl * cxl,cxl_p1_reg_t reg,u64 val)788 static inline void cxl_p1_write(struct cxl *cxl, cxl_p1_reg_t reg, u64 val)
789 {
790 if (likely(cxl_adapter_link_ok(cxl, NULL)))
791 out_be64(_cxl_p1_addr(cxl, reg), val);
792 }
793
cxl_p1_read(struct cxl * cxl,cxl_p1_reg_t reg)794 static inline u64 cxl_p1_read(struct cxl *cxl, cxl_p1_reg_t reg)
795 {
796 if (likely(cxl_adapter_link_ok(cxl, NULL)))
797 return in_be64(_cxl_p1_addr(cxl, reg));
798 else
799 return ~0ULL;
800 }
801
_cxl_p1n_addr(struct cxl_afu * afu,cxl_p1n_reg_t reg)802 static inline void __iomem *_cxl_p1n_addr(struct cxl_afu *afu, cxl_p1n_reg_t reg)
803 {
804 WARN_ON(!cpu_has_feature(CPU_FTR_HVMODE));
805 return afu->native->p1n_mmio + cxl_reg_off(reg);
806 }
807
cxl_p1n_write(struct cxl_afu * afu,cxl_p1n_reg_t reg,u64 val)808 static inline void cxl_p1n_write(struct cxl_afu *afu, cxl_p1n_reg_t reg, u64 val)
809 {
810 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
811 out_be64(_cxl_p1n_addr(afu, reg), val);
812 }
813
cxl_p1n_read(struct cxl_afu * afu,cxl_p1n_reg_t reg)814 static inline u64 cxl_p1n_read(struct cxl_afu *afu, cxl_p1n_reg_t reg)
815 {
816 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
817 return in_be64(_cxl_p1n_addr(afu, reg));
818 else
819 return ~0ULL;
820 }
821
_cxl_p2n_addr(struct cxl_afu * afu,cxl_p2n_reg_t reg)822 static inline void __iomem *_cxl_p2n_addr(struct cxl_afu *afu, cxl_p2n_reg_t reg)
823 {
824 return afu->p2n_mmio + cxl_reg_off(reg);
825 }
826
cxl_p2n_write(struct cxl_afu * afu,cxl_p2n_reg_t reg,u64 val)827 static inline void cxl_p2n_write(struct cxl_afu *afu, cxl_p2n_reg_t reg, u64 val)
828 {
829 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
830 out_be64(_cxl_p2n_addr(afu, reg), val);
831 }
832
cxl_p2n_read(struct cxl_afu * afu,cxl_p2n_reg_t reg)833 static inline u64 cxl_p2n_read(struct cxl_afu *afu, cxl_p2n_reg_t reg)
834 {
835 if (likely(cxl_adapter_link_ok(afu->adapter, afu)))
836 return in_be64(_cxl_p2n_addr(afu, reg));
837 else
838 return ~0ULL;
839 }
840
cxl_is_power8(void)841 static inline bool cxl_is_power8(void)
842 {
843 if ((pvr_version_is(PVR_POWER8E)) ||
844 (pvr_version_is(PVR_POWER8NVL)) ||
845 (pvr_version_is(PVR_POWER8)))
846 return true;
847 return false;
848 }
849
cxl_is_power9(void)850 static inline bool cxl_is_power9(void)
851 {
852 if (pvr_version_is(PVR_POWER9))
853 return true;
854 return false;
855 }
856
cxl_is_power9_dd1(void)857 static inline bool cxl_is_power9_dd1(void)
858 {
859 if ((pvr_version_is(PVR_POWER9)) &&
860 cpu_has_feature(CPU_FTR_POWER9_DD1))
861 return true;
862 return false;
863 }
864
865 ssize_t cxl_pci_afu_read_err_buffer(struct cxl_afu *afu, char *buf,
866 loff_t off, size_t count);
867
868 /* Internal functions wrapped in cxl_base to allow PHB to call them */
869 bool _cxl_pci_associate_default_context(struct pci_dev *dev, struct cxl_afu *afu);
870 void _cxl_pci_disable_device(struct pci_dev *dev);
871 int _cxl_next_msi_hwirq(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq);
872 int _cxl_cx4_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type);
873 void _cxl_cx4_teardown_msi_irqs(struct pci_dev *pdev);
874
875 struct cxl_calls {
876 void (*cxl_slbia)(struct mm_struct *mm);
877 bool (*cxl_pci_associate_default_context)(struct pci_dev *dev, struct cxl_afu *afu);
878 void (*cxl_pci_disable_device)(struct pci_dev *dev);
879 int (*cxl_next_msi_hwirq)(struct pci_dev *pdev, struct cxl_context **ctx, int *afu_irq);
880 int (*cxl_cx4_setup_msi_irqs)(struct pci_dev *pdev, int nvec, int type);
881 void (*cxl_cx4_teardown_msi_irqs)(struct pci_dev *pdev);
882
883 struct module *owner;
884 };
885 int register_cxl_calls(struct cxl_calls *calls);
886 void unregister_cxl_calls(struct cxl_calls *calls);
887 int cxl_update_properties(struct device_node *dn, struct property *new_prop);
888
889 void cxl_remove_adapter_nr(struct cxl *adapter);
890
891 void cxl_release_spa(struct cxl_afu *afu);
892
893 dev_t cxl_get_dev(void);
894 int cxl_file_init(void);
895 void cxl_file_exit(void);
896 int cxl_register_adapter(struct cxl *adapter);
897 int cxl_register_afu(struct cxl_afu *afu);
898 int cxl_chardev_d_afu_add(struct cxl_afu *afu);
899 int cxl_chardev_m_afu_add(struct cxl_afu *afu);
900 int cxl_chardev_s_afu_add(struct cxl_afu *afu);
901 void cxl_chardev_afu_remove(struct cxl_afu *afu);
902
903 void cxl_context_detach_all(struct cxl_afu *afu);
904 void cxl_context_free(struct cxl_context *ctx);
905 void cxl_context_detach(struct cxl_context *ctx);
906
907 int cxl_sysfs_adapter_add(struct cxl *adapter);
908 void cxl_sysfs_adapter_remove(struct cxl *adapter);
909 int cxl_sysfs_afu_add(struct cxl_afu *afu);
910 void cxl_sysfs_afu_remove(struct cxl_afu *afu);
911 int cxl_sysfs_afu_m_add(struct cxl_afu *afu);
912 void cxl_sysfs_afu_m_remove(struct cxl_afu *afu);
913
914 struct cxl *cxl_alloc_adapter(void);
915 struct cxl_afu *cxl_alloc_afu(struct cxl *adapter, int slice);
916 int cxl_afu_select_best_mode(struct cxl_afu *afu);
917
918 int cxl_native_register_psl_irq(struct cxl_afu *afu);
919 void cxl_native_release_psl_irq(struct cxl_afu *afu);
920 int cxl_native_register_psl_err_irq(struct cxl *adapter);
921 void cxl_native_release_psl_err_irq(struct cxl *adapter);
922 int cxl_native_register_serr_irq(struct cxl_afu *afu);
923 void cxl_native_release_serr_irq(struct cxl_afu *afu);
924 int afu_register_irqs(struct cxl_context *ctx, u32 count);
925 void afu_release_irqs(struct cxl_context *ctx, void *cookie);
926 void afu_irq_name_free(struct cxl_context *ctx);
927
928 int cxl_attach_afu_directed_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
929 int cxl_attach_afu_directed_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
930 int cxl_activate_dedicated_process_psl9(struct cxl_afu *afu);
931 int cxl_activate_dedicated_process_psl8(struct cxl_afu *afu);
932 int cxl_attach_dedicated_process_psl9(struct cxl_context *ctx, u64 wed, u64 amr);
933 int cxl_attach_dedicated_process_psl8(struct cxl_context *ctx, u64 wed, u64 amr);
934 void cxl_update_dedicated_ivtes_psl9(struct cxl_context *ctx);
935 void cxl_update_dedicated_ivtes_psl8(struct cxl_context *ctx);
936
937 #ifdef CONFIG_DEBUG_FS
938
939 int cxl_debugfs_init(void);
940 void cxl_debugfs_exit(void);
941 int cxl_debugfs_adapter_add(struct cxl *adapter);
942 void cxl_debugfs_adapter_remove(struct cxl *adapter);
943 int cxl_debugfs_afu_add(struct cxl_afu *afu);
944 void cxl_debugfs_afu_remove(struct cxl_afu *afu);
945 void cxl_stop_trace_psl9(struct cxl *cxl);
946 void cxl_stop_trace_psl8(struct cxl *cxl);
947 void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter, struct dentry *dir);
948 void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter, struct dentry *dir);
949 void cxl_debugfs_add_adapter_regs_xsl(struct cxl *adapter, struct dentry *dir);
950 void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir);
951 void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir);
952
953 #else /* CONFIG_DEBUG_FS */
954
cxl_debugfs_init(void)955 static inline int __init cxl_debugfs_init(void)
956 {
957 return 0;
958 }
959
cxl_debugfs_exit(void)960 static inline void cxl_debugfs_exit(void)
961 {
962 }
963
cxl_debugfs_adapter_add(struct cxl * adapter)964 static inline int cxl_debugfs_adapter_add(struct cxl *adapter)
965 {
966 return 0;
967 }
968
cxl_debugfs_adapter_remove(struct cxl * adapter)969 static inline void cxl_debugfs_adapter_remove(struct cxl *adapter)
970 {
971 }
972
cxl_debugfs_afu_add(struct cxl_afu * afu)973 static inline int cxl_debugfs_afu_add(struct cxl_afu *afu)
974 {
975 return 0;
976 }
977
cxl_debugfs_afu_remove(struct cxl_afu * afu)978 static inline void cxl_debugfs_afu_remove(struct cxl_afu *afu)
979 {
980 }
981
cxl_stop_trace_psl9(struct cxl * cxl)982 static inline void cxl_stop_trace_psl9(struct cxl *cxl)
983 {
984 }
985
cxl_stop_trace_psl8(struct cxl * cxl)986 static inline void cxl_stop_trace_psl8(struct cxl *cxl)
987 {
988 }
989
cxl_debugfs_add_adapter_regs_psl9(struct cxl * adapter,struct dentry * dir)990 static inline void cxl_debugfs_add_adapter_regs_psl9(struct cxl *adapter,
991 struct dentry *dir)
992 {
993 }
994
cxl_debugfs_add_adapter_regs_psl8(struct cxl * adapter,struct dentry * dir)995 static inline void cxl_debugfs_add_adapter_regs_psl8(struct cxl *adapter,
996 struct dentry *dir)
997 {
998 }
999
cxl_debugfs_add_adapter_regs_xsl(struct cxl * adapter,struct dentry * dir)1000 static inline void cxl_debugfs_add_adapter_regs_xsl(struct cxl *adapter,
1001 struct dentry *dir)
1002 {
1003 }
1004
cxl_debugfs_add_afu_regs_psl9(struct cxl_afu * afu,struct dentry * dir)1005 static inline void cxl_debugfs_add_afu_regs_psl9(struct cxl_afu *afu, struct dentry *dir)
1006 {
1007 }
1008
cxl_debugfs_add_afu_regs_psl8(struct cxl_afu * afu,struct dentry * dir)1009 static inline void cxl_debugfs_add_afu_regs_psl8(struct cxl_afu *afu, struct dentry *dir)
1010 {
1011 }
1012
1013 #endif /* CONFIG_DEBUG_FS */
1014
1015 void cxl_handle_fault(struct work_struct *work);
1016 void cxl_prefault(struct cxl_context *ctx, u64 wed);
1017 int cxl_handle_mm_fault(struct mm_struct *mm, u64 dsisr, u64 dar);
1018
1019 struct cxl *get_cxl_adapter(int num);
1020 int cxl_alloc_sst(struct cxl_context *ctx);
1021 void cxl_dump_debug_buffer(void *addr, size_t size);
1022
1023 void init_cxl_native(void);
1024
1025 struct cxl_context *cxl_context_alloc(void);
1026 int cxl_context_init(struct cxl_context *ctx, struct cxl_afu *afu, bool master);
1027 void cxl_context_set_mapping(struct cxl_context *ctx,
1028 struct address_space *mapping);
1029 void cxl_context_free(struct cxl_context *ctx);
1030 int cxl_context_iomap(struct cxl_context *ctx, struct vm_area_struct *vma);
1031 unsigned int cxl_map_irq(struct cxl *adapter, irq_hw_number_t hwirq,
1032 irq_handler_t handler, void *cookie, const char *name);
1033 void cxl_unmap_irq(unsigned int virq, void *cookie);
1034 int __detach_context(struct cxl_context *ctx);
1035
1036 /*
1037 * This must match the layout of the H_COLLECT_CA_INT_INFO retbuf defined
1038 * in PAPR.
1039 * Field pid_tid is now 'reserved' because it's no more used on bare-metal.
1040 * On a guest environment, PSL_PID_An is located on the upper 32 bits and
1041 * PSL_TID_An register in the lower 32 bits.
1042 */
1043 struct cxl_irq_info {
1044 u64 dsisr;
1045 u64 dar;
1046 u64 dsr;
1047 u64 reserved;
1048 u64 afu_err;
1049 u64 errstat;
1050 u64 proc_handle;
1051 u64 padding[2]; /* to match the expected retbuf size for plpar_hcall9 */
1052 };
1053
1054 void cxl_assign_psn_space(struct cxl_context *ctx);
1055 int cxl_invalidate_all_psl9(struct cxl *adapter);
1056 int cxl_invalidate_all_psl8(struct cxl *adapter);
1057 irqreturn_t cxl_irq_psl9(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
1058 irqreturn_t cxl_irq_psl8(int irq, struct cxl_context *ctx, struct cxl_irq_info *irq_info);
1059 irqreturn_t cxl_fail_irq_psl(struct cxl_afu *afu, struct cxl_irq_info *irq_info);
1060 int cxl_register_one_irq(struct cxl *adapter, irq_handler_t handler,
1061 void *cookie, irq_hw_number_t *dest_hwirq,
1062 unsigned int *dest_virq, const char *name);
1063
1064 int cxl_check_error(struct cxl_afu *afu);
1065 int cxl_afu_slbia(struct cxl_afu *afu);
1066 int cxl_data_cache_flush(struct cxl *adapter);
1067 int cxl_afu_disable(struct cxl_afu *afu);
1068 int cxl_psl_purge(struct cxl_afu *afu);
1069 int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
1070 u32 *phb_index, u64 *capp_unit_id);
1071 int cxl_slot_is_switched(struct pci_dev *dev);
1072 int cxl_get_xsl9_dsnctl(u64 capp_unit_id, u64 *reg);
1073 u64 cxl_calculate_sr(bool master, bool kernel, bool real_mode, bool p9);
1074
1075 void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx);
1076 void cxl_native_irq_dump_regs_psl8(struct cxl_context *ctx);
1077 void cxl_native_err_irq_dump_regs(struct cxl *adapter);
1078 int cxl_pci_vphb_add(struct cxl_afu *afu);
1079 void cxl_pci_vphb_remove(struct cxl_afu *afu);
1080 void cxl_release_mapping(struct cxl_context *ctx);
1081
1082 extern struct pci_driver cxl_pci_driver;
1083 extern struct platform_driver cxl_of_driver;
1084 int afu_allocate_irqs(struct cxl_context *ctx, u32 count);
1085
1086 int afu_open(struct inode *inode, struct file *file);
1087 int afu_release(struct inode *inode, struct file *file);
1088 long afu_ioctl(struct file *file, unsigned int cmd, unsigned long arg);
1089 int afu_mmap(struct file *file, struct vm_area_struct *vm);
1090 unsigned int afu_poll(struct file *file, struct poll_table_struct *poll);
1091 ssize_t afu_read(struct file *file, char __user *buf, size_t count, loff_t *off);
1092 extern const struct file_operations afu_fops;
1093
1094 struct cxl *cxl_guest_init_adapter(struct device_node *np, struct platform_device *dev);
1095 void cxl_guest_remove_adapter(struct cxl *adapter);
1096 int cxl_of_read_adapter_handle(struct cxl *adapter, struct device_node *np);
1097 int cxl_of_read_adapter_properties(struct cxl *adapter, struct device_node *np);
1098 ssize_t cxl_guest_read_adapter_vpd(struct cxl *adapter, void *buf, size_t len);
1099 ssize_t cxl_guest_read_afu_vpd(struct cxl_afu *afu, void *buf, size_t len);
1100 int cxl_guest_init_afu(struct cxl *adapter, int slice, struct device_node *afu_np);
1101 void cxl_guest_remove_afu(struct cxl_afu *afu);
1102 int cxl_of_read_afu_handle(struct cxl_afu *afu, struct device_node *afu_np);
1103 int cxl_of_read_afu_properties(struct cxl_afu *afu, struct device_node *afu_np);
1104 int cxl_guest_add_chardev(struct cxl *adapter);
1105 void cxl_guest_remove_chardev(struct cxl *adapter);
1106 void cxl_guest_reload_module(struct cxl *adapter);
1107 int cxl_of_probe(struct platform_device *pdev);
1108
1109 struct cxl_backend_ops {
1110 struct module *module;
1111 int (*adapter_reset)(struct cxl *adapter);
1112 int (*alloc_one_irq)(struct cxl *adapter);
1113 void (*release_one_irq)(struct cxl *adapter, int hwirq);
1114 int (*alloc_irq_ranges)(struct cxl_irq_ranges *irqs,
1115 struct cxl *adapter, unsigned int num);
1116 void (*release_irq_ranges)(struct cxl_irq_ranges *irqs,
1117 struct cxl *adapter);
1118 int (*setup_irq)(struct cxl *adapter, unsigned int hwirq,
1119 unsigned int virq);
1120 irqreturn_t (*handle_psl_slice_error)(struct cxl_context *ctx,
1121 u64 dsisr, u64 errstat);
1122 irqreturn_t (*psl_interrupt)(int irq, void *data);
1123 int (*ack_irq)(struct cxl_context *ctx, u64 tfc, u64 psl_reset_mask);
1124 void (*irq_wait)(struct cxl_context *ctx);
1125 int (*attach_process)(struct cxl_context *ctx, bool kernel,
1126 u64 wed, u64 amr);
1127 int (*detach_process)(struct cxl_context *ctx);
1128 void (*update_ivtes)(struct cxl_context *ctx);
1129 bool (*support_attributes)(const char *attr_name, enum cxl_attrs type);
1130 bool (*link_ok)(struct cxl *cxl, struct cxl_afu *afu);
1131 void (*release_afu)(struct device *dev);
1132 ssize_t (*afu_read_err_buffer)(struct cxl_afu *afu, char *buf,
1133 loff_t off, size_t count);
1134 int (*afu_check_and_enable)(struct cxl_afu *afu);
1135 int (*afu_activate_mode)(struct cxl_afu *afu, int mode);
1136 int (*afu_deactivate_mode)(struct cxl_afu *afu, int mode);
1137 int (*afu_reset)(struct cxl_afu *afu);
1138 int (*afu_cr_read8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 *val);
1139 int (*afu_cr_read16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 *val);
1140 int (*afu_cr_read32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 *val);
1141 int (*afu_cr_read64)(struct cxl_afu *afu, int cr_idx, u64 offset, u64 *val);
1142 int (*afu_cr_write8)(struct cxl_afu *afu, int cr_idx, u64 offset, u8 val);
1143 int (*afu_cr_write16)(struct cxl_afu *afu, int cr_idx, u64 offset, u16 val);
1144 int (*afu_cr_write32)(struct cxl_afu *afu, int cr_idx, u64 offset, u32 val);
1145 ssize_t (*read_adapter_vpd)(struct cxl *adapter, void *buf, size_t count);
1146 };
1147 extern const struct cxl_backend_ops cxl_native_ops;
1148 extern const struct cxl_backend_ops cxl_guest_ops;
1149 extern const struct cxl_backend_ops *cxl_ops;
1150
1151 /* check if the given pci_dev is on the the cxl vphb bus */
1152 bool cxl_pci_is_vphb_device(struct pci_dev *dev);
1153
1154 /* decode AFU error bits in the PSL register PSL_SERR_An */
1155 void cxl_afu_decode_psl_serr(struct cxl_afu *afu, u64 serr);
1156
1157 /*
1158 * Increments the number of attached contexts on an adapter.
1159 * In case an adapter_context_lock is taken the return -EBUSY.
1160 */
1161 int cxl_adapter_context_get(struct cxl *adapter);
1162
1163 /* Decrements the number of attached contexts on an adapter */
1164 void cxl_adapter_context_put(struct cxl *adapter);
1165
1166 /* If no active contexts then prevents contexts from being attached */
1167 int cxl_adapter_context_lock(struct cxl *adapter);
1168
1169 /* Unlock the contexts-lock if taken. Warn and force unlock otherwise */
1170 void cxl_adapter_context_unlock(struct cxl *adapter);
1171
1172 /* Increases the reference count to "struct mm_struct" */
1173 void cxl_context_mm_count_get(struct cxl_context *ctx);
1174
1175 /* Decrements the reference count to "struct mm_struct" */
1176 void cxl_context_mm_count_put(struct cxl_context *ctx);
1177
1178 #endif
1179