1 /* 2 * Copyright (C) 2012-2017 ARM Limited or its affiliates. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program; if not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef __DX_CRYS_KERNEL_H__ 18 #define __DX_CRYS_KERNEL_H__ 19 20 // -------------------------------------- 21 // BLOCK: DSCRPTR 22 // -------------------------------------- 23 #define DX_DSCRPTR_COMPLETION_COUNTER_REG_OFFSET 0xE00UL 24 #define DX_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SHIFT 0x0UL 25 #define DX_DSCRPTR_COMPLETION_COUNTER_COMPLETION_COUNTER_BIT_SIZE 0x6UL 26 #define DX_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SHIFT 0x6UL 27 #define DX_DSCRPTR_COMPLETION_COUNTER_OVERFLOW_COUNTER_BIT_SIZE 0x1UL 28 #define DX_DSCRPTR_SW_RESET_REG_OFFSET 0xE40UL 29 #define DX_DSCRPTR_SW_RESET_VALUE_BIT_SHIFT 0x0UL 30 #define DX_DSCRPTR_SW_RESET_VALUE_BIT_SIZE 0x1UL 31 #define DX_DSCRPTR_QUEUE_SRAM_SIZE_REG_OFFSET 0xE60UL 32 #define DX_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SHIFT 0x0UL 33 #define DX_DSCRPTR_QUEUE_SRAM_SIZE_NUM_OF_DSCRPTR_BIT_SIZE 0xAUL 34 #define DX_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SHIFT 0xAUL 35 #define DX_DSCRPTR_QUEUE_SRAM_SIZE_DSCRPTR_SRAM_SIZE_BIT_SIZE 0xCUL 36 #define DX_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SHIFT 0x16UL 37 #define DX_DSCRPTR_QUEUE_SRAM_SIZE_SRAM_SIZE_BIT_SIZE 0x3UL 38 #define DX_DSCRPTR_SINGLE_ADDR_EN_REG_OFFSET 0xE64UL 39 #define DX_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SHIFT 0x0UL 40 #define DX_DSCRPTR_SINGLE_ADDR_EN_VALUE_BIT_SIZE 0x1UL 41 #define DX_DSCRPTR_MEASURE_CNTR_REG_OFFSET 0xE68UL 42 #define DX_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SHIFT 0x0UL 43 #define DX_DSCRPTR_MEASURE_CNTR_VALUE_BIT_SIZE 0x20UL 44 #define DX_DSCRPTR_QUEUE_WORD0_REG_OFFSET 0xE80UL 45 #define DX_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SHIFT 0x0UL 46 #define DX_DSCRPTR_QUEUE_WORD0_VALUE_BIT_SIZE 0x20UL 47 #define DX_DSCRPTR_QUEUE_WORD1_REG_OFFSET 0xE84UL 48 #define DX_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SHIFT 0x0UL 49 #define DX_DSCRPTR_QUEUE_WORD1_DIN_DMA_MODE_BIT_SIZE 0x2UL 50 #define DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SHIFT 0x2UL 51 #define DX_DSCRPTR_QUEUE_WORD1_DIN_SIZE_BIT_SIZE 0x18UL 52 #define DX_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SHIFT 0x1AUL 53 #define DX_DSCRPTR_QUEUE_WORD1_NS_BIT_BIT_SIZE 0x1UL 54 #define DX_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SHIFT 0x1BUL 55 #define DX_DSCRPTR_QUEUE_WORD1_DIN_CONST_VALUE_BIT_SIZE 0x1UL 56 #define DX_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SHIFT 0x1CUL 57 #define DX_DSCRPTR_QUEUE_WORD1_NOT_LAST_BIT_SIZE 0x1UL 58 #define DX_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SHIFT 0x1DUL 59 #define DX_DSCRPTR_QUEUE_WORD1_LOCK_QUEUE_BIT_SIZE 0x1UL 60 #define DX_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SHIFT 0x1EUL 61 #define DX_DSCRPTR_QUEUE_WORD1_NOT_USED_BIT_SIZE 0x2UL 62 #define DX_DSCRPTR_QUEUE_WORD2_REG_OFFSET 0xE88UL 63 #define DX_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SHIFT 0x0UL 64 #define DX_DSCRPTR_QUEUE_WORD2_VALUE_BIT_SIZE 0x20UL 65 #define DX_DSCRPTR_QUEUE_WORD3_REG_OFFSET 0xE8CUL 66 #define DX_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SHIFT 0x0UL 67 #define DX_DSCRPTR_QUEUE_WORD3_DOUT_DMA_MODE_BIT_SIZE 0x2UL 68 #define DX_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SHIFT 0x2UL 69 #define DX_DSCRPTR_QUEUE_WORD3_DOUT_SIZE_BIT_SIZE 0x18UL 70 #define DX_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SHIFT 0x1AUL 71 #define DX_DSCRPTR_QUEUE_WORD3_NS_BIT_BIT_SIZE 0x1UL 72 #define DX_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SHIFT 0x1BUL 73 #define DX_DSCRPTR_QUEUE_WORD3_DOUT_LAST_IND_BIT_SIZE 0x1UL 74 #define DX_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SHIFT 0x1DUL 75 #define DX_DSCRPTR_QUEUE_WORD3_HASH_XOR_BIT_BIT_SIZE 0x1UL 76 #define DX_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SHIFT 0x1EUL 77 #define DX_DSCRPTR_QUEUE_WORD3_NOT_USED_BIT_SIZE 0x1UL 78 #define DX_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SHIFT 0x1FUL 79 #define DX_DSCRPTR_QUEUE_WORD3_QUEUE_LAST_IND_BIT_SIZE 0x1UL 80 #define DX_DSCRPTR_QUEUE_WORD4_REG_OFFSET 0xE90UL 81 #define DX_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SHIFT 0x0UL 82 #define DX_DSCRPTR_QUEUE_WORD4_DATA_FLOW_MODE_BIT_SIZE 0x6UL 83 #define DX_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SHIFT 0x6UL 84 #define DX_DSCRPTR_QUEUE_WORD4_AES_SEL_N_HASH_BIT_SIZE 0x1UL 85 #define DX_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SHIFT 0x7UL 86 #define DX_DSCRPTR_QUEUE_WORD4_AES_XOR_CRYPTO_KEY_BIT_SIZE 0x1UL 87 #define DX_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SHIFT 0x8UL 88 #define DX_DSCRPTR_QUEUE_WORD4_ACK_NEEDED_BIT_SIZE 0x2UL 89 #define DX_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SHIFT 0xAUL 90 #define DX_DSCRPTR_QUEUE_WORD4_CIPHER_MODE_BIT_SIZE 0x4UL 91 #define DX_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SHIFT 0xEUL 92 #define DX_DSCRPTR_QUEUE_WORD4_CMAC_SIZE0_BIT_SIZE 0x1UL 93 #define DX_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SHIFT 0xFUL 94 #define DX_DSCRPTR_QUEUE_WORD4_CIPHER_DO_BIT_SIZE 0x2UL 95 #define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SHIFT 0x11UL 96 #define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF0_BIT_SIZE 0x2UL 97 #define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SHIFT 0x13UL 98 #define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF1_BIT_SIZE 0x1UL 99 #define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SHIFT 0x14UL 100 #define DX_DSCRPTR_QUEUE_WORD4_CIPHER_CONF2_BIT_SIZE 0x2UL 101 #define DX_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SHIFT 0x16UL 102 #define DX_DSCRPTR_QUEUE_WORD4_KEY_SIZE_BIT_SIZE 0x2UL 103 #define DX_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SHIFT 0x18UL 104 #define DX_DSCRPTR_QUEUE_WORD4_SETUP_OPERATION_BIT_SIZE 0x4UL 105 #define DX_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SHIFT 0x1CUL 106 #define DX_DSCRPTR_QUEUE_WORD4_DIN_SRAM_ENDIANNESS_BIT_SIZE 0x1UL 107 #define DX_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SHIFT 0x1DUL 108 #define DX_DSCRPTR_QUEUE_WORD4_DOUT_SRAM_ENDIANNESS_BIT_SIZE 0x1UL 109 #define DX_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SHIFT 0x1EUL 110 #define DX_DSCRPTR_QUEUE_WORD4_WORD_SWAP_BIT_SIZE 0x1UL 111 #define DX_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SHIFT 0x1FUL 112 #define DX_DSCRPTR_QUEUE_WORD4_BYTES_SWAP_BIT_SIZE 0x1UL 113 #define DX_DSCRPTR_QUEUE_WORD5_REG_OFFSET 0xE94UL 114 #define DX_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SHIFT 0x0UL 115 #define DX_DSCRPTR_QUEUE_WORD5_DIN_ADDR_HIGH_BIT_SIZE 0x10UL 116 #define DX_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SHIFT 0x10UL 117 #define DX_DSCRPTR_QUEUE_WORD5_DOUT_ADDR_HIGH_BIT_SIZE 0x10UL 118 #define DX_DSCRPTR_QUEUE_WATERMARK_REG_OFFSET 0xE98UL 119 #define DX_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SHIFT 0x0UL 120 #define DX_DSCRPTR_QUEUE_WATERMARK_VALUE_BIT_SIZE 0xAUL 121 #define DX_DSCRPTR_QUEUE_CONTENT_REG_OFFSET 0xE9CUL 122 #define DX_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SHIFT 0x0UL 123 #define DX_DSCRPTR_QUEUE_CONTENT_VALUE_BIT_SIZE 0xAUL 124 // -------------------------------------- 125 // BLOCK: AXI_P 126 // -------------------------------------- 127 #define DX_AXIM_MON_INFLIGHT_REG_OFFSET 0xB00UL 128 #define DX_AXIM_MON_INFLIGHT_VALUE_BIT_SHIFT 0x0UL 129 #define DX_AXIM_MON_INFLIGHT_VALUE_BIT_SIZE 0x8UL 130 #define DX_AXIM_MON_INFLIGHTLAST_REG_OFFSET 0xB40UL 131 #define DX_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SHIFT 0x0UL 132 #define DX_AXIM_MON_INFLIGHTLAST_VALUE_BIT_SIZE 0x8UL 133 #define DX_AXIM_MON_COMP_REG_OFFSET 0xB80UL 134 #define DX_AXIM_MON_COMP_VALUE_BIT_SHIFT 0x0UL 135 #define DX_AXIM_MON_COMP_VALUE_BIT_SIZE 0x10UL 136 #define DX_AXIM_MON_ERR_REG_OFFSET 0xBC4UL 137 #define DX_AXIM_MON_ERR_BRESP_BIT_SHIFT 0x0UL 138 #define DX_AXIM_MON_ERR_BRESP_BIT_SIZE 0x2UL 139 #define DX_AXIM_MON_ERR_BID_BIT_SHIFT 0x2UL 140 #define DX_AXIM_MON_ERR_BID_BIT_SIZE 0x4UL 141 #define DX_AXIM_MON_ERR_RRESP_BIT_SHIFT 0x10UL 142 #define DX_AXIM_MON_ERR_RRESP_BIT_SIZE 0x2UL 143 #define DX_AXIM_MON_ERR_RID_BIT_SHIFT 0x12UL 144 #define DX_AXIM_MON_ERR_RID_BIT_SIZE 0x4UL 145 #define DX_AXIM_CFG_REG_OFFSET 0xBE8UL 146 #define DX_AXIM_CFG_BRESPMASK_BIT_SHIFT 0x4UL 147 #define DX_AXIM_CFG_BRESPMASK_BIT_SIZE 0x1UL 148 #define DX_AXIM_CFG_RRESPMASK_BIT_SHIFT 0x5UL 149 #define DX_AXIM_CFG_RRESPMASK_BIT_SIZE 0x1UL 150 #define DX_AXIM_CFG_INFLTMASK_BIT_SHIFT 0x6UL 151 #define DX_AXIM_CFG_INFLTMASK_BIT_SIZE 0x1UL 152 #define DX_AXIM_CFG_COMPMASK_BIT_SHIFT 0x7UL 153 #define DX_AXIM_CFG_COMPMASK_BIT_SIZE 0x1UL 154 #define DX_AXIM_ACE_CONST_REG_OFFSET 0xBECUL 155 #define DX_AXIM_ACE_CONST_ARDOMAIN_BIT_SHIFT 0x0UL 156 #define DX_AXIM_ACE_CONST_ARDOMAIN_BIT_SIZE 0x2UL 157 #define DX_AXIM_ACE_CONST_AWDOMAIN_BIT_SHIFT 0x2UL 158 #define DX_AXIM_ACE_CONST_AWDOMAIN_BIT_SIZE 0x2UL 159 #define DX_AXIM_ACE_CONST_ARBAR_BIT_SHIFT 0x4UL 160 #define DX_AXIM_ACE_CONST_ARBAR_BIT_SIZE 0x2UL 161 #define DX_AXIM_ACE_CONST_AWBAR_BIT_SHIFT 0x6UL 162 #define DX_AXIM_ACE_CONST_AWBAR_BIT_SIZE 0x2UL 163 #define DX_AXIM_ACE_CONST_ARSNOOP_BIT_SHIFT 0x8UL 164 #define DX_AXIM_ACE_CONST_ARSNOOP_BIT_SIZE 0x4UL 165 #define DX_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SHIFT 0xCUL 166 #define DX_AXIM_ACE_CONST_AWSNOOP_NOT_ALIGNED_BIT_SIZE 0x3UL 167 #define DX_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SHIFT 0xFUL 168 #define DX_AXIM_ACE_CONST_AWSNOOP_ALIGNED_BIT_SIZE 0x3UL 169 #define DX_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SHIFT 0x12UL 170 #define DX_AXIM_ACE_CONST_AWADDR_NOT_MASKED_BIT_SIZE 0x7UL 171 #define DX_AXIM_ACE_CONST_AWLEN_VAL_BIT_SHIFT 0x19UL 172 #define DX_AXIM_ACE_CONST_AWLEN_VAL_BIT_SIZE 0x4UL 173 #define DX_AXIM_CACHE_PARAMS_REG_OFFSET 0xBF0UL 174 #define DX_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SHIFT 0x0UL 175 #define DX_AXIM_CACHE_PARAMS_AWCACHE_LAST_BIT_SIZE 0x4UL 176 #define DX_AXIM_CACHE_PARAMS_AWCACHE_BIT_SHIFT 0x4UL 177 #define DX_AXIM_CACHE_PARAMS_AWCACHE_BIT_SIZE 0x4UL 178 #define DX_AXIM_CACHE_PARAMS_ARCACHE_BIT_SHIFT 0x8UL 179 #define DX_AXIM_CACHE_PARAMS_ARCACHE_BIT_SIZE 0x4UL 180 #endif // __DX_CRYS_KERNEL_H__ 181