1 /*
2 * Performance events x86 architecture header
3 *
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
11 *
12 * For licencing details see kernel-base/COPYING
13 */
14
15 #include <linux/perf_event.h>
16
17 #include <asm/intel_ds.h>
18
19 /* To enable MSR tracing please use the generic trace points. */
20
21 /*
22 * | NHM/WSM | SNB |
23 * register -------------------------------
24 * | HT | no HT | HT | no HT |
25 *-----------------------------------------
26 * offcore | core | core | cpu | core |
27 * lbr_sel | core | core | cpu | core |
28 * ld_lat | cpu | core | cpu | core |
29 *-----------------------------------------
30 *
31 * Given that there is a small number of shared regs,
32 * we can pre-allocate their slot in the per-cpu
33 * per-core reg tables.
34 */
35 enum extra_reg_type {
36 EXTRA_REG_NONE = -1, /* not used */
37
38 EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
39 EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
40 EXTRA_REG_LBR = 2, /* lbr_select */
41 EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */
42 EXTRA_REG_FE = 4, /* fe_* */
43
44 EXTRA_REG_MAX /* number of entries needed */
45 };
46
47 struct event_constraint {
48 union {
49 unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
50 u64 idxmsk64;
51 };
52 u64 code;
53 u64 cmask;
54 int weight;
55 int overlap;
56 int flags;
57 };
58 /*
59 * struct hw_perf_event.flags flags
60 */
61 #define PERF_X86_EVENT_PEBS_LDLAT 0x0001 /* ld+ldlat data address sampling */
62 #define PERF_X86_EVENT_PEBS_ST 0x0002 /* st data address sampling */
63 #define PERF_X86_EVENT_PEBS_ST_HSW 0x0004 /* haswell style datala, store */
64 #define PERF_X86_EVENT_COMMITTED 0x0008 /* event passed commit_txn */
65 #define PERF_X86_EVENT_PEBS_LD_HSW 0x0010 /* haswell style datala, load */
66 #define PERF_X86_EVENT_PEBS_NA_HSW 0x0020 /* haswell style datala, unknown */
67 #define PERF_X86_EVENT_EXCL 0x0040 /* HT exclusivity on counter */
68 #define PERF_X86_EVENT_DYNAMIC 0x0080 /* dynamic alloc'd constraint */
69 #define PERF_X86_EVENT_RDPMC_ALLOWED 0x0100 /* grant rdpmc permission */
70 #define PERF_X86_EVENT_EXCL_ACCT 0x0200 /* accounted EXCL event */
71 #define PERF_X86_EVENT_AUTO_RELOAD 0x0400 /* use PEBS auto-reload */
72 #define PERF_X86_EVENT_FREERUNNING 0x0800 /* use freerunning PEBS */
73
74
75 struct amd_nb {
76 int nb_id; /* NorthBridge id */
77 int refcnt; /* reference count */
78 struct perf_event *owners[X86_PMC_IDX_MAX];
79 struct event_constraint event_constraints[X86_PMC_IDX_MAX];
80 };
81
82 #define PEBS_COUNTER_MASK ((1ULL << MAX_PEBS_EVENTS) - 1)
83
84 /*
85 * Flags PEBS can handle without an PMI.
86 *
87 * TID can only be handled by flushing at context switch.
88 * REGS_USER can be handled for events limited to ring 3.
89 *
90 */
91 #define PEBS_FREERUNNING_FLAGS \
92 (PERF_SAMPLE_IP | PERF_SAMPLE_TID | PERF_SAMPLE_ADDR | \
93 PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \
94 PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \
95 PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \
96 PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER)
97
98 #define PEBS_GP_REGS \
99 ((1ULL << PERF_REG_X86_AX) | \
100 (1ULL << PERF_REG_X86_BX) | \
101 (1ULL << PERF_REG_X86_CX) | \
102 (1ULL << PERF_REG_X86_DX) | \
103 (1ULL << PERF_REG_X86_DI) | \
104 (1ULL << PERF_REG_X86_SI) | \
105 (1ULL << PERF_REG_X86_SP) | \
106 (1ULL << PERF_REG_X86_BP) | \
107 (1ULL << PERF_REG_X86_IP) | \
108 (1ULL << PERF_REG_X86_FLAGS) | \
109 (1ULL << PERF_REG_X86_R8) | \
110 (1ULL << PERF_REG_X86_R9) | \
111 (1ULL << PERF_REG_X86_R10) | \
112 (1ULL << PERF_REG_X86_R11) | \
113 (1ULL << PERF_REG_X86_R12) | \
114 (1ULL << PERF_REG_X86_R13) | \
115 (1ULL << PERF_REG_X86_R14) | \
116 (1ULL << PERF_REG_X86_R15))
117
118 /*
119 * Per register state.
120 */
121 struct er_account {
122 raw_spinlock_t lock; /* per-core: protect structure */
123 u64 config; /* extra MSR config */
124 u64 reg; /* extra MSR number */
125 atomic_t ref; /* reference count */
126 };
127
128 /*
129 * Per core/cpu state
130 *
131 * Used to coordinate shared registers between HT threads or
132 * among events on a single PMU.
133 */
134 struct intel_shared_regs {
135 struct er_account regs[EXTRA_REG_MAX];
136 int refcnt; /* per-core: #HT threads */
137 unsigned core_id; /* per-core: core id */
138 };
139
140 enum intel_excl_state_type {
141 INTEL_EXCL_UNUSED = 0, /* counter is unused */
142 INTEL_EXCL_SHARED = 1, /* counter can be used by both threads */
143 INTEL_EXCL_EXCLUSIVE = 2, /* counter can be used by one thread only */
144 };
145
146 struct intel_excl_states {
147 enum intel_excl_state_type state[X86_PMC_IDX_MAX];
148 bool sched_started; /* true if scheduling has started */
149 };
150
151 struct intel_excl_cntrs {
152 raw_spinlock_t lock;
153
154 struct intel_excl_states states[2];
155
156 union {
157 u16 has_exclusive[2];
158 u32 exclusive_present;
159 };
160
161 int refcnt; /* per-core: #HT threads */
162 unsigned core_id; /* per-core: core id */
163 };
164
165 #define MAX_LBR_ENTRIES 32
166
167 enum {
168 X86_PERF_KFREE_SHARED = 0,
169 X86_PERF_KFREE_EXCL = 1,
170 X86_PERF_KFREE_MAX
171 };
172
173 struct cpu_hw_events {
174 /*
175 * Generic x86 PMC bits
176 */
177 struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
178 unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
179 unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
180 int enabled;
181
182 int n_events; /* the # of events in the below arrays */
183 int n_added; /* the # last events in the below arrays;
184 they've never been enabled yet */
185 int n_txn; /* the # last events in the below arrays;
186 added in the current transaction */
187 int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
188 u64 tags[X86_PMC_IDX_MAX];
189
190 struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
191 struct event_constraint *event_constraint[X86_PMC_IDX_MAX];
192
193 int n_excl; /* the number of exclusive events */
194
195 unsigned int txn_flags;
196 int is_fake;
197
198 /*
199 * Intel DebugStore bits
200 */
201 struct debug_store *ds;
202 void *ds_pebs_vaddr;
203 void *ds_bts_vaddr;
204 u64 pebs_enabled;
205 int n_pebs;
206 int n_large_pebs;
207
208 /*
209 * Intel LBR bits
210 */
211 int lbr_users;
212 struct perf_branch_stack lbr_stack;
213 struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
214 struct er_account *lbr_sel;
215 u64 br_sel;
216
217 /*
218 * Intel host/guest exclude bits
219 */
220 u64 intel_ctrl_guest_mask;
221 u64 intel_ctrl_host_mask;
222 struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
223
224 /*
225 * Intel checkpoint mask
226 */
227 u64 intel_cp_status;
228
229 /*
230 * manage shared (per-core, per-cpu) registers
231 * used on Intel NHM/WSM/SNB
232 */
233 struct intel_shared_regs *shared_regs;
234 /*
235 * manage exclusive counter access between hyperthread
236 */
237 struct event_constraint *constraint_list; /* in enable order */
238 struct intel_excl_cntrs *excl_cntrs;
239 int excl_thread_id; /* 0 or 1 */
240
241 /*
242 * SKL TSX_FORCE_ABORT shadow
243 */
244 u64 tfa_shadow;
245
246 /*
247 * AMD specific bits
248 */
249 struct amd_nb *amd_nb;
250 /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
251 u64 perf_ctr_virt_mask;
252
253 void *kfree_on_online[X86_PERF_KFREE_MAX];
254 };
255
256 #define __EVENT_CONSTRAINT(c, n, m, w, o, f) {\
257 { .idxmsk64 = (n) }, \
258 .code = (c), \
259 .cmask = (m), \
260 .weight = (w), \
261 .overlap = (o), \
262 .flags = f, \
263 }
264
265 #define EVENT_CONSTRAINT(c, n, m) \
266 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
267
268 #define INTEL_EXCLEVT_CONSTRAINT(c, n) \
269 __EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT, HWEIGHT(n),\
270 0, PERF_X86_EVENT_EXCL)
271
272 /*
273 * The overlap flag marks event constraints with overlapping counter
274 * masks. This is the case if the counter mask of such an event is not
275 * a subset of any other counter mask of a constraint with an equal or
276 * higher weight, e.g.:
277 *
278 * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
279 * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
280 * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
281 *
282 * The event scheduler may not select the correct counter in the first
283 * cycle because it needs to know which subsequent events will be
284 * scheduled. It may fail to schedule the events then. So we set the
285 * overlap flag for such constraints to give the scheduler a hint which
286 * events to select for counter rescheduling.
287 *
288 * Care must be taken as the rescheduling algorithm is O(n!) which
289 * will increase scheduling cycles for an over-committed system
290 * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
291 * and its counter masks must be kept at a minimum.
292 */
293 #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
294 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
295
296 /*
297 * Constraint on the Event code.
298 */
299 #define INTEL_EVENT_CONSTRAINT(c, n) \
300 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
301
302 /*
303 * Constraint on the Event code + UMask + fixed-mask
304 *
305 * filter mask to validate fixed counter events.
306 * the following filters disqualify for fixed counters:
307 * - inv
308 * - edge
309 * - cnt-mask
310 * - in_tx
311 * - in_tx_checkpointed
312 * The other filters are supported by fixed counters.
313 * The any-thread option is supported starting with v3.
314 */
315 #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
316 #define FIXED_EVENT_CONSTRAINT(c, n) \
317 EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
318
319 /*
320 * Constraint on the Event code + UMask
321 */
322 #define INTEL_UEVENT_CONSTRAINT(c, n) \
323 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
324
325 /* Constraint on specific umask bit only + event */
326 #define INTEL_UBIT_EVENT_CONSTRAINT(c, n) \
327 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT|(c))
328
329 /* Like UEVENT_CONSTRAINT, but match flags too */
330 #define INTEL_FLAGS_UEVENT_CONSTRAINT(c, n) \
331 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
332
333 #define INTEL_EXCLUEVT_CONSTRAINT(c, n) \
334 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
335 HWEIGHT(n), 0, PERF_X86_EVENT_EXCL)
336
337 #define INTEL_PLD_CONSTRAINT(c, n) \
338 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
339 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
340
341 #define INTEL_PST_CONSTRAINT(c, n) \
342 __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
343 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
344
345 /* Event constraint, but match on all event flags too. */
346 #define INTEL_FLAGS_EVENT_CONSTRAINT(c, n) \
347 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS)
348
349 /* Check only flags, but allow all event/umask */
350 #define INTEL_ALL_EVENT_CONSTRAINT(code, n) \
351 EVENT_CONSTRAINT(code, n, X86_ALL_EVENT_FLAGS)
352
353 /* Check flags and event code, and set the HSW store flag */
354 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_ST(code, n) \
355 __EVENT_CONSTRAINT(code, n, \
356 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
357 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
358
359 /* Check flags and event code, and set the HSW load flag */
360 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(code, n) \
361 __EVENT_CONSTRAINT(code, n, \
362 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
363 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
364
365 #define INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(code, n) \
366 __EVENT_CONSTRAINT(code, n, \
367 ARCH_PERFMON_EVENTSEL_EVENT|X86_ALL_EVENT_FLAGS, \
368 HWEIGHT(n), 0, \
369 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
370
371 /* Check flags and event code/umask, and set the HSW store flag */
372 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(code, n) \
373 __EVENT_CONSTRAINT(code, n, \
374 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
375 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
376
377 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(code, n) \
378 __EVENT_CONSTRAINT(code, n, \
379 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
380 HWEIGHT(n), 0, \
381 PERF_X86_EVENT_PEBS_ST_HSW|PERF_X86_EVENT_EXCL)
382
383 /* Check flags and event code/umask, and set the HSW load flag */
384 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(code, n) \
385 __EVENT_CONSTRAINT(code, n, \
386 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
387 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LD_HSW)
388
389 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(code, n) \
390 __EVENT_CONSTRAINT(code, n, \
391 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
392 HWEIGHT(n), 0, \
393 PERF_X86_EVENT_PEBS_LD_HSW|PERF_X86_EVENT_EXCL)
394
395 /* Check flags and event code/umask, and set the HSW N/A flag */
396 #define INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(code, n) \
397 __EVENT_CONSTRAINT(code, n, \
398 INTEL_ARCH_EVENT_MASK|X86_ALL_EVENT_FLAGS, \
399 HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_NA_HSW)
400
401
402 /*
403 * We define the end marker as having a weight of -1
404 * to enable blacklisting of events using a counter bitmask
405 * of zero and thus a weight of zero.
406 * The end marker has a weight that cannot possibly be
407 * obtained from counting the bits in the bitmask.
408 */
409 #define EVENT_CONSTRAINT_END { .weight = -1 }
410
411 /*
412 * Check for end marker with weight == -1
413 */
414 #define for_each_event_constraint(e, c) \
415 for ((e) = (c); (e)->weight != -1; (e)++)
416
417 /*
418 * Extra registers for specific events.
419 *
420 * Some events need large masks and require external MSRs.
421 * Those extra MSRs end up being shared for all events on
422 * a PMU and sometimes between PMU of sibling HT threads.
423 * In either case, the kernel needs to handle conflicting
424 * accesses to those extra, shared, regs. The data structure
425 * to manage those registers is stored in cpu_hw_event.
426 */
427 struct extra_reg {
428 unsigned int event;
429 unsigned int msr;
430 u64 config_mask;
431 u64 valid_mask;
432 int idx; /* per_xxx->regs[] reg index */
433 bool extra_msr_access;
434 };
435
436 #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
437 .event = (e), \
438 .msr = (ms), \
439 .config_mask = (m), \
440 .valid_mask = (vm), \
441 .idx = EXTRA_REG_##i, \
442 .extra_msr_access = true, \
443 }
444
445 #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
446 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
447
448 #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
449 EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
450 ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
451
452 #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
453 INTEL_UEVENT_EXTRA_REG(c, \
454 MSR_PEBS_LD_LAT_THRESHOLD, \
455 0xffff, \
456 LDLAT)
457
458 #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
459
460 union perf_capabilities {
461 struct {
462 u64 lbr_format:6;
463 u64 pebs_trap:1;
464 u64 pebs_arch_reg:1;
465 u64 pebs_format:4;
466 u64 smm_freeze:1;
467 /*
468 * PMU supports separate counter range for writing
469 * values > 32bit.
470 */
471 u64 full_width_write:1;
472 };
473 u64 capabilities;
474 };
475
476 struct x86_pmu_quirk {
477 struct x86_pmu_quirk *next;
478 void (*func)(void);
479 };
480
481 union x86_pmu_config {
482 struct {
483 u64 event:8,
484 umask:8,
485 usr:1,
486 os:1,
487 edge:1,
488 pc:1,
489 interrupt:1,
490 __reserved1:1,
491 en:1,
492 inv:1,
493 cmask:8,
494 event2:4,
495 __reserved2:4,
496 go:1,
497 ho:1;
498 } bits;
499 u64 value;
500 };
501
502 #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
503
504 enum {
505 x86_lbr_exclusive_lbr,
506 x86_lbr_exclusive_bts,
507 x86_lbr_exclusive_pt,
508 x86_lbr_exclusive_max,
509 };
510
511 /*
512 * struct x86_pmu - generic x86 pmu
513 */
514 struct x86_pmu {
515 /*
516 * Generic x86 PMC bits
517 */
518 const char *name;
519 int version;
520 int (*handle_irq)(struct pt_regs *);
521 void (*disable_all)(void);
522 void (*enable_all)(int added);
523 void (*enable)(struct perf_event *);
524 void (*disable)(struct perf_event *);
525 void (*add)(struct perf_event *);
526 void (*del)(struct perf_event *);
527 int (*hw_config)(struct perf_event *event);
528 int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
529 unsigned eventsel;
530 unsigned perfctr;
531 int (*addr_offset)(int index, bool eventsel);
532 int (*rdpmc_index)(int index);
533 u64 (*event_map)(int);
534 int max_events;
535 int num_counters;
536 int num_counters_fixed;
537 int cntval_bits;
538 u64 cntval_mask;
539 union {
540 unsigned long events_maskl;
541 unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
542 };
543 int events_mask_len;
544 int apic;
545 u64 max_period;
546 struct event_constraint *
547 (*get_event_constraints)(struct cpu_hw_events *cpuc,
548 int idx,
549 struct perf_event *event);
550
551 void (*put_event_constraints)(struct cpu_hw_events *cpuc,
552 struct perf_event *event);
553
554 void (*start_scheduling)(struct cpu_hw_events *cpuc);
555
556 void (*commit_scheduling)(struct cpu_hw_events *cpuc, int idx, int cntr);
557
558 void (*stop_scheduling)(struct cpu_hw_events *cpuc);
559
560 struct event_constraint *event_constraints;
561 struct x86_pmu_quirk *quirks;
562 int perfctr_second_write;
563 bool late_ack;
564 u64 (*limit_period)(struct perf_event *event, u64 l);
565
566 /*
567 * sysfs attrs
568 */
569 int attr_rdpmc_broken;
570 int attr_rdpmc;
571 struct attribute **format_attrs;
572 struct attribute **event_attrs;
573 struct attribute **caps_attrs;
574
575 ssize_t (*events_sysfs_show)(char *page, u64 config);
576 struct attribute **cpu_events;
577
578 unsigned long attr_freeze_on_smi;
579 struct attribute **attrs;
580
581 /*
582 * CPU Hotplug hooks
583 */
584 int (*cpu_prepare)(int cpu);
585 void (*cpu_starting)(int cpu);
586 void (*cpu_dying)(int cpu);
587 void (*cpu_dead)(int cpu);
588
589 void (*check_microcode)(void);
590 void (*sched_task)(struct perf_event_context *ctx,
591 bool sched_in);
592
593 /*
594 * Intel Arch Perfmon v2+
595 */
596 u64 intel_ctrl;
597 union perf_capabilities intel_cap;
598
599 /*
600 * Intel DebugStore bits
601 */
602 unsigned int bts :1,
603 bts_active :1,
604 pebs :1,
605 pebs_active :1,
606 pebs_broken :1,
607 pebs_prec_dist :1,
608 pebs_no_tlb :1;
609 int pebs_record_size;
610 int pebs_buffer_size;
611 void (*drain_pebs)(struct pt_regs *regs);
612 struct event_constraint *pebs_constraints;
613 void (*pebs_aliases)(struct perf_event *event);
614 int max_pebs_events;
615 unsigned long free_running_flags;
616
617 /*
618 * Intel LBR
619 */
620 unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
621 int lbr_nr; /* hardware stack size */
622 u64 lbr_sel_mask; /* LBR_SELECT valid bits */
623 const int *lbr_sel_map; /* lbr_select mappings */
624 bool lbr_double_abort; /* duplicated lbr aborts */
625 bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
626
627 /*
628 * Intel PT/LBR/BTS are exclusive
629 */
630 atomic_t lbr_exclusive[x86_lbr_exclusive_max];
631
632 /*
633 * AMD bits
634 */
635 unsigned int amd_nb_constraints : 1;
636
637 /*
638 * Extra registers for events
639 */
640 struct extra_reg *extra_regs;
641 unsigned int flags;
642
643 /*
644 * Intel host/guest support (KVM)
645 */
646 struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
647
648 /*
649 * Check period value for PERF_EVENT_IOC_PERIOD ioctl.
650 */
651 int (*check_period) (struct perf_event *event, u64 period);
652 };
653
654 struct x86_perf_task_context {
655 u64 lbr_from[MAX_LBR_ENTRIES];
656 u64 lbr_to[MAX_LBR_ENTRIES];
657 u64 lbr_info[MAX_LBR_ENTRIES];
658 int tos;
659 int valid_lbrs;
660 int lbr_callstack_users;
661 int lbr_stack_state;
662 };
663
664 #define x86_add_quirk(func_) \
665 do { \
666 static struct x86_pmu_quirk __quirk __initdata = { \
667 .func = func_, \
668 }; \
669 __quirk.next = x86_pmu.quirks; \
670 x86_pmu.quirks = &__quirk; \
671 } while (0)
672
673 /*
674 * x86_pmu flags
675 */
676 #define PMU_FL_NO_HT_SHARING 0x1 /* no hyper-threading resource sharing */
677 #define PMU_FL_HAS_RSP_1 0x2 /* has 2 equivalent offcore_rsp regs */
678 #define PMU_FL_EXCL_CNTRS 0x4 /* has exclusive counter requirements */
679 #define PMU_FL_EXCL_ENABLED 0x8 /* exclusive counter active */
680 #define PMU_FL_TFA 0x20 /* deal with TSX force abort */
681
682 #define EVENT_VAR(_id) event_attr_##_id
683 #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
684
685 #define EVENT_ATTR(_name, _id) \
686 static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
687 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
688 .id = PERF_COUNT_HW_##_id, \
689 .event_str = NULL, \
690 };
691
692 #define EVENT_ATTR_STR(_name, v, str) \
693 static struct perf_pmu_events_attr event_attr_##v = { \
694 .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
695 .id = 0, \
696 .event_str = str, \
697 };
698
699 #define EVENT_ATTR_STR_HT(_name, v, noht, ht) \
700 static struct perf_pmu_events_ht_attr event_attr_##v = { \
701 .attr = __ATTR(_name, 0444, events_ht_sysfs_show, NULL),\
702 .id = 0, \
703 .event_str_noht = noht, \
704 .event_str_ht = ht, \
705 }
706
707 extern struct x86_pmu x86_pmu __read_mostly;
708
x86_pmu_has_lbr_callstack(void)709 static inline bool x86_pmu_has_lbr_callstack(void)
710 {
711 return x86_pmu.lbr_sel_map &&
712 x86_pmu.lbr_sel_map[PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT] > 0;
713 }
714
715 DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
716
717 int x86_perf_event_set_period(struct perf_event *event);
718
719 /*
720 * Generalized hw caching related hw_event table, filled
721 * in on a per model basis. A value of 0 means
722 * 'not supported', -1 means 'hw_event makes no sense on
723 * this CPU', any other value means the raw hw_event
724 * ID.
725 */
726
727 #define C(x) PERF_COUNT_HW_CACHE_##x
728
729 extern u64 __read_mostly hw_cache_event_ids
730 [PERF_COUNT_HW_CACHE_MAX]
731 [PERF_COUNT_HW_CACHE_OP_MAX]
732 [PERF_COUNT_HW_CACHE_RESULT_MAX];
733 extern u64 __read_mostly hw_cache_extra_regs
734 [PERF_COUNT_HW_CACHE_MAX]
735 [PERF_COUNT_HW_CACHE_OP_MAX]
736 [PERF_COUNT_HW_CACHE_RESULT_MAX];
737
738 u64 x86_perf_event_update(struct perf_event *event);
739
x86_pmu_config_addr(int index)740 static inline unsigned int x86_pmu_config_addr(int index)
741 {
742 return x86_pmu.eventsel + (x86_pmu.addr_offset ?
743 x86_pmu.addr_offset(index, true) : index);
744 }
745
x86_pmu_event_addr(int index)746 static inline unsigned int x86_pmu_event_addr(int index)
747 {
748 return x86_pmu.perfctr + (x86_pmu.addr_offset ?
749 x86_pmu.addr_offset(index, false) : index);
750 }
751
x86_pmu_rdpmc_index(int index)752 static inline int x86_pmu_rdpmc_index(int index)
753 {
754 return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
755 }
756
757 int x86_add_exclusive(unsigned int what);
758
759 void x86_del_exclusive(unsigned int what);
760
761 int x86_reserve_hardware(void);
762
763 void x86_release_hardware(void);
764
765 int x86_pmu_max_precise(void);
766
767 void hw_perf_lbr_event_destroy(struct perf_event *event);
768
769 int x86_setup_perfctr(struct perf_event *event);
770
771 int x86_pmu_hw_config(struct perf_event *event);
772
773 void x86_pmu_disable_all(void);
774
__x86_pmu_enable_event(struct hw_perf_event * hwc,u64 enable_mask)775 static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
776 u64 enable_mask)
777 {
778 u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
779
780 if (hwc->extra_reg.reg)
781 wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
782 wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
783 }
784
785 void x86_pmu_enable_all(int added);
786
787 int perf_assign_events(struct event_constraint **constraints, int n,
788 int wmin, int wmax, int gpmax, int *assign);
789 int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
790
791 void x86_pmu_stop(struct perf_event *event, int flags);
792
x86_pmu_disable_event(struct perf_event * event)793 static inline void x86_pmu_disable_event(struct perf_event *event)
794 {
795 struct hw_perf_event *hwc = &event->hw;
796
797 wrmsrl(hwc->config_base, hwc->config);
798 }
799
800 void x86_pmu_enable_event(struct perf_event *event);
801
802 int x86_pmu_handle_irq(struct pt_regs *regs);
803
804 extern struct event_constraint emptyconstraint;
805
806 extern struct event_constraint unconstrained;
807
kernel_ip(unsigned long ip)808 static inline bool kernel_ip(unsigned long ip)
809 {
810 #ifdef CONFIG_X86_32
811 return ip > PAGE_OFFSET;
812 #else
813 return (long)ip < 0;
814 #endif
815 }
816
817 /*
818 * Not all PMUs provide the right context information to place the reported IP
819 * into full context. Specifically segment registers are typically not
820 * supplied.
821 *
822 * Assuming the address is a linear address (it is for IBS), we fake the CS and
823 * vm86 mode using the known zero-based code segment and 'fix up' the registers
824 * to reflect this.
825 *
826 * Intel PEBS/LBR appear to typically provide the effective address, nothing
827 * much we can do about that but pray and treat it like a linear address.
828 */
set_linear_ip(struct pt_regs * regs,unsigned long ip)829 static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
830 {
831 regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
832 if (regs->flags & X86_VM_MASK)
833 regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
834 regs->ip = ip;
835 }
836
837 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
838 ssize_t intel_event_sysfs_show(char *page, u64 config);
839
840 struct attribute **merge_attr(struct attribute **a, struct attribute **b);
841
842 ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
843 char *page);
844 ssize_t events_ht_sysfs_show(struct device *dev, struct device_attribute *attr,
845 char *page);
846
847 #ifdef CONFIG_CPU_SUP_AMD
848
849 int amd_pmu_init(void);
850
851 #else /* CONFIG_CPU_SUP_AMD */
852
amd_pmu_init(void)853 static inline int amd_pmu_init(void)
854 {
855 return 0;
856 }
857
858 #endif /* CONFIG_CPU_SUP_AMD */
859
860 #ifdef CONFIG_CPU_SUP_INTEL
861
intel_pmu_has_bts_period(struct perf_event * event,u64 period)862 static inline bool intel_pmu_has_bts_period(struct perf_event *event, u64 period)
863 {
864 struct hw_perf_event *hwc = &event->hw;
865 unsigned int hw_event, bts_event;
866
867 if (event->attr.freq)
868 return false;
869
870 hw_event = hwc->config & INTEL_ARCH_EVENT_MASK;
871 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS);
872
873 return hw_event == bts_event && period == 1;
874 }
875
intel_pmu_has_bts(struct perf_event * event)876 static inline bool intel_pmu_has_bts(struct perf_event *event)
877 {
878 struct hw_perf_event *hwc = &event->hw;
879
880 return intel_pmu_has_bts_period(event, hwc->sample_period);
881 }
882
883 int intel_pmu_save_and_restart(struct perf_event *event);
884
885 struct event_constraint *
886 x86_get_event_constraints(struct cpu_hw_events *cpuc, int idx,
887 struct perf_event *event);
888
889 extern int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu);
890 extern void intel_cpuc_finish(struct cpu_hw_events *cpuc);
891
892 int intel_pmu_init(void);
893
894 void init_debug_store_on_cpu(int cpu);
895
896 void fini_debug_store_on_cpu(int cpu);
897
898 void release_ds_buffers(void);
899
900 void reserve_ds_buffers(void);
901
902 extern struct event_constraint bts_constraint;
903
904 void intel_pmu_enable_bts(u64 config);
905
906 void intel_pmu_disable_bts(void);
907
908 int intel_pmu_drain_bts_buffer(void);
909
910 extern struct event_constraint intel_core2_pebs_event_constraints[];
911
912 extern struct event_constraint intel_atom_pebs_event_constraints[];
913
914 extern struct event_constraint intel_slm_pebs_event_constraints[];
915
916 extern struct event_constraint intel_glm_pebs_event_constraints[];
917
918 extern struct event_constraint intel_glp_pebs_event_constraints[];
919
920 extern struct event_constraint intel_nehalem_pebs_event_constraints[];
921
922 extern struct event_constraint intel_westmere_pebs_event_constraints[];
923
924 extern struct event_constraint intel_snb_pebs_event_constraints[];
925
926 extern struct event_constraint intel_ivb_pebs_event_constraints[];
927
928 extern struct event_constraint intel_hsw_pebs_event_constraints[];
929
930 extern struct event_constraint intel_bdw_pebs_event_constraints[];
931
932 extern struct event_constraint intel_skl_pebs_event_constraints[];
933
934 struct event_constraint *intel_pebs_constraints(struct perf_event *event);
935
936 void intel_pmu_pebs_add(struct perf_event *event);
937
938 void intel_pmu_pebs_del(struct perf_event *event);
939
940 void intel_pmu_pebs_enable(struct perf_event *event);
941
942 void intel_pmu_pebs_disable(struct perf_event *event);
943
944 void intel_pmu_pebs_enable_all(void);
945
946 void intel_pmu_pebs_disable_all(void);
947
948 void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in);
949
950 void intel_ds_init(void);
951
952 void intel_pmu_lbr_sched_task(struct perf_event_context *ctx, bool sched_in);
953
954 u64 lbr_from_signext_quirk_wr(u64 val);
955
956 void intel_pmu_lbr_reset(void);
957
958 void intel_pmu_lbr_add(struct perf_event *event);
959
960 void intel_pmu_lbr_del(struct perf_event *event);
961
962 void intel_pmu_lbr_enable_all(bool pmi);
963
964 void intel_pmu_lbr_disable_all(void);
965
966 void intel_pmu_lbr_read(void);
967
968 void intel_pmu_lbr_init_core(void);
969
970 void intel_pmu_lbr_init_nhm(void);
971
972 void intel_pmu_lbr_init_atom(void);
973
974 void intel_pmu_lbr_init_slm(void);
975
976 void intel_pmu_lbr_init_snb(void);
977
978 void intel_pmu_lbr_init_hsw(void);
979
980 void intel_pmu_lbr_init_skl(void);
981
982 void intel_pmu_lbr_init_knl(void);
983
984 void intel_pmu_pebs_data_source_nhm(void);
985
986 void intel_pmu_pebs_data_source_skl(bool pmem);
987
988 int intel_pmu_setup_lbr_filter(struct perf_event *event);
989
990 void intel_pt_interrupt(void);
991
992 int intel_bts_interrupt(void);
993
994 void intel_bts_enable_local(void);
995
996 void intel_bts_disable_local(void);
997
998 int p4_pmu_init(void);
999
1000 int p6_pmu_init(void);
1001
1002 int knc_pmu_init(void);
1003
is_ht_workaround_enabled(void)1004 static inline int is_ht_workaround_enabled(void)
1005 {
1006 return !!(x86_pmu.flags & PMU_FL_EXCL_ENABLED);
1007 }
1008
1009 #else /* CONFIG_CPU_SUP_INTEL */
1010
reserve_ds_buffers(void)1011 static inline void reserve_ds_buffers(void)
1012 {
1013 }
1014
release_ds_buffers(void)1015 static inline void release_ds_buffers(void)
1016 {
1017 }
1018
intel_pmu_init(void)1019 static inline int intel_pmu_init(void)
1020 {
1021 return 0;
1022 }
1023
intel_cpuc_prepare(struct cpu_hw_events * cpuc,int cpu)1024 static inline int intel_cpuc_prepare(struct cpu_hw_events *cpuc, int cpu)
1025 {
1026 return 0;
1027 }
1028
intel_cpuc_finish(struct cpu_hw_events * cpuc)1029 static inline void intel_cpuc_finish(struct cpu_hw_events *cpuc)
1030 {
1031 }
1032
is_ht_workaround_enabled(void)1033 static inline int is_ht_workaround_enabled(void)
1034 {
1035 return 0;
1036 }
1037 #endif /* CONFIG_CPU_SUP_INTEL */
1038