1 /*
2 * Macros for accessing system registers with older binutils.
3 *
4 * Copyright (C) 2014 ARM Ltd.
5 * Author: Catalin Marinas <catalin.marinas@arm.com>
6 *
7 * This program is free software: you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef __ASM_SYSREG_H
21 #define __ASM_SYSREG_H
22
23 #include <asm/compiler.h>
24 #include <linux/stringify.h>
25
26 /*
27 * ARMv8 ARM reserves the following encoding for system registers:
28 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview",
29 * C5.2, version:ARM DDI 0487A.f)
30 * [20-19] : Op0
31 * [18-16] : Op1
32 * [15-12] : CRn
33 * [11-8] : CRm
34 * [7-5] : Op2
35 */
36 #define Op0_shift 19
37 #define Op0_mask 0x3
38 #define Op1_shift 16
39 #define Op1_mask 0x7
40 #define CRn_shift 12
41 #define CRn_mask 0xf
42 #define CRm_shift 8
43 #define CRm_mask 0xf
44 #define Op2_shift 5
45 #define Op2_mask 0x7
46
47 #define sys_reg(op0, op1, crn, crm, op2) \
48 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \
49 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \
50 ((op2) << Op2_shift))
51
52 #define sys_insn sys_reg
53
54 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask)
55 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask)
56 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask)
57 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask)
58 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask)
59
60 #ifndef CONFIG_BROKEN_GAS_INST
61
62 #ifdef __ASSEMBLY__
63 #define __emit_inst(x) .inst (x)
64 #else
65 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t"
66 #endif
67
68 #else /* CONFIG_BROKEN_GAS_INST */
69
70 #ifndef CONFIG_CPU_BIG_ENDIAN
71 #define __INSTR_BSWAP(x) (x)
72 #else /* CONFIG_CPU_BIG_ENDIAN */
73 #define __INSTR_BSWAP(x) ((((x) << 24) & 0xff000000) | \
74 (((x) << 8) & 0x00ff0000) | \
75 (((x) >> 8) & 0x0000ff00) | \
76 (((x) >> 24) & 0x000000ff))
77 #endif /* CONFIG_CPU_BIG_ENDIAN */
78
79 #ifdef __ASSEMBLY__
80 #define __emit_inst(x) .long __INSTR_BSWAP(x)
81 #else /* __ASSEMBLY__ */
82 #define __emit_inst(x) ".long " __stringify(__INSTR_BSWAP(x)) "\n\t"
83 #endif /* __ASSEMBLY__ */
84
85 #endif /* CONFIG_BROKEN_GAS_INST */
86
87 #define REG_PSTATE_PAN_IMM sys_reg(0, 0, 4, 0, 4)
88 #define REG_PSTATE_UAO_IMM sys_reg(0, 0, 4, 0, 3)
89 #define REG_PSTATE_SSBS_IMM sys_reg(0, 3, 4, 0, 1)
90
91 #define SET_PSTATE_PAN(x) __emit_inst(0xd5000000 | REG_PSTATE_PAN_IMM | \
92 (!!x)<<8 | 0x1f)
93 #define SET_PSTATE_UAO(x) __emit_inst(0xd5000000 | REG_PSTATE_UAO_IMM | \
94 (!!x)<<8 | 0x1f)
95 #define SET_PSTATE_SSBS(x) __emit_inst(0xd5000000 | REG_PSTATE_SSBS_IMM | \
96 (!!x)<<8 | 0x1f)
97
98 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2)
99 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2)
100 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2)
101
102 #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2)
103 #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0)
104 #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)
105 #define SYS_OSDTRTX_EL1 sys_reg(2, 0, 0, 3, 2)
106 #define SYS_OSECCR_EL1 sys_reg(2, 0, 0, 6, 2)
107 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4)
108 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5)
109 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6)
110 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7)
111 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0)
112 #define SYS_OSLAR_EL1 sys_reg(2, 0, 1, 0, 4)
113 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4)
114 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4)
115 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4)
116 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6)
117 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6)
118 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6)
119 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0)
120 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0)
121 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0)
122 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0)
123 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0)
124
125 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0)
126 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5)
127 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6)
128
129 #define SYS_ID_PFR0_EL1 sys_reg(3, 0, 0, 1, 0)
130 #define SYS_ID_PFR1_EL1 sys_reg(3, 0, 0, 1, 1)
131 #define SYS_ID_DFR0_EL1 sys_reg(3, 0, 0, 1, 2)
132 #define SYS_ID_AFR0_EL1 sys_reg(3, 0, 0, 1, 3)
133 #define SYS_ID_MMFR0_EL1 sys_reg(3, 0, 0, 1, 4)
134 #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5)
135 #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6)
136 #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7)
137
138 #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0)
139 #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)
140 #define SYS_ID_ISAR2_EL1 sys_reg(3, 0, 0, 2, 2)
141 #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3)
142 #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4)
143 #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5)
144 #define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6)
145
146 #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
147 #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1)
148 #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2)
149
150 #define SYS_ID_AA64PFR0_EL1 sys_reg(3, 0, 0, 4, 0)
151 #define SYS_ID_AA64PFR1_EL1 sys_reg(3, 0, 0, 4, 1)
152
153 #define SYS_ID_AA64DFR0_EL1 sys_reg(3, 0, 0, 5, 0)
154 #define SYS_ID_AA64DFR1_EL1 sys_reg(3, 0, 0, 5, 1)
155
156 #define SYS_ID_AA64ISAR0_EL1 sys_reg(3, 0, 0, 6, 0)
157 #define SYS_ID_AA64ISAR1_EL1 sys_reg(3, 0, 0, 6, 1)
158
159 #define SYS_ID_AA64MMFR0_EL1 sys_reg(3, 0, 0, 7, 0)
160 #define SYS_ID_AA64MMFR1_EL1 sys_reg(3, 0, 0, 7, 1)
161 #define SYS_ID_AA64MMFR2_EL1 sys_reg(3, 0, 0, 7, 2)
162
163 #define SYS_SCTLR_EL1 sys_reg(3, 0, 1, 0, 0)
164 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1)
165 #define SYS_CPACR_EL1 sys_reg(3, 0, 1, 0, 2)
166
167 #define SYS_TTBR0_EL1 sys_reg(3, 0, 2, 0, 0)
168 #define SYS_TTBR1_EL1 sys_reg(3, 0, 2, 0, 1)
169 #define SYS_TCR_EL1 sys_reg(3, 0, 2, 0, 2)
170
171 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
172
173 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0)
174 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1)
175 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0)
176 #define SYS_FAR_EL1 sys_reg(3, 0, 6, 0, 0)
177 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0)
178
179 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1)
180 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2)
181
182 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0)
183 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0)
184
185 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0)
186
187 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0)
188 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1)
189 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2)
190 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3)
191 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n)
192 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0)
193 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1)
194 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2)
195 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3)
196 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n)
197 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0)
198 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1)
199 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2)
200 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3)
201 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1)
202 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3)
203 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5)
204 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
205 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
206 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2)
207 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3)
208 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4)
209 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
210 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6)
211 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
212
213 #define SYS_CONTEXTIDR_EL1 sys_reg(3, 0, 13, 0, 1)
214 #define SYS_TPIDR_EL1 sys_reg(3, 0, 13, 0, 4)
215
216 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0)
217
218 #define SYS_CLIDR_EL1 sys_reg(3, 1, 0, 0, 1)
219 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7)
220
221 #define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0)
222
223 #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1)
224 #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7)
225
226 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0)
227 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1)
228 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2)
229 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3)
230 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4)
231 #define SYS_PMSELR_EL0 sys_reg(3, 3, 9, 12, 5)
232 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6)
233 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7)
234 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0)
235 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1)
236 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2)
237 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0)
238 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3)
239
240 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
241 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
242
243 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
244
245 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
246 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1)
247 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2)
248
249 #define __PMEV_op2(n) ((n) & 0x7)
250 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3))
251 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n))
252 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3))
253 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n))
254
255 #define SYS_PMCCFILTR_EL0 sys_reg (3, 3, 14, 15, 7)
256
257 #define SYS_DACR32_EL2 sys_reg(3, 4, 3, 0, 0)
258 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1)
259 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0)
260
261 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x)
262 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0)
263 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1)
264 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2)
265 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3)
266
267 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x)
268 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0)
269 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1)
270 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2)
271 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3)
272
273 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4)
274 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5)
275 #define SYS_ICH_HCR_EL2 sys_reg(3, 4, 12, 11, 0)
276 #define SYS_ICH_VTR_EL2 sys_reg(3, 4, 12, 11, 1)
277 #define SYS_ICH_MISR_EL2 sys_reg(3, 4, 12, 11, 2)
278 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3)
279 #define SYS_ICH_ELSR_EL2 sys_reg(3, 4, 12, 11, 5)
280 #define SYS_ICH_VMCR_EL2 sys_reg(3, 4, 12, 11, 7)
281
282 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x)
283 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0)
284 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1)
285 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2)
286 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3)
287 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4)
288 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5)
289 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6)
290 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7)
291
292 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x)
293 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0)
294 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1)
295 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2)
296 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3)
297 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4)
298 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5)
299 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6)
300 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7)
301
302 /* Common SCTLR_ELx flags. */
303 #define SCTLR_ELx_DSSBS (1UL << 44)
304 #define SCTLR_ELx_EE (1 << 25)
305 #define SCTLR_ELx_WXN (1 << 19)
306 #define SCTLR_ELx_I (1 << 12)
307 #define SCTLR_ELx_SA (1 << 3)
308 #define SCTLR_ELx_C (1 << 2)
309 #define SCTLR_ELx_A (1 << 1)
310 #define SCTLR_ELx_M 1
311
312 #define SCTLR_ELx_FLAGS (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
313 SCTLR_ELx_SA | SCTLR_ELx_I)
314
315 /* SCTLR_EL2 specific flags. */
316 #define SCTLR_EL2_RES1 ((1 << 4) | (1 << 5) | (1 << 11) | (1 << 16) | \
317 (1 << 18) | (1 << 22) | (1 << 23) | (1 << 28) | \
318 (1 << 29))
319 #define SCTLR_EL2_RES0 ((1 << 6) | (1 << 7) | (1 << 8) | (1 << 9) | \
320 (1 << 10) | (1 << 13) | (1 << 14) | (1 << 15) | \
321 (1 << 17) | (1 << 20) | (1 << 21) | (1 << 24) | \
322 (1 << 26) | (1 << 27) | (1 << 30) | (1 << 31) | \
323 (0xffffefffUL << 32))
324
325 #ifdef CONFIG_CPU_BIG_ENDIAN
326 #define ENDIAN_SET_EL2 SCTLR_ELx_EE
327 #define ENDIAN_CLEAR_EL2 0
328 #else
329 #define ENDIAN_SET_EL2 0
330 #define ENDIAN_CLEAR_EL2 SCTLR_ELx_EE
331 #endif
332
333 /* SCTLR_EL2 value used for the hyp-stub */
334 #define SCTLR_EL2_SET (ENDIAN_SET_EL2 | SCTLR_EL2_RES1)
335 #define SCTLR_EL2_CLEAR (SCTLR_ELx_M | SCTLR_ELx_A | SCTLR_ELx_C | \
336 SCTLR_ELx_SA | SCTLR_ELx_I | SCTLR_ELx_WXN | \
337 SCTLR_ELx_DSSBS | ENDIAN_CLEAR_EL2 | SCTLR_EL2_RES0)
338
339 #if (SCTLR_EL2_SET ^ SCTLR_EL2_CLEAR) != 0xffffffffffffffff
340 #error "Inconsistent SCTLR_EL2 set/clear bits"
341 #endif
342
343 /* SCTLR_EL1 specific flags. */
344 #define SCTLR_EL1_UCI (1 << 26)
345 #define SCTLR_EL1_E0E (1 << 24)
346 #define SCTLR_EL1_SPAN (1 << 23)
347 #define SCTLR_EL1_NTWE (1 << 18)
348 #define SCTLR_EL1_NTWI (1 << 16)
349 #define SCTLR_EL1_UCT (1 << 15)
350 #define SCTLR_EL1_DZE (1 << 14)
351 #define SCTLR_EL1_UMA (1 << 9)
352 #define SCTLR_EL1_SED (1 << 8)
353 #define SCTLR_EL1_ITD (1 << 7)
354 #define SCTLR_EL1_CP15BEN (1 << 5)
355 #define SCTLR_EL1_SA0 (1 << 4)
356
357 #define SCTLR_EL1_RES1 ((1 << 11) | (1 << 20) | (1 << 22) | (1 << 28) | \
358 (1 << 29))
359 #define SCTLR_EL1_RES0 ((1 << 6) | (1 << 10) | (1 << 13) | (1 << 17) | \
360 (1 << 21) | (1 << 27) | (1 << 30) | (1 << 31) | \
361 (0xffffefffUL << 32))
362
363 #ifdef CONFIG_CPU_BIG_ENDIAN
364 #define ENDIAN_SET_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
365 #define ENDIAN_CLEAR_EL1 0
366 #else
367 #define ENDIAN_SET_EL1 0
368 #define ENDIAN_CLEAR_EL1 (SCTLR_EL1_E0E | SCTLR_ELx_EE)
369 #endif
370
371 #define SCTLR_EL1_SET (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA |\
372 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I |\
373 SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_NTWI |\
374 SCTLR_EL1_NTWE | SCTLR_EL1_SPAN | ENDIAN_SET_EL1 |\
375 SCTLR_EL1_UCI | SCTLR_EL1_RES1)
376 #define SCTLR_EL1_CLEAR (SCTLR_ELx_A | SCTLR_EL1_CP15BEN | SCTLR_EL1_ITD |\
377 SCTLR_EL1_UMA | SCTLR_ELx_WXN | ENDIAN_CLEAR_EL1 |\
378 SCTLR_ELx_DSSBS | SCTLR_EL1_RES0)
379
380 #if (SCTLR_EL1_SET ^ SCTLR_EL1_CLEAR) != 0xffffffffffffffff
381 #error "Inconsistent SCTLR_EL1 set/clear bits"
382 #endif
383
384 /* id_aa64isar0 */
385 #define ID_AA64ISAR0_TS_SHIFT 52
386 #define ID_AA64ISAR0_FHM_SHIFT 48
387 #define ID_AA64ISAR0_DP_SHIFT 44
388 #define ID_AA64ISAR0_SM4_SHIFT 40
389 #define ID_AA64ISAR0_SM3_SHIFT 36
390 #define ID_AA64ISAR0_SHA3_SHIFT 32
391 #define ID_AA64ISAR0_RDM_SHIFT 28
392 #define ID_AA64ISAR0_ATOMICS_SHIFT 20
393 #define ID_AA64ISAR0_CRC32_SHIFT 16
394 #define ID_AA64ISAR0_SHA2_SHIFT 12
395 #define ID_AA64ISAR0_SHA1_SHIFT 8
396 #define ID_AA64ISAR0_AES_SHIFT 4
397
398 /* id_aa64isar1 */
399 #define ID_AA64ISAR1_LRCPC_SHIFT 20
400 #define ID_AA64ISAR1_FCMA_SHIFT 16
401 #define ID_AA64ISAR1_JSCVT_SHIFT 12
402 #define ID_AA64ISAR1_DPB_SHIFT 0
403
404 /* id_aa64pfr0 */
405 #define ID_AA64PFR0_CSV3_SHIFT 60
406 #define ID_AA64PFR0_CSV2_SHIFT 56
407 #define ID_AA64PFR0_DIT_SHIFT 48
408 #define ID_AA64PFR0_GIC_SHIFT 24
409 #define ID_AA64PFR0_ASIMD_SHIFT 20
410 #define ID_AA64PFR0_FP_SHIFT 16
411 #define ID_AA64PFR0_EL3_SHIFT 12
412 #define ID_AA64PFR0_EL2_SHIFT 8
413 #define ID_AA64PFR0_EL1_SHIFT 4
414 #define ID_AA64PFR0_EL0_SHIFT 0
415
416 #define ID_AA64PFR0_FP_NI 0xf
417 #define ID_AA64PFR0_FP_SUPPORTED 0x0
418 #define ID_AA64PFR0_ASIMD_NI 0xf
419 #define ID_AA64PFR0_ASIMD_SUPPORTED 0x0
420 #define ID_AA64PFR0_EL1_64BIT_ONLY 0x1
421 #define ID_AA64PFR0_EL0_64BIT_ONLY 0x1
422 #define ID_AA64PFR0_EL0_32BIT_64BIT 0x2
423
424 /* id_aa64pfr1 */
425 #define ID_AA64PFR1_SSBS_SHIFT 4
426
427 #define ID_AA64PFR1_SSBS_PSTATE_NI 0
428 #define ID_AA64PFR1_SSBS_PSTATE_ONLY 1
429 #define ID_AA64PFR1_SSBS_PSTATE_INSNS 2
430
431 /* id_aa64mmfr0 */
432 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
433 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
434 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
435 #define ID_AA64MMFR0_BIGENDEL0_SHIFT 16
436 #define ID_AA64MMFR0_SNSMEM_SHIFT 12
437 #define ID_AA64MMFR0_BIGENDEL_SHIFT 8
438 #define ID_AA64MMFR0_ASID_SHIFT 4
439 #define ID_AA64MMFR0_PARANGE_SHIFT 0
440
441 #define ID_AA64MMFR0_TGRAN4_NI 0xf
442 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
443 #define ID_AA64MMFR0_TGRAN64_NI 0xf
444 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
445 #define ID_AA64MMFR0_TGRAN16_NI 0x0
446 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
447
448 /* id_aa64mmfr1 */
449 #define ID_AA64MMFR1_PAN_SHIFT 20
450 #define ID_AA64MMFR1_LOR_SHIFT 16
451 #define ID_AA64MMFR1_HPD_SHIFT 12
452 #define ID_AA64MMFR1_VHE_SHIFT 8
453 #define ID_AA64MMFR1_VMIDBITS_SHIFT 4
454 #define ID_AA64MMFR1_HADBS_SHIFT 0
455
456 #define ID_AA64MMFR1_VMIDBITS_8 0
457 #define ID_AA64MMFR1_VMIDBITS_16 2
458
459 /* id_aa64mmfr2 */
460 #define ID_AA64MMFR2_AT_SHIFT 32
461 #define ID_AA64MMFR2_LVA_SHIFT 16
462 #define ID_AA64MMFR2_IESB_SHIFT 12
463 #define ID_AA64MMFR2_LSM_SHIFT 8
464 #define ID_AA64MMFR2_UAO_SHIFT 4
465 #define ID_AA64MMFR2_CNP_SHIFT 0
466
467 /* id_aa64dfr0 */
468 #define ID_AA64DFR0_PMSVER_SHIFT 32
469 #define ID_AA64DFR0_CTX_CMPS_SHIFT 28
470 #define ID_AA64DFR0_WRPS_SHIFT 20
471 #define ID_AA64DFR0_BRPS_SHIFT 12
472 #define ID_AA64DFR0_PMUVER_SHIFT 8
473 #define ID_AA64DFR0_TRACEVER_SHIFT 4
474 #define ID_AA64DFR0_DEBUGVER_SHIFT 0
475
476 #define ID_ISAR5_RDM_SHIFT 24
477 #define ID_ISAR5_CRC32_SHIFT 16
478 #define ID_ISAR5_SHA2_SHIFT 12
479 #define ID_ISAR5_SHA1_SHIFT 8
480 #define ID_ISAR5_AES_SHIFT 4
481 #define ID_ISAR5_SEVL_SHIFT 0
482
483 #define MVFR0_FPROUND_SHIFT 28
484 #define MVFR0_FPSHVEC_SHIFT 24
485 #define MVFR0_FPSQRT_SHIFT 20
486 #define MVFR0_FPDIVIDE_SHIFT 16
487 #define MVFR0_FPTRAP_SHIFT 12
488 #define MVFR0_FPDP_SHIFT 8
489 #define MVFR0_FPSP_SHIFT 4
490 #define MVFR0_SIMD_SHIFT 0
491
492 #define MVFR1_SIMDFMAC_SHIFT 28
493 #define MVFR1_FPHP_SHIFT 24
494 #define MVFR1_SIMDHP_SHIFT 20
495 #define MVFR1_SIMDSP_SHIFT 16
496 #define MVFR1_SIMDINT_SHIFT 12
497 #define MVFR1_SIMDLS_SHIFT 8
498 #define MVFR1_FPDNAN_SHIFT 4
499 #define MVFR1_FPFTZ_SHIFT 0
500
501
502 #define ID_AA64MMFR0_TGRAN4_SHIFT 28
503 #define ID_AA64MMFR0_TGRAN64_SHIFT 24
504 #define ID_AA64MMFR0_TGRAN16_SHIFT 20
505
506 #define ID_AA64MMFR0_TGRAN4_NI 0xf
507 #define ID_AA64MMFR0_TGRAN4_SUPPORTED 0x0
508 #define ID_AA64MMFR0_TGRAN64_NI 0xf
509 #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
510 #define ID_AA64MMFR0_TGRAN16_NI 0x0
511 #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
512
513 #if defined(CONFIG_ARM64_4K_PAGES)
514 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN4_SHIFT
515 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN4_SUPPORTED
516 #elif defined(CONFIG_ARM64_16K_PAGES)
517 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN16_SHIFT
518 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN16_SUPPORTED
519 #elif defined(CONFIG_ARM64_64K_PAGES)
520 #define ID_AA64MMFR0_TGRAN_SHIFT ID_AA64MMFR0_TGRAN64_SHIFT
521 #define ID_AA64MMFR0_TGRAN_SUPPORTED ID_AA64MMFR0_TGRAN64_SUPPORTED
522 #endif
523
524
525 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
526 #define SYS_MPIDR_SAFE_VAL (1UL << 31)
527
528 #ifdef __ASSEMBLY__
529
530 .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30
531 .equ .L__reg_num_x\num, \num
532 .endr
533 .equ .L__reg_num_xzr, 31
534
535 .macro mrs_s, rt, sreg
536 __emit_inst(0xd5200000|(\sreg)|(.L__reg_num_\rt))
537 .endm
538
539 .macro msr_s, sreg, rt
540 __emit_inst(0xd5000000|(\sreg)|(.L__reg_num_\rt))
541 .endm
542
543 #else
544
545 #include <linux/build_bug.h>
546 #include <linux/types.h>
547
548 #define __DEFINE_MRS_MSR_S_REGNUM \
549 " .irp num,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30\n" \
550 " .equ .L__reg_num_x\\num, \\num\n" \
551 " .endr\n" \
552 " .equ .L__reg_num_xzr, 31\n"
553
554 #define DEFINE_MRS_S \
555 __DEFINE_MRS_MSR_S_REGNUM \
556 " .macro mrs_s, rt, sreg\n" \
557 " .inst 0xd5200000|(\\sreg)|(.L__reg_num_\\rt)\n" \
558 " .endm\n"
559
560 #define DEFINE_MSR_S \
561 __DEFINE_MRS_MSR_S_REGNUM \
562 " .macro msr_s, sreg, rt\n" \
563 " .inst 0xd5000000|(\\sreg)|(.L__reg_num_\\rt)\n" \
564 " .endm\n"
565
566 #define UNDEFINE_MRS_S \
567 " .purgem mrs_s\n"
568
569 #define UNDEFINE_MSR_S \
570 " .purgem msr_s\n"
571
572 #define __mrs_s(r, v) \
573 DEFINE_MRS_S \
574 " mrs_s %0, " __stringify(r) "\n" \
575 UNDEFINE_MRS_S : "=r" (v)
576
577 #define __msr_s(r, v) \
578 DEFINE_MSR_S \
579 " msr_s " __stringify(r) ", %x0\n" \
580 UNDEFINE_MSR_S : : "rZ" (v)
581
582 /*
583 * Unlike read_cpuid, calls to read_sysreg are never expected to be
584 * optimized away or replaced with synthetic values.
585 */
586 #define read_sysreg(r) ({ \
587 u64 __val; \
588 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \
589 __val; \
590 })
591
592 /*
593 * The "Z" constraint normally means a zero immediate, but when combined with
594 * the "%x0" template means XZR.
595 */
596 #define write_sysreg(v, r) do { \
597 u64 __val = (u64)(v); \
598 asm volatile("msr " __stringify(r) ", %x0" \
599 : : "rZ" (__val)); \
600 } while (0)
601
602 /*
603 * For registers without architectural names, or simply unsupported by
604 * GAS.
605 */
606 #define read_sysreg_s(r) ({ \
607 u64 __val; \
608 asm volatile(__mrs_s(r, __val)); \
609 __val; \
610 })
611
612 #define write_sysreg_s(v, r) do { \
613 u64 __val = (u64)(v); \
614 asm volatile(__msr_s(r, __val)); \
615 } while (0)
616
617 /*
618 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the
619 * set mask are set. Other bits are left as-is.
620 */
621 #define sysreg_clear_set(sysreg, clear, set) do { \
622 u64 __scs_val = read_sysreg(sysreg); \
623 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \
624 if (__scs_new != __scs_val) \
625 write_sysreg(__scs_new, sysreg); \
626 } while (0)
627
config_sctlr_el1(u32 clear,u32 set)628 static inline void config_sctlr_el1(u32 clear, u32 set)
629 {
630 u32 val;
631
632 val = read_sysreg(sctlr_el1);
633 val &= ~clear;
634 val |= set;
635 write_sysreg(val, sctlr_el1);
636 }
637
638 #endif
639
640 #endif /* __ASM_SYSREG_H */
641