1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /* 3 * Copyright 2010 Tilera Corporation. All Rights Reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation, version 2. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 12 * NON INFRINGEMENT. See the GNU General Public License for 13 * more details. 14 */ 15 16 #ifndef __ARCH_INTERRUPTS_H__ 17 #define __ARCH_INTERRUPTS_H__ 18 19 #ifndef __KERNEL__ 20 /** Mask for an interrupt. */ 21 /* Note: must handle breaking interrupts into high and low words manually. */ 22 #define INT_MASK_LO(intno) (1 << (intno)) 23 #define INT_MASK_HI(intno) (1 << ((intno) - 32)) 24 25 #ifndef __ASSEMBLER__ 26 #define INT_MASK(intno) (1ULL << (intno)) 27 #endif 28 #endif 29 30 31 /** Where a given interrupt executes */ 32 #define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8)) 33 34 /** Where to store a vector for a given interrupt. */ 35 #define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0) 36 37 /** The base address of user-level interrupts. */ 38 #define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0) 39 40 41 /** Additional synthetic interrupt. */ 42 #define INT_BREAKPOINT (63) 43 44 #define INT_ITLB_MISS 0 45 #define INT_MEM_ERROR 1 46 #define INT_ILL 2 47 #define INT_GPV 3 48 #define INT_SN_ACCESS 4 49 #define INT_IDN_ACCESS 5 50 #define INT_UDN_ACCESS 6 51 #define INT_IDN_REFILL 7 52 #define INT_UDN_REFILL 8 53 #define INT_IDN_COMPLETE 9 54 #define INT_UDN_COMPLETE 10 55 #define INT_SWINT_3 11 56 #define INT_SWINT_2 12 57 #define INT_SWINT_1 13 58 #define INT_SWINT_0 14 59 #define INT_UNALIGN_DATA 15 60 #define INT_DTLB_MISS 16 61 #define INT_DTLB_ACCESS 17 62 #define INT_DMATLB_MISS 18 63 #define INT_DMATLB_ACCESS 19 64 #define INT_SNITLB_MISS 20 65 #define INT_SN_NOTIFY 21 66 #define INT_SN_FIREWALL 22 67 #define INT_IDN_FIREWALL 23 68 #define INT_UDN_FIREWALL 24 69 #define INT_TILE_TIMER 25 70 #define INT_IDN_TIMER 26 71 #define INT_UDN_TIMER 27 72 #define INT_DMA_NOTIFY 28 73 #define INT_IDN_CA 29 74 #define INT_UDN_CA 30 75 #define INT_IDN_AVAIL 31 76 #define INT_UDN_AVAIL 32 77 #define INT_PERF_COUNT 33 78 #define INT_INTCTRL_3 34 79 #define INT_INTCTRL_2 35 80 #define INT_INTCTRL_1 36 81 #define INT_INTCTRL_0 37 82 #define INT_BOOT_ACCESS 38 83 #define INT_WORLD_ACCESS 39 84 #define INT_I_ASID 40 85 #define INT_D_ASID 41 86 #define INT_DMA_ASID 42 87 #define INT_SNI_ASID 43 88 #define INT_DMA_CPL 44 89 #define INT_SN_CPL 45 90 #define INT_DOUBLE_FAULT 46 91 #define INT_SN_STATIC_ACCESS 47 92 #define INT_AUX_PERF_COUNT 48 93 94 #define NUM_INTERRUPTS 49 95 96 #ifndef __ASSEMBLER__ 97 #define QUEUED_INTERRUPTS ( \ 98 (1ULL << INT_MEM_ERROR) | \ 99 (1ULL << INT_DMATLB_MISS) | \ 100 (1ULL << INT_DMATLB_ACCESS) | \ 101 (1ULL << INT_SNITLB_MISS) | \ 102 (1ULL << INT_SN_NOTIFY) | \ 103 (1ULL << INT_SN_FIREWALL) | \ 104 (1ULL << INT_IDN_FIREWALL) | \ 105 (1ULL << INT_UDN_FIREWALL) | \ 106 (1ULL << INT_TILE_TIMER) | \ 107 (1ULL << INT_IDN_TIMER) | \ 108 (1ULL << INT_UDN_TIMER) | \ 109 (1ULL << INT_DMA_NOTIFY) | \ 110 (1ULL << INT_IDN_CA) | \ 111 (1ULL << INT_UDN_CA) | \ 112 (1ULL << INT_IDN_AVAIL) | \ 113 (1ULL << INT_UDN_AVAIL) | \ 114 (1ULL << INT_PERF_COUNT) | \ 115 (1ULL << INT_INTCTRL_3) | \ 116 (1ULL << INT_INTCTRL_2) | \ 117 (1ULL << INT_INTCTRL_1) | \ 118 (1ULL << INT_INTCTRL_0) | \ 119 (1ULL << INT_BOOT_ACCESS) | \ 120 (1ULL << INT_WORLD_ACCESS) | \ 121 (1ULL << INT_I_ASID) | \ 122 (1ULL << INT_D_ASID) | \ 123 (1ULL << INT_DMA_ASID) | \ 124 (1ULL << INT_SNI_ASID) | \ 125 (1ULL << INT_DMA_CPL) | \ 126 (1ULL << INT_SN_CPL) | \ 127 (1ULL << INT_DOUBLE_FAULT) | \ 128 (1ULL << INT_AUX_PERF_COUNT) | \ 129 0) 130 #define NONQUEUED_INTERRUPTS ( \ 131 (1ULL << INT_ITLB_MISS) | \ 132 (1ULL << INT_ILL) | \ 133 (1ULL << INT_GPV) | \ 134 (1ULL << INT_SN_ACCESS) | \ 135 (1ULL << INT_IDN_ACCESS) | \ 136 (1ULL << INT_UDN_ACCESS) | \ 137 (1ULL << INT_IDN_REFILL) | \ 138 (1ULL << INT_UDN_REFILL) | \ 139 (1ULL << INT_IDN_COMPLETE) | \ 140 (1ULL << INT_UDN_COMPLETE) | \ 141 (1ULL << INT_SWINT_3) | \ 142 (1ULL << INT_SWINT_2) | \ 143 (1ULL << INT_SWINT_1) | \ 144 (1ULL << INT_SWINT_0) | \ 145 (1ULL << INT_UNALIGN_DATA) | \ 146 (1ULL << INT_DTLB_MISS) | \ 147 (1ULL << INT_DTLB_ACCESS) | \ 148 (1ULL << INT_SN_STATIC_ACCESS) | \ 149 0) 150 #define CRITICAL_MASKED_INTERRUPTS ( \ 151 (1ULL << INT_MEM_ERROR) | \ 152 (1ULL << INT_DMATLB_MISS) | \ 153 (1ULL << INT_DMATLB_ACCESS) | \ 154 (1ULL << INT_SNITLB_MISS) | \ 155 (1ULL << INT_SN_NOTIFY) | \ 156 (1ULL << INT_SN_FIREWALL) | \ 157 (1ULL << INT_IDN_FIREWALL) | \ 158 (1ULL << INT_UDN_FIREWALL) | \ 159 (1ULL << INT_TILE_TIMER) | \ 160 (1ULL << INT_IDN_TIMER) | \ 161 (1ULL << INT_UDN_TIMER) | \ 162 (1ULL << INT_DMA_NOTIFY) | \ 163 (1ULL << INT_IDN_CA) | \ 164 (1ULL << INT_UDN_CA) | \ 165 (1ULL << INT_IDN_AVAIL) | \ 166 (1ULL << INT_UDN_AVAIL) | \ 167 (1ULL << INT_PERF_COUNT) | \ 168 (1ULL << INT_INTCTRL_3) | \ 169 (1ULL << INT_INTCTRL_2) | \ 170 (1ULL << INT_INTCTRL_1) | \ 171 (1ULL << INT_INTCTRL_0) | \ 172 (1ULL << INT_AUX_PERF_COUNT) | \ 173 0) 174 #define CRITICAL_UNMASKED_INTERRUPTS ( \ 175 (1ULL << INT_ITLB_MISS) | \ 176 (1ULL << INT_ILL) | \ 177 (1ULL << INT_GPV) | \ 178 (1ULL << INT_SN_ACCESS) | \ 179 (1ULL << INT_IDN_ACCESS) | \ 180 (1ULL << INT_UDN_ACCESS) | \ 181 (1ULL << INT_IDN_REFILL) | \ 182 (1ULL << INT_UDN_REFILL) | \ 183 (1ULL << INT_IDN_COMPLETE) | \ 184 (1ULL << INT_UDN_COMPLETE) | \ 185 (1ULL << INT_SWINT_3) | \ 186 (1ULL << INT_SWINT_2) | \ 187 (1ULL << INT_SWINT_1) | \ 188 (1ULL << INT_SWINT_0) | \ 189 (1ULL << INT_UNALIGN_DATA) | \ 190 (1ULL << INT_DTLB_MISS) | \ 191 (1ULL << INT_DTLB_ACCESS) | \ 192 (1ULL << INT_BOOT_ACCESS) | \ 193 (1ULL << INT_WORLD_ACCESS) | \ 194 (1ULL << INT_I_ASID) | \ 195 (1ULL << INT_D_ASID) | \ 196 (1ULL << INT_DMA_ASID) | \ 197 (1ULL << INT_SNI_ASID) | \ 198 (1ULL << INT_DMA_CPL) | \ 199 (1ULL << INT_SN_CPL) | \ 200 (1ULL << INT_DOUBLE_FAULT) | \ 201 (1ULL << INT_SN_STATIC_ACCESS) | \ 202 0) 203 #define MASKABLE_INTERRUPTS ( \ 204 (1ULL << INT_MEM_ERROR) | \ 205 (1ULL << INT_IDN_REFILL) | \ 206 (1ULL << INT_UDN_REFILL) | \ 207 (1ULL << INT_IDN_COMPLETE) | \ 208 (1ULL << INT_UDN_COMPLETE) | \ 209 (1ULL << INT_DMATLB_MISS) | \ 210 (1ULL << INT_DMATLB_ACCESS) | \ 211 (1ULL << INT_SNITLB_MISS) | \ 212 (1ULL << INT_SN_NOTIFY) | \ 213 (1ULL << INT_SN_FIREWALL) | \ 214 (1ULL << INT_IDN_FIREWALL) | \ 215 (1ULL << INT_UDN_FIREWALL) | \ 216 (1ULL << INT_TILE_TIMER) | \ 217 (1ULL << INT_IDN_TIMER) | \ 218 (1ULL << INT_UDN_TIMER) | \ 219 (1ULL << INT_DMA_NOTIFY) | \ 220 (1ULL << INT_IDN_CA) | \ 221 (1ULL << INT_UDN_CA) | \ 222 (1ULL << INT_IDN_AVAIL) | \ 223 (1ULL << INT_UDN_AVAIL) | \ 224 (1ULL << INT_PERF_COUNT) | \ 225 (1ULL << INT_INTCTRL_3) | \ 226 (1ULL << INT_INTCTRL_2) | \ 227 (1ULL << INT_INTCTRL_1) | \ 228 (1ULL << INT_INTCTRL_0) | \ 229 (1ULL << INT_AUX_PERF_COUNT) | \ 230 0) 231 #define UNMASKABLE_INTERRUPTS ( \ 232 (1ULL << INT_ITLB_MISS) | \ 233 (1ULL << INT_ILL) | \ 234 (1ULL << INT_GPV) | \ 235 (1ULL << INT_SN_ACCESS) | \ 236 (1ULL << INT_IDN_ACCESS) | \ 237 (1ULL << INT_UDN_ACCESS) | \ 238 (1ULL << INT_SWINT_3) | \ 239 (1ULL << INT_SWINT_2) | \ 240 (1ULL << INT_SWINT_1) | \ 241 (1ULL << INT_SWINT_0) | \ 242 (1ULL << INT_UNALIGN_DATA) | \ 243 (1ULL << INT_DTLB_MISS) | \ 244 (1ULL << INT_DTLB_ACCESS) | \ 245 (1ULL << INT_BOOT_ACCESS) | \ 246 (1ULL << INT_WORLD_ACCESS) | \ 247 (1ULL << INT_I_ASID) | \ 248 (1ULL << INT_D_ASID) | \ 249 (1ULL << INT_DMA_ASID) | \ 250 (1ULL << INT_SNI_ASID) | \ 251 (1ULL << INT_DMA_CPL) | \ 252 (1ULL << INT_SN_CPL) | \ 253 (1ULL << INT_DOUBLE_FAULT) | \ 254 (1ULL << INT_SN_STATIC_ACCESS) | \ 255 0) 256 #define SYNC_INTERRUPTS ( \ 257 (1ULL << INT_ITLB_MISS) | \ 258 (1ULL << INT_ILL) | \ 259 (1ULL << INT_GPV) | \ 260 (1ULL << INT_SN_ACCESS) | \ 261 (1ULL << INT_IDN_ACCESS) | \ 262 (1ULL << INT_UDN_ACCESS) | \ 263 (1ULL << INT_IDN_REFILL) | \ 264 (1ULL << INT_UDN_REFILL) | \ 265 (1ULL << INT_IDN_COMPLETE) | \ 266 (1ULL << INT_UDN_COMPLETE) | \ 267 (1ULL << INT_SWINT_3) | \ 268 (1ULL << INT_SWINT_2) | \ 269 (1ULL << INT_SWINT_1) | \ 270 (1ULL << INT_SWINT_0) | \ 271 (1ULL << INT_UNALIGN_DATA) | \ 272 (1ULL << INT_DTLB_MISS) | \ 273 (1ULL << INT_DTLB_ACCESS) | \ 274 (1ULL << INT_SN_STATIC_ACCESS) | \ 275 0) 276 #define NON_SYNC_INTERRUPTS ( \ 277 (1ULL << INT_MEM_ERROR) | \ 278 (1ULL << INT_DMATLB_MISS) | \ 279 (1ULL << INT_DMATLB_ACCESS) | \ 280 (1ULL << INT_SNITLB_MISS) | \ 281 (1ULL << INT_SN_NOTIFY) | \ 282 (1ULL << INT_SN_FIREWALL) | \ 283 (1ULL << INT_IDN_FIREWALL) | \ 284 (1ULL << INT_UDN_FIREWALL) | \ 285 (1ULL << INT_TILE_TIMER) | \ 286 (1ULL << INT_IDN_TIMER) | \ 287 (1ULL << INT_UDN_TIMER) | \ 288 (1ULL << INT_DMA_NOTIFY) | \ 289 (1ULL << INT_IDN_CA) | \ 290 (1ULL << INT_UDN_CA) | \ 291 (1ULL << INT_IDN_AVAIL) | \ 292 (1ULL << INT_UDN_AVAIL) | \ 293 (1ULL << INT_PERF_COUNT) | \ 294 (1ULL << INT_INTCTRL_3) | \ 295 (1ULL << INT_INTCTRL_2) | \ 296 (1ULL << INT_INTCTRL_1) | \ 297 (1ULL << INT_INTCTRL_0) | \ 298 (1ULL << INT_BOOT_ACCESS) | \ 299 (1ULL << INT_WORLD_ACCESS) | \ 300 (1ULL << INT_I_ASID) | \ 301 (1ULL << INT_D_ASID) | \ 302 (1ULL << INT_DMA_ASID) | \ 303 (1ULL << INT_SNI_ASID) | \ 304 (1ULL << INT_DMA_CPL) | \ 305 (1ULL << INT_SN_CPL) | \ 306 (1ULL << INT_DOUBLE_FAULT) | \ 307 (1ULL << INT_AUX_PERF_COUNT) | \ 308 0) 309 #endif /* !__ASSEMBLER__ */ 310 #endif /* !__ARCH_INTERRUPTS_H__ */ 311