1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */ 2 /*!************************************************************************** 3 *! 4 *! MACROS: 5 *! IO_MASK(reg,field) 6 *! IO_STATE(reg,field,state) 7 *! IO_EXTRACT(reg,field,val) 8 *! IO_STATE_VALUE(reg,field,state) 9 *! IO_BITNR(reg,field) 10 *! IO_WIDTH(reg,field) 11 *! IO_FIELD(reg,field,val) 12 *! IO_RD(reg) 13 *! All moderegister addresses and fields of these. 14 *! 15 *!**************************************************************************/ 16 17 #ifndef __sv_addr_ag_h__ 18 #define __sv_addr_ag_h__ 19 20 21 #define __test_sv_addr__ 0 22 23 /*------------------------------------------------------------ 24 !* General macros to manipulate moderegisters. 25 !*-----------------------------------------------------------*/ 26 27 /* IO_MASK returns a mask for a specified bitfield in a register. 28 Note that this macro doesn't work when field width is 32 bits. */ 29 #define IO_MASK(reg, field) IO_MASK_ (reg##_, field##_) 30 #define IO_MASK_(reg_, field_) \ 31 ( ( ( 1 << reg_##_##field_##_WIDTH ) - 1 ) << reg_##_##field_##_BITNR ) 32 33 /* IO_STATE returns a constant corresponding to a one of the symbolic 34 states that the bitfield can have. (Shifted to correct position) */ 35 #define IO_STATE(reg, field, state) IO_STATE_ (reg##_, field##_, _##state) 36 #define IO_STATE_(reg_, field_, _state) \ 37 ( reg_##_##field_##_state << reg_##_##field_##_BITNR ) 38 39 /* IO_EXTRACT returns the masked and shifted value corresponding to the 40 bitfield can have. */ 41 #define IO_EXTRACT(reg, field, val) IO_EXTRACT_ (reg##_, field##_, val) 42 #define IO_EXTRACT_(reg_, field_, val) ( (( ( ( 1 << reg_##_##field_##_WIDTH ) \ 43 - 1 ) << reg_##_##field_##_BITNR ) & (val)) >> reg_##_##field_##_BITNR ) 44 45 /* IO_STATE_VALUE returns a constant corresponding to a one of the symbolic 46 states that the bitfield can have. (Not shifted) */ 47 #define IO_STATE_VALUE(reg, field, state) \ 48 IO_STATE_VALUE_ (reg##_, field##_, _##state) 49 #define IO_STATE_VALUE_(reg_, field_, _state) ( reg_##_##field_##_state ) 50 51 /* IO_FIELD shifts the val parameter to be aligned with the bitfield 52 specified. */ 53 #define IO_FIELD(reg, field, val) IO_FIELD_ (reg##_, field##_, val) 54 #define IO_FIELD_(reg_, field_, val) ((val) << reg_##_##field_##_BITNR) 55 56 /* IO_BITNR returns the starting bitnumber of a bitfield. Bit 0 is 57 LSB and the returned bitnumber is LSB of the field. */ 58 #define IO_BITNR(reg, field) IO_BITNR_ (reg##_, field##_) 59 #define IO_BITNR_(reg_, field_) (reg_##_##field_##_BITNR) 60 61 /* IO_WIDTH returns the width, in bits, of a bitfield. */ 62 #define IO_WIDTH(reg, field) IO_WIDTH_ (reg##_, field##_) 63 #define IO_WIDTH_(reg_, field_) (reg_##_##field_##_WIDTH) 64 65 /*--- Obsolete. Kept for backward compatibility. ---*/ 66 /* Reads (or writes) a byte/uword/udword from the specified mode 67 register. */ 68 #define IO_RD(reg) (*(volatile u32*)(reg)) 69 #define IO_RD_B(reg) (*(volatile u8*)(reg)) 70 #define IO_RD_W(reg) (*(volatile u16*)(reg)) 71 #define IO_RD_D(reg) (*(volatile u32*)(reg)) 72 73 /*------------------------------------------------------------ 74 !* Start addresses of the different memory areas. 75 !*-----------------------------------------------------------*/ 76 77 #define MEM_CSE0_START (0x00000000) 78 #define MEM_CSE0_SIZE (0x04000000) 79 #define MEM_CSE1_START (0x04000000) 80 #define MEM_CSE1_SIZE (0x04000000) 81 #define MEM_CSR0_START (0x08000000) 82 #define MEM_CSR1_START (0x0c000000) 83 #define MEM_CSP0_START (0x10000000) 84 #define MEM_CSP1_START (0x14000000) 85 #define MEM_CSP2_START (0x18000000) 86 #define MEM_CSP3_START (0x1c000000) 87 #define MEM_CSP4_START (0x20000000) 88 #define MEM_CSP5_START (0x24000000) 89 #define MEM_CSP6_START (0x28000000) 90 #define MEM_CSP7_START (0x2c000000) 91 #define MEM_DRAM_START (0x40000000) 92 93 #define MEM_NON_CACHEABLE (0x80000000) 94 95 /*------------------------------------------------------------ 96 !* Type casts used in mode register macros, making pointer 97 !* dereferencing possible. Empty in assembler. 98 !*-----------------------------------------------------------*/ 99 100 #ifndef __ASSEMBLER__ 101 # define IO_TYPECAST_UDWORD (volatile u32*) 102 # define IO_TYPECAST_RO_UDWORD (const volatile u32*) 103 # define IO_TYPECAST_UWORD (volatile u16*) 104 # define IO_TYPECAST_RO_UWORD (const volatile u16*) 105 # define IO_TYPECAST_BYTE (volatile u8*) 106 # define IO_TYPECAST_RO_BYTE (const volatile u8*) 107 #else 108 # define IO_TYPECAST_UDWORD 109 # define IO_TYPECAST_RO_UDWORD 110 # define IO_TYPECAST_UWORD 111 # define IO_TYPECAST_RO_UWORD 112 # define IO_TYPECAST_BYTE 113 # define IO_TYPECAST_RO_BYTE 114 #endif 115 116 /*------------------------------------------------------------*/ 117 118 #include <arch/sv_addr.agh> 119 120 #if __test_sv_addr__ 121 /* IO_MASK( R_BUS_CONFIG , CE ) */ 122 IO_MASK( R_WAITSTATES , SRAM_WS ) 123 IO_MASK( R_TEST , W32 ) 124 125 IO_STATE( R_BUS_CONFIG, CE, DISABLE ) 126 IO_STATE( R_BUS_CONFIG, CE, ENABLE ) 127 128 IO_STATE( R_DRAM_TIMING, REF, IVAL2 ) 129 130 IO_MASK( R_DRAM_TIMING, REF ) 131 132 IO_MASK( R_EXT_DMA_0_STAT, TFR_COUNT ) >> IO_BITNR( R_EXT_DMA_0_STAT, TFR_COUNT ) 133 134 IO_RD(R_EXT_DMA_0_STAT) & IO_MASK( R_EXT_DMA_0_STAT, S ) 135 == IO_STATE( R_EXT_DMA_0_STAT, S, STARTED ) 136 #endif 137 138 139 #endif /* ifndef __sv_addr_ag_h__ */ 140 141