1 /*
2 * Common prep/pmac/chrp boot and setup code.
3 */
4
5 #include <linux/module.h>
6 #include <linux/string.h>
7 #include <linux/sched.h>
8 #include <linux/init.h>
9 #include <linux/kernel.h>
10 #include <linux/reboot.h>
11 #include <linux/delay.h>
12 #include <linux/initrd.h>
13 #include <linux/tty.h>
14 #include <linux/seq_file.h>
15 #include <linux/root_dev.h>
16 #include <linux/cpu.h>
17 #include <linux/console.h>
18 #include <linux/memblock.h>
19 #include <linux/export.h>
20
21 #include <asm/io.h>
22 #include <asm/prom.h>
23 #include <asm/processor.h>
24 #include <asm/pgtable.h>
25 #include <asm/setup.h>
26 #include <asm/smp.h>
27 #include <asm/elf.h>
28 #include <asm/cputable.h>
29 #include <asm/bootx.h>
30 #include <asm/btext.h>
31 #include <asm/machdep.h>
32 #include <linux/uaccess.h>
33 #include <asm/pmac_feature.h>
34 #include <asm/sections.h>
35 #include <asm/nvram.h>
36 #include <asm/xmon.h>
37 #include <asm/time.h>
38 #include <asm/serial.h>
39 #include <asm/udbg.h>
40 #include <asm/code-patching.h>
41 #include <asm/cpu_has_feature.h>
42
43 #define DBG(fmt...)
44
45 extern void bootx_init(unsigned long r4, unsigned long phys);
46
47 int boot_cpuid_phys;
48 EXPORT_SYMBOL_GPL(boot_cpuid_phys);
49
50 int smp_hw_index[NR_CPUS];
51 EXPORT_SYMBOL(smp_hw_index);
52
53 unsigned long ISA_DMA_THRESHOLD;
54 unsigned int DMA_MODE_READ;
55 unsigned int DMA_MODE_WRITE;
56
57 EXPORT_SYMBOL(ISA_DMA_THRESHOLD);
58 EXPORT_SYMBOL(DMA_MODE_READ);
59 EXPORT_SYMBOL(DMA_MODE_WRITE);
60
61 /*
62 * We're called here very early in the boot.
63 *
64 * Note that the kernel may be running at an address which is different
65 * from the address that it was linked at, so we must use RELOC/PTRRELOC
66 * to access static data (including strings). -- paulus
67 */
early_init(unsigned long dt_ptr)68 notrace unsigned long __init early_init(unsigned long dt_ptr)
69 {
70 unsigned long offset = reloc_offset();
71
72 /* First zero the BSS -- use memset_io, some platforms don't have
73 * caches on yet */
74 memset_io((void __iomem *)PTRRELOC(&__bss_start), 0,
75 __bss_stop - __bss_start);
76
77 /*
78 * Identify the CPU type and fix up code sections
79 * that depend on which cpu we have.
80 */
81 identify_cpu(offset, mfspr(SPRN_PVR));
82
83 apply_feature_fixups();
84
85 return KERNELBASE + offset;
86 }
87
88
89 /*
90 * This is run before start_kernel(), the kernel has been relocated
91 * and we are running with enough of the MMU enabled to have our
92 * proper kernel virtual addresses
93 *
94 * We do the initial parsing of the flat device-tree and prepares
95 * for the MMU to be fully initialized.
96 */
97 extern unsigned int memset_nocache_branch; /* Insn to be replaced by NOP */
98
machine_init(u64 dt_ptr)99 notrace void __init machine_init(u64 dt_ptr)
100 {
101 unsigned int *addr = &memset_nocache_branch;
102 unsigned long insn;
103
104 /* Configure static keys first, now that we're relocated. */
105 setup_feature_keys();
106
107 /* Enable early debugging if any specified (see udbg.h) */
108 udbg_early_init();
109
110 patch_instruction((unsigned int *)&memcpy, PPC_INST_NOP);
111
112 insn = create_cond_branch(addr, branch_target(addr), 0x820000);
113 patch_instruction(addr, insn); /* replace b by bne cr0 */
114
115 /* Do some early initialization based on the flat device tree */
116 early_init_devtree(__va(dt_ptr));
117
118 early_init_mmu();
119
120 setup_kdump_trampoline();
121 }
122
123 /* Checks "l2cr=xxxx" command-line option */
ppc_setup_l2cr(char * str)124 int __init ppc_setup_l2cr(char *str)
125 {
126 if (cpu_has_feature(CPU_FTR_L2CR)) {
127 unsigned long val = simple_strtoul(str, NULL, 0);
128 printk(KERN_INFO "l2cr set to %lx\n", val);
129 _set_L2CR(0); /* force invalidate by disable cache */
130 _set_L2CR(val); /* and enable it */
131 }
132 return 1;
133 }
134 __setup("l2cr=", ppc_setup_l2cr);
135
136 /* Checks "l3cr=xxxx" command-line option */
ppc_setup_l3cr(char * str)137 int __init ppc_setup_l3cr(char *str)
138 {
139 if (cpu_has_feature(CPU_FTR_L3CR)) {
140 unsigned long val = simple_strtoul(str, NULL, 0);
141 printk(KERN_INFO "l3cr set to %lx\n", val);
142 _set_L3CR(val); /* and enable it */
143 }
144 return 1;
145 }
146 __setup("l3cr=", ppc_setup_l3cr);
147
148 #ifdef CONFIG_GENERIC_NVRAM
149
150 /* Generic nvram hooks used by drivers/char/gen_nvram.c */
nvram_read_byte(int addr)151 unsigned char nvram_read_byte(int addr)
152 {
153 if (ppc_md.nvram_read_val)
154 return ppc_md.nvram_read_val(addr);
155 return 0xff;
156 }
157 EXPORT_SYMBOL(nvram_read_byte);
158
nvram_write_byte(unsigned char val,int addr)159 void nvram_write_byte(unsigned char val, int addr)
160 {
161 if (ppc_md.nvram_write_val)
162 ppc_md.nvram_write_val(addr, val);
163 }
164 EXPORT_SYMBOL(nvram_write_byte);
165
nvram_get_size(void)166 ssize_t nvram_get_size(void)
167 {
168 if (ppc_md.nvram_size)
169 return ppc_md.nvram_size();
170 return -1;
171 }
172 EXPORT_SYMBOL(nvram_get_size);
173
nvram_sync(void)174 void nvram_sync(void)
175 {
176 if (ppc_md.nvram_sync)
177 ppc_md.nvram_sync();
178 }
179 EXPORT_SYMBOL(nvram_sync);
180
181 #endif /* CONFIG_NVRAM */
182
ppc_init(void)183 int __init ppc_init(void)
184 {
185 /* clear the progress line */
186 if (ppc_md.progress)
187 ppc_md.progress(" ", 0xffff);
188
189 /* call platform init */
190 if (ppc_md.init != NULL) {
191 ppc_md.init();
192 }
193 return 0;
194 }
195
196 arch_initcall(ppc_init);
197
irqstack_early_init(void)198 void __init irqstack_early_init(void)
199 {
200 unsigned int i;
201
202 /* interrupt stacks must be in lowmem, we get that for free on ppc32
203 * as the memblock is limited to lowmem by default */
204 for_each_possible_cpu(i) {
205 softirq_ctx[i] = (struct thread_info *)
206 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
207 hardirq_ctx[i] = (struct thread_info *)
208 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
209 }
210 }
211
212 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
exc_lvl_early_init(void)213 void __init exc_lvl_early_init(void)
214 {
215 unsigned int i, hw_cpu;
216
217 /* interrupt stacks must be in lowmem, we get that for free on ppc32
218 * as the memblock is limited to lowmem by MEMBLOCK_REAL_LIMIT */
219 for_each_possible_cpu(i) {
220 #ifdef CONFIG_SMP
221 hw_cpu = get_hard_smp_processor_id(i);
222 #else
223 hw_cpu = 0;
224 #endif
225
226 critirq_ctx[hw_cpu] = (struct thread_info *)
227 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
228 #ifdef CONFIG_BOOKE
229 dbgirq_ctx[hw_cpu] = (struct thread_info *)
230 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
231 mcheckirq_ctx[hw_cpu] = (struct thread_info *)
232 __va(memblock_alloc(THREAD_SIZE, THREAD_SIZE));
233 #endif
234 }
235 }
236 #endif
237
setup_power_save(void)238 void __init setup_power_save(void)
239 {
240 #ifdef CONFIG_6xx
241 if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
242 cpu_has_feature(CPU_FTR_CAN_NAP))
243 ppc_md.power_save = ppc6xx_idle;
244 #endif
245
246 #ifdef CONFIG_E500
247 if (cpu_has_feature(CPU_FTR_CAN_DOZE) ||
248 cpu_has_feature(CPU_FTR_CAN_NAP))
249 ppc_md.power_save = e500_idle;
250 #endif
251 }
252
initialize_cache_info(void)253 __init void initialize_cache_info(void)
254 {
255 /*
256 * Set cache line size based on type of cpu as a default.
257 * Systems with OF can look in the properties on the cpu node(s)
258 * for a possibly more accurate value.
259 */
260 dcache_bsize = cur_cpu_spec->dcache_bsize;
261 icache_bsize = cur_cpu_spec->icache_bsize;
262 ucache_bsize = 0;
263 if (cpu_has_feature(CPU_FTR_UNIFIED_ID_CACHE))
264 ucache_bsize = icache_bsize = dcache_bsize;
265 }
266