1 /*
2 * core.h - DesignWare HS OTG Controller common declarations
3 *
4 * Copyright (C) 2004-2013 Synopsys, Inc.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions, and the following disclaimer,
11 * without modification.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. The names of the above-listed copyright holders may not be used
16 * to endorse or promote products derived from this software without
17 * specific prior written permission.
18 *
19 * ALTERNATIVELY, this software may be distributed under the terms of the
20 * GNU General Public License ("GPL") as published by the Free Software
21 * Foundation; either version 2 of the License, or (at your option) any
22 * later version.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
25 * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
28 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
29 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
30 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
32 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
33 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
34 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 */
36
37 #ifndef __DWC2_CORE_H__
38 #define __DWC2_CORE_H__
39
40 #include <linux/phy/phy.h>
41 #include <linux/regulator/consumer.h>
42 #include <linux/usb/gadget.h>
43 #include <linux/usb/otg.h>
44 #include <linux/usb/phy.h>
45 #include "hw.h"
46
47 /*
48 * Suggested defines for tracers:
49 * - no_printk: Disable tracing
50 * - pr_info: Print this info to the console
51 * - trace_printk: Print this info to trace buffer (good for verbose logging)
52 */
53
54 #define DWC2_TRACE_SCHEDULER no_printk
55 #define DWC2_TRACE_SCHEDULER_VB no_printk
56
57 /* Detailed scheduler tracing, but won't overwhelm console */
58 #define dwc2_sch_dbg(hsotg, fmt, ...) \
59 DWC2_TRACE_SCHEDULER(pr_fmt("%s: SCH: " fmt), \
60 dev_name(hsotg->dev), ##__VA_ARGS__)
61
62 /* Verbose scheduler tracing */
63 #define dwc2_sch_vdbg(hsotg, fmt, ...) \
64 DWC2_TRACE_SCHEDULER_VB(pr_fmt("%s: SCH: " fmt), \
65 dev_name(hsotg->dev), ##__VA_ARGS__)
66
67 #ifdef CONFIG_MIPS
68 /*
69 * There are some MIPS machines that can run in either big-endian
70 * or little-endian mode and that use the dwc2 register without
71 * a byteswap in both ways.
72 * Unlike other architectures, MIPS apparently does not require a
73 * barrier before the __raw_writel() to synchronize with DMA but does
74 * require the barrier after the __raw_writel() to serialize a set of
75 * writes. This set of operations was added specifically for MIPS and
76 * should only be used there.
77 */
dwc2_readl(const void __iomem * addr)78 static inline u32 dwc2_readl(const void __iomem *addr)
79 {
80 u32 value = __raw_readl(addr);
81
82 /* In order to preserve endianness __raw_* operation is used. Therefore
83 * a barrier is needed to ensure IO access is not re-ordered across
84 * reads or writes
85 */
86 mb();
87 return value;
88 }
89
dwc2_writel(u32 value,void __iomem * addr)90 static inline void dwc2_writel(u32 value, void __iomem *addr)
91 {
92 __raw_writel(value, addr);
93
94 /*
95 * In order to preserve endianness __raw_* operation is used. Therefore
96 * a barrier is needed to ensure IO access is not re-ordered across
97 * reads or writes
98 */
99 mb();
100 #ifdef DWC2_LOG_WRITES
101 pr_info("INFO:: wrote %08x to %p\n", value, addr);
102 #endif
103 }
104 #else
105 /* Normal architectures just use readl/write */
dwc2_readl(const void __iomem * addr)106 static inline u32 dwc2_readl(const void __iomem *addr)
107 {
108 return readl(addr);
109 }
110
dwc2_writel(u32 value,void __iomem * addr)111 static inline void dwc2_writel(u32 value, void __iomem *addr)
112 {
113 writel(value, addr);
114
115 #ifdef DWC2_LOG_WRITES
116 pr_info("info:: wrote %08x to %p\n", value, addr);
117 #endif
118 }
119 #endif
120
121 /* Maximum number of Endpoints/HostChannels */
122 #define MAX_EPS_CHANNELS 16
123
124 /* dwc2-hsotg declarations */
125 static const char * const dwc2_hsotg_supply_names[] = {
126 "vusb_d", /* digital USB supply, 1.2V */
127 "vusb_a", /* analog USB supply, 1.1V */
128 };
129
130 #define DWC2_NUM_SUPPLIES ARRAY_SIZE(dwc2_hsotg_supply_names)
131
132 /*
133 * EP0_MPS_LIMIT
134 *
135 * Unfortunately there seems to be a limit of the amount of data that can
136 * be transferred by IN transactions on EP0. This is either 127 bytes or 3
137 * packets (which practically means 1 packet and 63 bytes of data) when the
138 * MPS is set to 64.
139 *
140 * This means if we are wanting to move >127 bytes of data, we need to
141 * split the transactions up, but just doing one packet at a time does
142 * not work (this may be an implicit DATA0 PID on first packet of the
143 * transaction) and doing 2 packets is outside the controller's limits.
144 *
145 * If we try to lower the MPS size for EP0, then no transfers work properly
146 * for EP0, and the system will fail basic enumeration. As no cause for this
147 * has currently been found, we cannot support any large IN transfers for
148 * EP0.
149 */
150 #define EP0_MPS_LIMIT 64
151
152 struct dwc2_hsotg;
153 struct dwc2_hsotg_req;
154
155 /**
156 * struct dwc2_hsotg_ep - driver endpoint definition.
157 * @ep: The gadget layer representation of the endpoint.
158 * @name: The driver generated name for the endpoint.
159 * @queue: Queue of requests for this endpoint.
160 * @parent: Reference back to the parent device structure.
161 * @req: The current request that the endpoint is processing. This is
162 * used to indicate an request has been loaded onto the endpoint
163 * and has yet to be completed (maybe due to data move, or simply
164 * awaiting an ack from the core all the data has been completed).
165 * @debugfs: File entry for debugfs file for this endpoint.
166 * @lock: State lock to protect contents of endpoint.
167 * @dir_in: Set to true if this endpoint is of the IN direction, which
168 * means that it is sending data to the Host.
169 * @index: The index for the endpoint registers.
170 * @mc: Multi Count - number of transactions per microframe
171 * @interval - Interval for periodic endpoints, in frames or microframes.
172 * @name: The name array passed to the USB core.
173 * @halted: Set if the endpoint has been halted.
174 * @periodic: Set if this is a periodic ep, such as Interrupt
175 * @isochronous: Set if this is a isochronous ep
176 * @send_zlp: Set if we need to send a zero-length packet.
177 * @desc_list_dma: The DMA address of descriptor chain currently in use.
178 * @desc_list: Pointer to descriptor DMA chain head currently in use.
179 * @desc_count: Count of entries within the DMA descriptor chain of EP.
180 * @isoc_chain_num: Number of ISOC chain currently in use - either 0 or 1.
181 * @next_desc: index of next free descriptor in the ISOC chain under SW control.
182 * @total_data: The total number of data bytes done.
183 * @fifo_size: The size of the FIFO (for periodic IN endpoints)
184 * @fifo_load: The amount of data loaded into the FIFO (periodic IN)
185 * @last_load: The offset of data for the last start of request.
186 * @size_loaded: The last loaded size for DxEPTSIZE for periodic IN
187 * @target_frame: Targeted frame num to setup next ISOC transfer
188 * @frame_overrun: Indicates SOF number overrun in DSTS
189 *
190 * This is the driver's state for each registered enpoint, allowing it
191 * to keep track of transactions that need doing. Each endpoint has a
192 * lock to protect the state, to try and avoid using an overall lock
193 * for the host controller as much as possible.
194 *
195 * For periodic IN endpoints, we have fifo_size and fifo_load to try
196 * and keep track of the amount of data in the periodic FIFO for each
197 * of these as we don't have a status register that tells us how much
198 * is in each of them. (note, this may actually be useless information
199 * as in shared-fifo mode periodic in acts like a single-frame packet
200 * buffer than a fifo)
201 */
202 struct dwc2_hsotg_ep {
203 struct usb_ep ep;
204 struct list_head queue;
205 struct dwc2_hsotg *parent;
206 struct dwc2_hsotg_req *req;
207 struct dentry *debugfs;
208
209 unsigned long total_data;
210 unsigned int size_loaded;
211 unsigned int last_load;
212 unsigned int fifo_load;
213 unsigned short fifo_size;
214 unsigned short fifo_index;
215
216 unsigned char dir_in;
217 unsigned char index;
218 unsigned char mc;
219 u16 interval;
220
221 unsigned int halted:1;
222 unsigned int periodic:1;
223 unsigned int isochronous:1;
224 unsigned int send_zlp:1;
225 unsigned int target_frame;
226 #define TARGET_FRAME_INITIAL 0xFFFFFFFF
227 bool frame_overrun;
228
229 dma_addr_t desc_list_dma;
230 struct dwc2_dma_desc *desc_list;
231 u8 desc_count;
232
233 unsigned char isoc_chain_num;
234 unsigned int next_desc;
235
236 char name[10];
237 };
238
239 /**
240 * struct dwc2_hsotg_req - data transfer request
241 * @req: The USB gadget request
242 * @queue: The list of requests for the endpoint this is queued for.
243 * @saved_req_buf: variable to save req.buf when bounce buffers are used.
244 */
245 struct dwc2_hsotg_req {
246 struct usb_request req;
247 struct list_head queue;
248 void *saved_req_buf;
249 };
250
251 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
252 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
253 #define call_gadget(_hs, _entry) \
254 do { \
255 if ((_hs)->gadget.speed != USB_SPEED_UNKNOWN && \
256 (_hs)->driver && (_hs)->driver->_entry) { \
257 spin_unlock(&_hs->lock); \
258 (_hs)->driver->_entry(&(_hs)->gadget); \
259 spin_lock(&_hs->lock); \
260 } \
261 } while (0)
262 #else
263 #define call_gadget(_hs, _entry) do {} while (0)
264 #endif
265
266 struct dwc2_hsotg;
267 struct dwc2_host_chan;
268
269 /* Device States */
270 enum dwc2_lx_state {
271 DWC2_L0, /* On state */
272 DWC2_L1, /* LPM sleep state */
273 DWC2_L2, /* USB suspend state */
274 DWC2_L3, /* Off state */
275 };
276
277 /* Gadget ep0 states */
278 enum dwc2_ep0_state {
279 DWC2_EP0_SETUP,
280 DWC2_EP0_DATA_IN,
281 DWC2_EP0_DATA_OUT,
282 DWC2_EP0_STATUS_IN,
283 DWC2_EP0_STATUS_OUT,
284 };
285
286 /**
287 * struct dwc2_core_params - Parameters for configuring the core
288 *
289 * @otg_cap: Specifies the OTG capabilities.
290 * 0 - HNP and SRP capable
291 * 1 - SRP Only capable
292 * 2 - No HNP/SRP capable (always available)
293 * Defaults to best available option (0, 1, then 2)
294 * @host_dma: Specifies whether to use slave or DMA mode for accessing
295 * the data FIFOs. The driver will automatically detect the
296 * value for this parameter if none is specified.
297 * 0 - Slave (always available)
298 * 1 - DMA (default, if available)
299 * @dma_desc_enable: When DMA mode is enabled, specifies whether to use
300 * address DMA mode or descriptor DMA mode for accessing
301 * the data FIFOs. The driver will automatically detect the
302 * value for this if none is specified.
303 * 0 - Address DMA
304 * 1 - Descriptor DMA (default, if available)
305 * @dma_desc_fs_enable: When DMA mode is enabled, specifies whether to use
306 * address DMA mode or descriptor DMA mode for accessing
307 * the data FIFOs in Full Speed mode only. The driver
308 * will automatically detect the value for this if none is
309 * specified.
310 * 0 - Address DMA
311 * 1 - Descriptor DMA in FS (default, if available)
312 * @speed: Specifies the maximum speed of operation in host and
313 * device mode. The actual speed depends on the speed of
314 * the attached device and the value of phy_type.
315 * 0 - High Speed
316 * (default when phy_type is UTMI+ or ULPI)
317 * 1 - Full Speed
318 * (default when phy_type is Full Speed)
319 * @enable_dynamic_fifo: 0 - Use coreConsultant-specified FIFO size parameters
320 * 1 - Allow dynamic FIFO sizing (default, if available)
321 * @en_multiple_tx_fifo: Specifies whether dedicated per-endpoint transmit FIFOs
322 * are enabled for non-periodic IN endpoints in device
323 * mode.
324 * @host_rx_fifo_size: Number of 4-byte words in the Rx FIFO in host mode when
325 * dynamic FIFO sizing is enabled
326 * 16 to 32768
327 * Actual maximum value is autodetected and also
328 * the default.
329 * @host_nperio_tx_fifo_size: Number of 4-byte words in the non-periodic Tx FIFO
330 * in host mode when dynamic FIFO sizing is enabled
331 * 16 to 32768
332 * Actual maximum value is autodetected and also
333 * the default.
334 * @host_perio_tx_fifo_size: Number of 4-byte words in the periodic Tx FIFO in
335 * host mode when dynamic FIFO sizing is enabled
336 * 16 to 32768
337 * Actual maximum value is autodetected and also
338 * the default.
339 * @max_transfer_size: The maximum transfer size supported, in bytes
340 * 2047 to 65,535
341 * Actual maximum value is autodetected and also
342 * the default.
343 * @max_packet_count: The maximum number of packets in a transfer
344 * 15 to 511
345 * Actual maximum value is autodetected and also
346 * the default.
347 * @host_channels: The number of host channel registers to use
348 * 1 to 16
349 * Actual maximum value is autodetected and also
350 * the default.
351 * @phy_type: Specifies the type of PHY interface to use. By default,
352 * the driver will automatically detect the phy_type.
353 * 0 - Full Speed Phy
354 * 1 - UTMI+ Phy
355 * 2 - ULPI Phy
356 * Defaults to best available option (2, 1, then 0)
357 * @phy_utmi_width: Specifies the UTMI+ Data Width (in bits). This parameter
358 * is applicable for a phy_type of UTMI+ or ULPI. (For a
359 * ULPI phy_type, this parameter indicates the data width
360 * between the MAC and the ULPI Wrapper.) Also, this
361 * parameter is applicable only if the OTG_HSPHY_WIDTH cC
362 * parameter was set to "8 and 16 bits", meaning that the
363 * core has been configured to work at either data path
364 * width.
365 * 8 or 16 (default 16 if available)
366 * @phy_ulpi_ddr: Specifies whether the ULPI operates at double or single
367 * data rate. This parameter is only applicable if phy_type
368 * is ULPI.
369 * 0 - single data rate ULPI interface with 8 bit wide
370 * data bus (default)
371 * 1 - double data rate ULPI interface with 4 bit wide
372 * data bus
373 * @phy_ulpi_ext_vbus: For a ULPI phy, specifies whether to use the internal or
374 * external supply to drive the VBus
375 * 0 - Internal supply (default)
376 * 1 - External supply
377 * @i2c_enable: Specifies whether to use the I2Cinterface for a full
378 * speed PHY. This parameter is only applicable if phy_type
379 * is FS.
380 * 0 - No (default)
381 * 1 - Yes
382 * @ulpi_fs_ls: Make ULPI phy operate in FS/LS mode only
383 * 0 - No (default)
384 * 1 - Yes
385 * @host_support_fs_ls_low_power: Specifies whether low power mode is supported
386 * when attached to a Full Speed or Low Speed device in
387 * host mode.
388 * 0 - Don't support low power mode (default)
389 * 1 - Support low power mode
390 * @host_ls_low_power_phy_clk: Specifies the PHY clock rate in low power mode
391 * when connected to a Low Speed device in host
392 * mode. This parameter is applicable only if
393 * host_support_fs_ls_low_power is enabled.
394 * 0 - 48 MHz
395 * (default when phy_type is UTMI+ or ULPI)
396 * 1 - 6 MHz
397 * (default when phy_type is Full Speed)
398 * @ts_dline: Enable Term Select Dline pulsing
399 * 0 - No (default)
400 * 1 - Yes
401 * @reload_ctl: Allow dynamic reloading of HFIR register during runtime
402 * 0 - No (default for core < 2.92a)
403 * 1 - Yes (default for core >= 2.92a)
404 * @ahbcfg: This field allows the default value of the GAHBCFG
405 * register to be overridden
406 * -1 - GAHBCFG value will be set to 0x06
407 * (INCR4, default)
408 * all others - GAHBCFG value will be overridden with
409 * this value
410 * Not all bits can be controlled like this, the
411 * bits defined by GAHBCFG_CTRL_MASK are controlled
412 * by the driver and are ignored in this
413 * configuration value.
414 * @uframe_sched: True to enable the microframe scheduler
415 * @external_id_pin_ctl: Specifies whether ID pin is handled externally.
416 * Disable CONIDSTSCHNG controller interrupt in such
417 * case.
418 * 0 - No (default)
419 * 1 - Yes
420 * @hibernation: Specifies whether the controller support hibernation.
421 * If hibernation is enabled, the controller will enter
422 * hibernation in both peripheral and host mode when
423 * needed.
424 * 0 - No (default)
425 * 1 - Yes
426 * @activate_stm_fs_transceiver: Activate internal transceiver using GGPIO
427 * register.
428 * 0 - Deactivate the transceiver (default)
429 * 1 - Activate the transceiver
430 * @g_dma: Enables gadget dma usage (default: autodetect).
431 * @g_dma_desc: Enables gadget descriptor DMA (default: autodetect).
432 * @g_rx_fifo_size: The periodic rx fifo size for the device, in
433 * DWORDS from 16-32768 (default: 2048 if
434 * possible, otherwise autodetect).
435 * @g_np_tx_fifo_size: The non-periodic tx fifo size for the device in
436 * DWORDS from 16-32768 (default: 1024 if
437 * possible, otherwise autodetect).
438 * @g_tx_fifo_size: An array of TX fifo sizes in dedicated fifo
439 * mode. Each value corresponds to one EP
440 * starting from EP1 (max 15 values). Sizes are
441 * in DWORDS with possible values from from
442 * 16-32768 (default: 256, 256, 256, 256, 768,
443 * 768, 768, 768, 0, 0, 0, 0, 0, 0, 0).
444 * @change_speed_quirk: Change speed configuration to DWC2_SPEED_PARAM_FULL
445 * while full&low speed device connect. And change speed
446 * back to DWC2_SPEED_PARAM_HIGH while device is gone.
447 * 0 - No (default)
448 * 1 - Yes
449 *
450 * The following parameters may be specified when starting the module. These
451 * parameters define how the DWC_otg controller should be configured. A
452 * value of -1 (or any other out of range value) for any parameter means
453 * to read the value from hardware (if possible) or use the builtin
454 * default described above.
455 */
456 struct dwc2_core_params {
457 u8 otg_cap;
458 #define DWC2_CAP_PARAM_HNP_SRP_CAPABLE 0
459 #define DWC2_CAP_PARAM_SRP_ONLY_CAPABLE 1
460 #define DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE 2
461
462 u8 phy_type;
463 #define DWC2_PHY_TYPE_PARAM_FS 0
464 #define DWC2_PHY_TYPE_PARAM_UTMI 1
465 #define DWC2_PHY_TYPE_PARAM_ULPI 2
466
467 u8 speed;
468 #define DWC2_SPEED_PARAM_HIGH 0
469 #define DWC2_SPEED_PARAM_FULL 1
470 #define DWC2_SPEED_PARAM_LOW 2
471
472 u8 phy_utmi_width;
473 bool phy_ulpi_ddr;
474 bool phy_ulpi_ext_vbus;
475 bool enable_dynamic_fifo;
476 bool en_multiple_tx_fifo;
477 bool i2c_enable;
478 bool ulpi_fs_ls;
479 bool ts_dline;
480 bool reload_ctl;
481 bool uframe_sched;
482 bool external_id_pin_ctl;
483 bool hibernation;
484 bool activate_stm_fs_transceiver;
485 u16 max_packet_count;
486 u32 max_transfer_size;
487 u32 ahbcfg;
488
489 /* Host parameters */
490 bool host_dma;
491 bool dma_desc_enable;
492 bool dma_desc_fs_enable;
493 bool host_support_fs_ls_low_power;
494 bool host_ls_low_power_phy_clk;
495
496 u8 host_channels;
497 u16 host_rx_fifo_size;
498 u16 host_nperio_tx_fifo_size;
499 u16 host_perio_tx_fifo_size;
500
501 /* Gadget parameters */
502 bool g_dma;
503 bool g_dma_desc;
504 u32 g_rx_fifo_size;
505 u32 g_np_tx_fifo_size;
506 u32 g_tx_fifo_size[MAX_EPS_CHANNELS];
507
508 bool change_speed_quirk;
509 };
510
511 /**
512 * struct dwc2_hw_params - Autodetected parameters.
513 *
514 * These parameters are the various parameters read from hardware
515 * registers during initialization. They typically contain the best
516 * supported or maximum value that can be configured in the
517 * corresponding dwc2_core_params value.
518 *
519 * The values that are not in dwc2_core_params are documented below.
520 *
521 * @op_mode Mode of Operation
522 * 0 - HNP- and SRP-Capable OTG (Host & Device)
523 * 1 - SRP-Capable OTG (Host & Device)
524 * 2 - Non-HNP and Non-SRP Capable OTG (Host & Device)
525 * 3 - SRP-Capable Device
526 * 4 - Non-OTG Device
527 * 5 - SRP-Capable Host
528 * 6 - Non-OTG Host
529 * @arch Architecture
530 * 0 - Slave only
531 * 1 - External DMA
532 * 2 - Internal DMA
533 * @power_optimized Are power optimizations enabled?
534 * @num_dev_ep Number of device endpoints available
535 * @num_dev_perio_in_ep Number of device periodic IN endpoints
536 * available
537 * @dev_token_q_depth Device Mode IN Token Sequence Learning Queue
538 * Depth
539 * 0 to 30
540 * @host_perio_tx_q_depth
541 * Host Mode Periodic Request Queue Depth
542 * 2, 4 or 8
543 * @nperio_tx_q_depth
544 * Non-Periodic Request Queue Depth
545 * 2, 4 or 8
546 * @hs_phy_type High-speed PHY interface type
547 * 0 - High-speed interface not supported
548 * 1 - UTMI+
549 * 2 - ULPI
550 * 3 - UTMI+ and ULPI
551 * @fs_phy_type Full-speed PHY interface type
552 * 0 - Full speed interface not supported
553 * 1 - Dedicated full speed interface
554 * 2 - FS pins shared with UTMI+ pins
555 * 3 - FS pins shared with ULPI pins
556 * @total_fifo_size: Total internal RAM for FIFOs (bytes)
557 * @utmi_phy_data_width UTMI+ PHY data width
558 * 0 - 8 bits
559 * 1 - 16 bits
560 * 2 - 8 or 16 bits
561 * @snpsid: Value from SNPSID register
562 * @dev_ep_dirs: Direction of device endpoints (GHWCFG1)
563 */
564 struct dwc2_hw_params {
565 unsigned op_mode:3;
566 unsigned arch:2;
567 unsigned dma_desc_enable:1;
568 unsigned enable_dynamic_fifo:1;
569 unsigned en_multiple_tx_fifo:1;
570 unsigned rx_fifo_size:16;
571 unsigned host_nperio_tx_fifo_size:16;
572 unsigned dev_nperio_tx_fifo_size:16;
573 unsigned host_perio_tx_fifo_size:16;
574 unsigned nperio_tx_q_depth:3;
575 unsigned host_perio_tx_q_depth:3;
576 unsigned dev_token_q_depth:5;
577 unsigned max_transfer_size:26;
578 unsigned max_packet_count:11;
579 unsigned host_channels:5;
580 unsigned hs_phy_type:2;
581 unsigned fs_phy_type:2;
582 unsigned i2c_enable:1;
583 unsigned num_dev_ep:4;
584 unsigned num_dev_perio_in_ep:4;
585 unsigned total_fifo_size:16;
586 unsigned power_optimized:1;
587 unsigned utmi_phy_data_width:2;
588 u32 snpsid;
589 u32 dev_ep_dirs;
590 };
591
592 /* Size of control and EP0 buffers */
593 #define DWC2_CTRL_BUFF_SIZE 8
594
595 /**
596 * struct dwc2_gregs_backup - Holds global registers state before
597 * entering partial power down
598 * @gotgctl: Backup of GOTGCTL register
599 * @gintmsk: Backup of GINTMSK register
600 * @gahbcfg: Backup of GAHBCFG register
601 * @gusbcfg: Backup of GUSBCFG register
602 * @grxfsiz: Backup of GRXFSIZ register
603 * @gnptxfsiz: Backup of GNPTXFSIZ register
604 * @gi2cctl: Backup of GI2CCTL register
605 * @hptxfsiz: Backup of HPTXFSIZ register
606 * @gdfifocfg: Backup of GDFIFOCFG register
607 * @dtxfsiz: Backup of DTXFSIZ registers for each endpoint
608 * @gpwrdn: Backup of GPWRDN register
609 */
610 struct dwc2_gregs_backup {
611 u32 gotgctl;
612 u32 gintmsk;
613 u32 gahbcfg;
614 u32 gusbcfg;
615 u32 grxfsiz;
616 u32 gnptxfsiz;
617 u32 gi2cctl;
618 u32 hptxfsiz;
619 u32 pcgcctl;
620 u32 gdfifocfg;
621 u32 dtxfsiz[MAX_EPS_CHANNELS];
622 u32 gpwrdn;
623 bool valid;
624 };
625
626 /**
627 * struct dwc2_dregs_backup - Holds device registers state before
628 * entering partial power down
629 * @dcfg: Backup of DCFG register
630 * @dctl: Backup of DCTL register
631 * @daintmsk: Backup of DAINTMSK register
632 * @diepmsk: Backup of DIEPMSK register
633 * @doepmsk: Backup of DOEPMSK register
634 * @diepctl: Backup of DIEPCTL register
635 * @dieptsiz: Backup of DIEPTSIZ register
636 * @diepdma: Backup of DIEPDMA register
637 * @doepctl: Backup of DOEPCTL register
638 * @doeptsiz: Backup of DOEPTSIZ register
639 * @doepdma: Backup of DOEPDMA register
640 */
641 struct dwc2_dregs_backup {
642 u32 dcfg;
643 u32 dctl;
644 u32 daintmsk;
645 u32 diepmsk;
646 u32 doepmsk;
647 u32 diepctl[MAX_EPS_CHANNELS];
648 u32 dieptsiz[MAX_EPS_CHANNELS];
649 u32 diepdma[MAX_EPS_CHANNELS];
650 u32 doepctl[MAX_EPS_CHANNELS];
651 u32 doeptsiz[MAX_EPS_CHANNELS];
652 u32 doepdma[MAX_EPS_CHANNELS];
653 bool valid;
654 };
655
656 /**
657 * struct dwc2_hregs_backup - Holds host registers state before
658 * entering partial power down
659 * @hcfg: Backup of HCFG register
660 * @haintmsk: Backup of HAINTMSK register
661 * @hcintmsk: Backup of HCINTMSK register
662 * @hptr0: Backup of HPTR0 register
663 * @hfir: Backup of HFIR register
664 */
665 struct dwc2_hregs_backup {
666 u32 hcfg;
667 u32 haintmsk;
668 u32 hcintmsk[MAX_EPS_CHANNELS];
669 u32 hprt0;
670 u32 hfir;
671 bool valid;
672 };
673
674 /*
675 * Constants related to high speed periodic scheduling
676 *
677 * We have a periodic schedule that is DWC2_HS_SCHEDULE_UFRAMES long. From a
678 * reservation point of view it's assumed that the schedule goes right back to
679 * the beginning after the end of the schedule.
680 *
681 * What does that mean for scheduling things with a long interval? It means
682 * we'll reserve time for them in every possible microframe that they could
683 * ever be scheduled in. ...but we'll still only actually schedule them as
684 * often as they were requested.
685 *
686 * We keep our schedule in a "bitmap" structure. This simplifies having
687 * to keep track of and merge intervals: we just let the bitmap code do most
688 * of the heavy lifting. In a way scheduling is much like memory allocation.
689 *
690 * We schedule 100us per uframe or 80% of 125us (the maximum amount you're
691 * supposed to schedule for periodic transfers). That's according to spec.
692 *
693 * Note that though we only schedule 80% of each microframe, the bitmap that we
694 * keep the schedule in is tightly packed (AKA it doesn't have 100us worth of
695 * space for each uFrame).
696 *
697 * Requirements:
698 * - DWC2_HS_SCHEDULE_UFRAMES must even divide 0x4000 (HFNUM_MAX_FRNUM + 1)
699 * - DWC2_HS_SCHEDULE_UFRAMES must be 8 times DWC2_LS_SCHEDULE_FRAMES (probably
700 * could be any multiple of 8 times DWC2_LS_SCHEDULE_FRAMES, but there might
701 * be bugs). The 8 comes from the USB spec: number of microframes per frame.
702 */
703 #define DWC2_US_PER_UFRAME 125
704 #define DWC2_HS_PERIODIC_US_PER_UFRAME 100
705
706 #define DWC2_HS_SCHEDULE_UFRAMES 8
707 #define DWC2_HS_SCHEDULE_US (DWC2_HS_SCHEDULE_UFRAMES * \
708 DWC2_HS_PERIODIC_US_PER_UFRAME)
709
710 /*
711 * Constants related to low speed scheduling
712 *
713 * For high speed we schedule every 1us. For low speed that's a bit overkill,
714 * so we make up a unit called a "slice" that's worth 25us. There are 40
715 * slices in a full frame and we can schedule 36 of those (90%) for periodic
716 * transfers.
717 *
718 * Our low speed schedule can be as short as 1 frame or could be longer. When
719 * we only schedule 1 frame it means that we'll need to reserve a time every
720 * frame even for things that only transfer very rarely, so something that runs
721 * every 2048 frames will get time reserved in every frame. Our low speed
722 * schedule can be longer and we'll be able to handle more overlap, but that
723 * will come at increased memory cost and increased time to schedule.
724 *
725 * Note: one other advantage of a short low speed schedule is that if we mess
726 * up and miss scheduling we can jump in and use any of the slots that we
727 * happened to reserve.
728 *
729 * With 25 us per slice and 1 frame in the schedule, we only need 4 bytes for
730 * the schedule. There will be one schedule per TT.
731 *
732 * Requirements:
733 * - DWC2_US_PER_SLICE must evenly divide DWC2_LS_PERIODIC_US_PER_FRAME.
734 */
735 #define DWC2_US_PER_SLICE 25
736 #define DWC2_SLICES_PER_UFRAME (DWC2_US_PER_UFRAME / DWC2_US_PER_SLICE)
737
738 #define DWC2_ROUND_US_TO_SLICE(us) \
739 (DIV_ROUND_UP((us), DWC2_US_PER_SLICE) * \
740 DWC2_US_PER_SLICE)
741
742 #define DWC2_LS_PERIODIC_US_PER_FRAME \
743 900
744 #define DWC2_LS_PERIODIC_SLICES_PER_FRAME \
745 (DWC2_LS_PERIODIC_US_PER_FRAME / \
746 DWC2_US_PER_SLICE)
747
748 #define DWC2_LS_SCHEDULE_FRAMES 1
749 #define DWC2_LS_SCHEDULE_SLICES (DWC2_LS_SCHEDULE_FRAMES * \
750 DWC2_LS_PERIODIC_SLICES_PER_FRAME)
751
752 /**
753 * struct dwc2_hsotg - Holds the state of the driver, including the non-periodic
754 * and periodic schedules
755 *
756 * These are common for both host and peripheral modes:
757 *
758 * @dev: The struct device pointer
759 * @regs: Pointer to controller regs
760 * @hw_params: Parameters that were autodetected from the
761 * hardware registers
762 * @core_params: Parameters that define how the core should be configured
763 * @op_state: The operational State, during transitions (a_host=>
764 * a_peripheral and b_device=>b_host) this may not match
765 * the core, but allows the software to determine
766 * transitions
767 * @dr_mode: Requested mode of operation, one of following:
768 * - USB_DR_MODE_PERIPHERAL
769 * - USB_DR_MODE_HOST
770 * - USB_DR_MODE_OTG
771 * @hcd_enabled Host mode sub-driver initialization indicator.
772 * @gadget_enabled Peripheral mode sub-driver initialization indicator.
773 * @ll_hw_enabled Status of low-level hardware resources.
774 * @phy: The otg phy transceiver structure for phy control.
775 * @uphy: The otg phy transceiver structure for old USB phy
776 * control.
777 * @plat: The platform specific configuration data. This can be
778 * removed once all SoCs support usb transceiver.
779 * @supplies: Definition of USB power supplies
780 * @phyif: PHY interface width
781 * @lock: Spinlock that protects all the driver data structures
782 * @priv: Stores a pointer to the struct usb_hcd
783 * @queuing_high_bandwidth: True if multiple packets of a high-bandwidth
784 * transfer are in process of being queued
785 * @srp_success: Stores status of SRP request in the case of a FS PHY
786 * with an I2C interface
787 * @wq_otg: Workqueue object used for handling of some interrupts
788 * @wf_otg: Work object for handling Connector ID Status Change
789 * interrupt
790 * @wkp_timer: Timer object for handling Wakeup Detected interrupt
791 * @lx_state: Lx state of connected device
792 * @gregs_backup: Backup of global registers during suspend
793 * @dregs_backup: Backup of device registers during suspend
794 * @hregs_backup: Backup of host registers during suspend
795 *
796 * These are for host mode:
797 *
798 * @flags: Flags for handling root port state changes
799 * @non_periodic_sched_inactive: Inactive QHs in the non-periodic schedule.
800 * Transfers associated with these QHs are not currently
801 * assigned to a host channel.
802 * @non_periodic_sched_active: Active QHs in the non-periodic schedule.
803 * Transfers associated with these QHs are currently
804 * assigned to a host channel.
805 * @non_periodic_qh_ptr: Pointer to next QH to process in the active
806 * non-periodic schedule
807 * @periodic_sched_inactive: Inactive QHs in the periodic schedule. This is a
808 * list of QHs for periodic transfers that are _not_
809 * scheduled for the next frame. Each QH in the list has an
810 * interval counter that determines when it needs to be
811 * scheduled for execution. This scheduling mechanism
812 * allows only a simple calculation for periodic bandwidth
813 * used (i.e. must assume that all periodic transfers may
814 * need to execute in the same frame). However, it greatly
815 * simplifies scheduling and should be sufficient for the
816 * vast majority of OTG hosts, which need to connect to a
817 * small number of peripherals at one time. Items move from
818 * this list to periodic_sched_ready when the QH interval
819 * counter is 0 at SOF.
820 * @periodic_sched_ready: List of periodic QHs that are ready for execution in
821 * the next frame, but have not yet been assigned to host
822 * channels. Items move from this list to
823 * periodic_sched_assigned as host channels become
824 * available during the current frame.
825 * @periodic_sched_assigned: List of periodic QHs to be executed in the next
826 * frame that are assigned to host channels. Items move
827 * from this list to periodic_sched_queued as the
828 * transactions for the QH are queued to the DWC_otg
829 * controller.
830 * @periodic_sched_queued: List of periodic QHs that have been queued for
831 * execution. Items move from this list to either
832 * periodic_sched_inactive or periodic_sched_ready when the
833 * channel associated with the transfer is released. If the
834 * interval for the QH is 1, the item moves to
835 * periodic_sched_ready because it must be rescheduled for
836 * the next frame. Otherwise, the item moves to
837 * periodic_sched_inactive.
838 * @split_order: List keeping track of channels doing splits, in order.
839 * @periodic_usecs: Total bandwidth claimed so far for periodic transfers.
840 * This value is in microseconds per (micro)frame. The
841 * assumption is that all periodic transfers may occur in
842 * the same (micro)frame.
843 * @hs_periodic_bitmap: Bitmap used by the microframe scheduler any time the
844 * host is in high speed mode; low speed schedules are
845 * stored elsewhere since we need one per TT.
846 * @frame_number: Frame number read from the core at SOF. The value ranges
847 * from 0 to HFNUM_MAX_FRNUM.
848 * @periodic_qh_count: Count of periodic QHs, if using several eps. Used for
849 * SOF enable/disable.
850 * @free_hc_list: Free host channels in the controller. This is a list of
851 * struct dwc2_host_chan items.
852 * @periodic_channels: Number of host channels assigned to periodic transfers.
853 * Currently assuming that there is a dedicated host
854 * channel for each periodic transaction and at least one
855 * host channel is available for non-periodic transactions.
856 * @non_periodic_channels: Number of host channels assigned to non-periodic
857 * transfers
858 * @available_host_channels Number of host channels available for the microframe
859 * scheduler to use
860 * @hc_ptr_array: Array of pointers to the host channel descriptors.
861 * Allows accessing a host channel descriptor given the
862 * host channel number. This is useful in interrupt
863 * handlers.
864 * @status_buf: Buffer used for data received during the status phase of
865 * a control transfer.
866 * @status_buf_dma: DMA address for status_buf
867 * @start_work: Delayed work for handling host A-cable connection
868 * @reset_work: Delayed work for handling a port reset
869 * @otg_port: OTG port number
870 * @frame_list: Frame list
871 * @frame_list_dma: Frame list DMA address
872 * @frame_list_sz: Frame list size
873 * @desc_gen_cache: Kmem cache for generic descriptors
874 * @desc_hsisoc_cache: Kmem cache for hs isochronous descriptors
875 * @unaligned_cache: Kmem cache for DMA mode to handle non-aligned buf
876 *
877 * These are for peripheral mode:
878 *
879 * @driver: USB gadget driver
880 * @dedicated_fifos: Set if the hardware has dedicated IN-EP fifos.
881 * @num_of_eps: Number of available EPs (excluding EP0)
882 * @debug_root: Root directrory for debugfs.
883 * @debug_file: Main status file for debugfs.
884 * @debug_testmode: Testmode status file for debugfs.
885 * @debug_fifo: FIFO status file for debugfs.
886 * @ep0_reply: Request used for ep0 reply.
887 * @ep0_buff: Buffer for EP0 reply data, if needed.
888 * @ctrl_buff: Buffer for EP0 control requests.
889 * @ctrl_req: Request for EP0 control packets.
890 * @ep0_state: EP0 control transfers state
891 * @test_mode: USB test mode requested by the host
892 * @setup_desc_dma: EP0 setup stage desc chain DMA address
893 * @setup_desc: EP0 setup stage desc chain pointer
894 * @ctrl_in_desc_dma: EP0 IN data phase desc chain DMA address
895 * @ctrl_in_desc: EP0 IN data phase desc chain pointer
896 * @ctrl_out_desc_dma: EP0 OUT data phase desc chain DMA address
897 * @ctrl_out_desc: EP0 OUT data phase desc chain pointer
898 * @eps: The endpoints being supplied to the gadget framework
899 */
900 struct dwc2_hsotg {
901 struct device *dev;
902 void __iomem *regs;
903 /** Params detected from hardware */
904 struct dwc2_hw_params hw_params;
905 /** Params to actually use */
906 struct dwc2_core_params params;
907 enum usb_otg_state op_state;
908 enum usb_dr_mode dr_mode;
909 unsigned int hcd_enabled:1;
910 unsigned int gadget_enabled:1;
911 unsigned int ll_hw_enabled:1;
912
913 struct phy *phy;
914 struct usb_phy *uphy;
915 struct dwc2_hsotg_plat *plat;
916 struct regulator_bulk_data supplies[DWC2_NUM_SUPPLIES];
917 u32 phyif;
918
919 spinlock_t lock;
920 void *priv;
921 int irq;
922 struct clk *clk;
923 struct reset_control *reset;
924
925 unsigned int queuing_high_bandwidth:1;
926 unsigned int srp_success:1;
927
928 struct workqueue_struct *wq_otg;
929 struct work_struct wf_otg;
930 struct timer_list wkp_timer;
931 enum dwc2_lx_state lx_state;
932 struct dwc2_gregs_backup gr_backup;
933 struct dwc2_dregs_backup dr_backup;
934 struct dwc2_hregs_backup hr_backup;
935
936 struct dentry *debug_root;
937 struct debugfs_regset32 *regset;
938
939 /* DWC OTG HW Release versions */
940 #define DWC2_CORE_REV_2_71a 0x4f54271a
941 #define DWC2_CORE_REV_2_90a 0x4f54290a
942 #define DWC2_CORE_REV_2_91a 0x4f54291a
943 #define DWC2_CORE_REV_2_92a 0x4f54292a
944 #define DWC2_CORE_REV_2_94a 0x4f54294a
945 #define DWC2_CORE_REV_3_00a 0x4f54300a
946 #define DWC2_CORE_REV_3_10a 0x4f54310a
947 #define DWC2_FS_IOT_REV_1_00a 0x5531100a
948 #define DWC2_HS_IOT_REV_1_00a 0x5532100a
949
950 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
951 union dwc2_hcd_internal_flags {
952 u32 d32;
953 struct {
954 unsigned port_connect_status_change:1;
955 unsigned port_connect_status:1;
956 unsigned port_reset_change:1;
957 unsigned port_enable_change:1;
958 unsigned port_suspend_change:1;
959 unsigned port_over_current_change:1;
960 unsigned port_l1_change:1;
961 unsigned reserved:25;
962 } b;
963 } flags;
964
965 struct list_head non_periodic_sched_inactive;
966 struct list_head non_periodic_sched_active;
967 struct list_head *non_periodic_qh_ptr;
968 struct list_head periodic_sched_inactive;
969 struct list_head periodic_sched_ready;
970 struct list_head periodic_sched_assigned;
971 struct list_head periodic_sched_queued;
972 struct list_head split_order;
973 u16 periodic_usecs;
974 unsigned long hs_periodic_bitmap[
975 DIV_ROUND_UP(DWC2_HS_SCHEDULE_US, BITS_PER_LONG)];
976 u16 frame_number;
977 u16 periodic_qh_count;
978 bool bus_suspended;
979 bool new_connection;
980
981 u16 last_frame_num;
982
983 #ifdef CONFIG_USB_DWC2_TRACK_MISSED_SOFS
984 #define FRAME_NUM_ARRAY_SIZE 1000
985 u16 *frame_num_array;
986 u16 *last_frame_num_array;
987 int frame_num_idx;
988 int dumped_frame_num_array;
989 #endif
990
991 struct list_head free_hc_list;
992 int periodic_channels;
993 int non_periodic_channels;
994 int available_host_channels;
995 struct dwc2_host_chan *hc_ptr_array[MAX_EPS_CHANNELS];
996 u8 *status_buf;
997 dma_addr_t status_buf_dma;
998 #define DWC2_HCD_STATUS_BUF_SIZE 64
999
1000 struct delayed_work start_work;
1001 struct delayed_work reset_work;
1002 u8 otg_port;
1003 u32 *frame_list;
1004 dma_addr_t frame_list_dma;
1005 u32 frame_list_sz;
1006 struct kmem_cache *desc_gen_cache;
1007 struct kmem_cache *desc_hsisoc_cache;
1008 struct kmem_cache *unaligned_cache;
1009 #define DWC2_KMEM_UNALIGNED_BUF_SIZE 1024
1010
1011 #ifdef DEBUG
1012 u32 frrem_samples;
1013 u64 frrem_accum;
1014
1015 u32 hfnum_7_samples_a;
1016 u64 hfnum_7_frrem_accum_a;
1017 u32 hfnum_0_samples_a;
1018 u64 hfnum_0_frrem_accum_a;
1019 u32 hfnum_other_samples_a;
1020 u64 hfnum_other_frrem_accum_a;
1021
1022 u32 hfnum_7_samples_b;
1023 u64 hfnum_7_frrem_accum_b;
1024 u32 hfnum_0_samples_b;
1025 u64 hfnum_0_frrem_accum_b;
1026 u32 hfnum_other_samples_b;
1027 u64 hfnum_other_frrem_accum_b;
1028 #endif
1029 #endif /* CONFIG_USB_DWC2_HOST || CONFIG_USB_DWC2_DUAL_ROLE */
1030
1031 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1032 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1033 /* Gadget structures */
1034 struct usb_gadget_driver *driver;
1035 int fifo_mem;
1036 unsigned int dedicated_fifos:1;
1037 unsigned char num_of_eps;
1038 u32 fifo_map;
1039
1040 struct usb_request *ep0_reply;
1041 struct usb_request *ctrl_req;
1042 void *ep0_buff;
1043 void *ctrl_buff;
1044 enum dwc2_ep0_state ep0_state;
1045 u8 test_mode;
1046
1047 dma_addr_t setup_desc_dma[2];
1048 struct dwc2_dma_desc *setup_desc[2];
1049 dma_addr_t ctrl_in_desc_dma;
1050 struct dwc2_dma_desc *ctrl_in_desc;
1051 dma_addr_t ctrl_out_desc_dma;
1052 struct dwc2_dma_desc *ctrl_out_desc;
1053
1054 struct usb_gadget gadget;
1055 unsigned int enabled:1;
1056 unsigned int connected:1;
1057 struct dwc2_hsotg_ep *eps_in[MAX_EPS_CHANNELS];
1058 struct dwc2_hsotg_ep *eps_out[MAX_EPS_CHANNELS];
1059 #endif /* CONFIG_USB_DWC2_PERIPHERAL || CONFIG_USB_DWC2_DUAL_ROLE */
1060 };
1061
1062 /* Reasons for halting a host channel */
1063 enum dwc2_halt_status {
1064 DWC2_HC_XFER_NO_HALT_STATUS,
1065 DWC2_HC_XFER_COMPLETE,
1066 DWC2_HC_XFER_URB_COMPLETE,
1067 DWC2_HC_XFER_ACK,
1068 DWC2_HC_XFER_NAK,
1069 DWC2_HC_XFER_NYET,
1070 DWC2_HC_XFER_STALL,
1071 DWC2_HC_XFER_XACT_ERR,
1072 DWC2_HC_XFER_FRAME_OVERRUN,
1073 DWC2_HC_XFER_BABBLE_ERR,
1074 DWC2_HC_XFER_DATA_TOGGLE_ERR,
1075 DWC2_HC_XFER_AHB_ERR,
1076 DWC2_HC_XFER_PERIODIC_INCOMPLETE,
1077 DWC2_HC_XFER_URB_DEQUEUE,
1078 };
1079
1080 /* Core version information */
dwc2_is_iot(struct dwc2_hsotg * hsotg)1081 static inline bool dwc2_is_iot(struct dwc2_hsotg *hsotg)
1082 {
1083 return (hsotg->hw_params.snpsid & 0xfff00000) == 0x55300000;
1084 }
1085
dwc2_is_fs_iot(struct dwc2_hsotg * hsotg)1086 static inline bool dwc2_is_fs_iot(struct dwc2_hsotg *hsotg)
1087 {
1088 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55310000;
1089 }
1090
dwc2_is_hs_iot(struct dwc2_hsotg * hsotg)1091 static inline bool dwc2_is_hs_iot(struct dwc2_hsotg *hsotg)
1092 {
1093 return (hsotg->hw_params.snpsid & 0xffff0000) == 0x55320000;
1094 }
1095
1096 /*
1097 * The following functions support initialization of the core driver component
1098 * and the DWC_otg controller
1099 */
1100 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait);
1101 int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg);
1102 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg);
1103 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, bool restore);
1104
1105 bool dwc2_force_mode_if_needed(struct dwc2_hsotg *hsotg, bool host);
1106 void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg);
1107 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg);
1108
1109 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg);
1110
1111 /*
1112 * Common core Functions.
1113 * The following functions support managing the DWC_otg controller in either
1114 * device or host mode.
1115 */
1116 void dwc2_read_packet(struct dwc2_hsotg *hsotg, u8 *dest, u16 bytes);
1117 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num);
1118 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg);
1119
1120 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hcd);
1121 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hcd);
1122
1123 /* This function should be called on every hardware interrupt. */
1124 irqreturn_t dwc2_handle_common_intr(int irq, void *dev);
1125
1126 /* The device ID match table */
1127 extern const struct of_device_id dwc2_of_match_table[];
1128
1129 int dwc2_lowlevel_hw_enable(struct dwc2_hsotg *hsotg);
1130 int dwc2_lowlevel_hw_disable(struct dwc2_hsotg *hsotg);
1131
1132 /* Parameters */
1133 int dwc2_get_hwparams(struct dwc2_hsotg *hsotg);
1134 int dwc2_init_params(struct dwc2_hsotg *hsotg);
1135
1136 /*
1137 * The following functions check the controller's OTG operation mode
1138 * capability (GHWCFG2.OTG_MODE).
1139 *
1140 * These functions can be used before the internal hsotg->hw_params
1141 * are read in and cached so they always read directly from the
1142 * GHWCFG2 register.
1143 */
1144 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg);
1145 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg);
1146 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg);
1147 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg);
1148
1149 /*
1150 * Returns the mode of operation, host or device
1151 */
dwc2_is_host_mode(struct dwc2_hsotg * hsotg)1152 static inline int dwc2_is_host_mode(struct dwc2_hsotg *hsotg)
1153 {
1154 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) != 0;
1155 }
1156
dwc2_is_device_mode(struct dwc2_hsotg * hsotg)1157 static inline int dwc2_is_device_mode(struct dwc2_hsotg *hsotg)
1158 {
1159 return (dwc2_readl(hsotg->regs + GINTSTS) & GINTSTS_CURMODE_HOST) == 0;
1160 }
1161
1162 /*
1163 * Dump core registers and SPRAM
1164 */
1165 void dwc2_dump_dev_registers(struct dwc2_hsotg *hsotg);
1166 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg);
1167 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg);
1168
1169 /* Gadget defines */
1170 #if IS_ENABLED(CONFIG_USB_DWC2_PERIPHERAL) || \
1171 IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1172 int dwc2_hsotg_remove(struct dwc2_hsotg *hsotg);
1173 int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2);
1174 int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2);
1175 int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq);
1176 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1177 bool reset);
1178 void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg);
1179 void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2);
1180 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg, int testmode);
1181 #define dwc2_is_device_connected(hsotg) (hsotg->connected)
1182 int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg);
1183 int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg);
1184 int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg);
1185 int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg);
1186 int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg);
1187 #else
dwc2_hsotg_remove(struct dwc2_hsotg * dwc2)1188 static inline int dwc2_hsotg_remove(struct dwc2_hsotg *dwc2)
1189 { return 0; }
dwc2_hsotg_suspend(struct dwc2_hsotg * dwc2)1190 static inline int dwc2_hsotg_suspend(struct dwc2_hsotg *dwc2)
1191 { return 0; }
dwc2_hsotg_resume(struct dwc2_hsotg * dwc2)1192 static inline int dwc2_hsotg_resume(struct dwc2_hsotg *dwc2)
1193 { return 0; }
dwc2_gadget_init(struct dwc2_hsotg * hsotg,int irq)1194 static inline int dwc2_gadget_init(struct dwc2_hsotg *hsotg, int irq)
1195 { return 0; }
dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg * dwc2,bool reset)1196 static inline void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg *dwc2,
1197 bool reset) {}
dwc2_hsotg_core_connect(struct dwc2_hsotg * hsotg)1198 static inline void dwc2_hsotg_core_connect(struct dwc2_hsotg *hsotg) {}
dwc2_hsotg_disconnect(struct dwc2_hsotg * dwc2)1199 static inline void dwc2_hsotg_disconnect(struct dwc2_hsotg *dwc2) {}
dwc2_hsotg_set_test_mode(struct dwc2_hsotg * hsotg,int testmode)1200 static inline int dwc2_hsotg_set_test_mode(struct dwc2_hsotg *hsotg,
1201 int testmode)
1202 { return 0; }
1203 #define dwc2_is_device_connected(hsotg) (0)
dwc2_backup_device_registers(struct dwc2_hsotg * hsotg)1204 static inline int dwc2_backup_device_registers(struct dwc2_hsotg *hsotg)
1205 { return 0; }
dwc2_restore_device_registers(struct dwc2_hsotg * hsotg)1206 static inline int dwc2_restore_device_registers(struct dwc2_hsotg *hsotg)
1207 { return 0; }
dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg * hsotg)1208 static inline int dwc2_hsotg_tx_fifo_count(struct dwc2_hsotg *hsotg)
1209 { return 0; }
dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg * hsotg)1210 static inline int dwc2_hsotg_tx_fifo_total_depth(struct dwc2_hsotg *hsotg)
1211 { return 0; }
dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg * hsotg)1212 static inline int dwc2_hsotg_tx_fifo_average_depth(struct dwc2_hsotg *hsotg)
1213 { return 0; }
1214 #endif
1215
1216 #if IS_ENABLED(CONFIG_USB_DWC2_HOST) || IS_ENABLED(CONFIG_USB_DWC2_DUAL_ROLE)
1217 int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg);
1218 int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg, int us);
1219 void dwc2_hcd_connect(struct dwc2_hsotg *hsotg);
1220 void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force);
1221 void dwc2_hcd_start(struct dwc2_hsotg *hsotg);
1222 int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg);
1223 int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg);
1224 #else
dwc2_hcd_get_frame_number(struct dwc2_hsotg * hsotg)1225 static inline int dwc2_hcd_get_frame_number(struct dwc2_hsotg *hsotg)
1226 { return 0; }
dwc2_hcd_get_future_frame_number(struct dwc2_hsotg * hsotg,int us)1227 static inline int dwc2_hcd_get_future_frame_number(struct dwc2_hsotg *hsotg,
1228 int us)
1229 { return 0; }
dwc2_hcd_connect(struct dwc2_hsotg * hsotg)1230 static inline void dwc2_hcd_connect(struct dwc2_hsotg *hsotg) {}
dwc2_hcd_disconnect(struct dwc2_hsotg * hsotg,bool force)1231 static inline void dwc2_hcd_disconnect(struct dwc2_hsotg *hsotg, bool force) {}
dwc2_hcd_start(struct dwc2_hsotg * hsotg)1232 static inline void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {}
dwc2_hcd_remove(struct dwc2_hsotg * hsotg)1233 static inline void dwc2_hcd_remove(struct dwc2_hsotg *hsotg) {}
dwc2_hcd_init(struct dwc2_hsotg * hsotg)1234 static inline int dwc2_hcd_init(struct dwc2_hsotg *hsotg)
1235 { return 0; }
dwc2_backup_host_registers(struct dwc2_hsotg * hsotg)1236 static inline int dwc2_backup_host_registers(struct dwc2_hsotg *hsotg)
1237 { return 0; }
dwc2_restore_host_registers(struct dwc2_hsotg * hsotg)1238 static inline int dwc2_restore_host_registers(struct dwc2_hsotg *hsotg)
1239 { return 0; }
1240
1241 #endif
1242
1243 #endif /* __DWC2_CORE_H__ */
1244