1 /*
2 * Copyright (C) 2016 Texas Instruments
3 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18 #ifndef __OMAP_DRM_DSS_H
19 #define __OMAP_DRM_DSS_H
20
21 #include <linux/list.h>
22 #include <linux/kobject.h>
23 #include <linux/device.h>
24 #include <linux/interrupt.h>
25 #include <video/videomode.h>
26 #include <linux/platform_data/omapdss.h>
27 #include <uapi/drm/drm_mode.h>
28 #include <drm/drm_crtc.h>
29
30 #define DISPC_IRQ_FRAMEDONE (1 << 0)
31 #define DISPC_IRQ_VSYNC (1 << 1)
32 #define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
33 #define DISPC_IRQ_EVSYNC_ODD (1 << 3)
34 #define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
35 #define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
36 #define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
37 #define DISPC_IRQ_GFX_END_WIN (1 << 7)
38 #define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
39 #define DISPC_IRQ_OCP_ERR (1 << 9)
40 #define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
41 #define DISPC_IRQ_VID1_END_WIN (1 << 11)
42 #define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
43 #define DISPC_IRQ_VID2_END_WIN (1 << 13)
44 #define DISPC_IRQ_SYNC_LOST (1 << 14)
45 #define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
46 #define DISPC_IRQ_WAKEUP (1 << 16)
47 #define DISPC_IRQ_SYNC_LOST2 (1 << 17)
48 #define DISPC_IRQ_VSYNC2 (1 << 18)
49 #define DISPC_IRQ_VID3_END_WIN (1 << 19)
50 #define DISPC_IRQ_VID3_FIFO_UNDERFLOW (1 << 20)
51 #define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
52 #define DISPC_IRQ_FRAMEDONE2 (1 << 22)
53 #define DISPC_IRQ_FRAMEDONEWB (1 << 23)
54 #define DISPC_IRQ_FRAMEDONETV (1 << 24)
55 #define DISPC_IRQ_WBBUFFEROVERFLOW (1 << 25)
56 #define DISPC_IRQ_WBUNCOMPLETEERROR (1 << 26)
57 #define DISPC_IRQ_SYNC_LOST3 (1 << 27)
58 #define DISPC_IRQ_VSYNC3 (1 << 28)
59 #define DISPC_IRQ_ACBIAS_COUNT_STAT3 (1 << 29)
60 #define DISPC_IRQ_FRAMEDONE3 (1 << 30)
61
62 struct omap_dss_device;
63 struct dss_lcd_mgr_config;
64 struct snd_aes_iec958;
65 struct snd_cea_861_aud_if;
66 struct hdmi_avi_infoframe;
67
68 enum omap_display_type {
69 OMAP_DISPLAY_TYPE_NONE = 0,
70 OMAP_DISPLAY_TYPE_DPI = 1 << 0,
71 OMAP_DISPLAY_TYPE_DBI = 1 << 1,
72 OMAP_DISPLAY_TYPE_SDI = 1 << 2,
73 OMAP_DISPLAY_TYPE_DSI = 1 << 3,
74 OMAP_DISPLAY_TYPE_VENC = 1 << 4,
75 OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
76 OMAP_DISPLAY_TYPE_DVI = 1 << 6,
77 };
78
79 enum omap_plane_id {
80 OMAP_DSS_GFX = 0,
81 OMAP_DSS_VIDEO1 = 1,
82 OMAP_DSS_VIDEO2 = 2,
83 OMAP_DSS_VIDEO3 = 3,
84 OMAP_DSS_WB = 4,
85 };
86
87 enum omap_channel {
88 OMAP_DSS_CHANNEL_LCD = 0,
89 OMAP_DSS_CHANNEL_DIGIT = 1,
90 OMAP_DSS_CHANNEL_LCD2 = 2,
91 OMAP_DSS_CHANNEL_LCD3 = 3,
92 OMAP_DSS_CHANNEL_WB = 4,
93 };
94
95 enum omap_color_mode {
96 _UNUSED_,
97 };
98
99 enum omap_dss_load_mode {
100 OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
101 OMAP_DSS_LOAD_CLUT_ONLY = 1,
102 OMAP_DSS_LOAD_FRAME_ONLY = 2,
103 OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
104 };
105
106 enum omap_dss_trans_key_type {
107 OMAP_DSS_COLOR_KEY_GFX_DST = 0,
108 OMAP_DSS_COLOR_KEY_VID_SRC = 1,
109 };
110
111 enum omap_dss_signal_level {
112 OMAPDSS_SIG_ACTIVE_LOW,
113 OMAPDSS_SIG_ACTIVE_HIGH,
114 };
115
116 enum omap_dss_signal_edge {
117 OMAPDSS_DRIVE_SIG_FALLING_EDGE,
118 OMAPDSS_DRIVE_SIG_RISING_EDGE,
119 };
120
121 enum omap_dss_venc_type {
122 OMAP_DSS_VENC_TYPE_COMPOSITE,
123 OMAP_DSS_VENC_TYPE_SVIDEO,
124 };
125
126 enum omap_dss_dsi_pixel_format {
127 OMAP_DSS_DSI_FMT_RGB888,
128 OMAP_DSS_DSI_FMT_RGB666,
129 OMAP_DSS_DSI_FMT_RGB666_PACKED,
130 OMAP_DSS_DSI_FMT_RGB565,
131 };
132
133 enum omap_dss_dsi_mode {
134 OMAP_DSS_DSI_CMD_MODE = 0,
135 OMAP_DSS_DSI_VIDEO_MODE,
136 };
137
138 enum omap_display_caps {
139 OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
140 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
141 };
142
143 enum omap_dss_display_state {
144 OMAP_DSS_DISPLAY_DISABLED = 0,
145 OMAP_DSS_DISPLAY_ACTIVE,
146 };
147
148 enum omap_dss_rotation_type {
149 OMAP_DSS_ROT_NONE = 0,
150 OMAP_DSS_ROT_TILER = 1 << 0,
151 };
152
153 enum omap_overlay_caps {
154 OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
155 OMAP_DSS_OVL_CAP_GLOBAL_ALPHA = 1 << 1,
156 OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA = 1 << 2,
157 OMAP_DSS_OVL_CAP_ZORDER = 1 << 3,
158 OMAP_DSS_OVL_CAP_POS = 1 << 4,
159 OMAP_DSS_OVL_CAP_REPLICATION = 1 << 5,
160 };
161
162 enum omap_dss_clk_source {
163 OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
164 * OMAP4: DSS_FCLK */
165 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
166 * OMAP4: PLL1_CLK1 */
167 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
168 * OMAP4: PLL1_CLK2 */
169 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
170 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
171 };
172
173 enum omap_hdmi_flags {
174 OMAP_HDMI_SDA_SCL_EXTERNAL_PULLUP = 1 << 0,
175 };
176
177 enum omap_dss_output_id {
178 OMAP_DSS_OUTPUT_DPI = 1 << 0,
179 OMAP_DSS_OUTPUT_DBI = 1 << 1,
180 OMAP_DSS_OUTPUT_SDI = 1 << 2,
181 OMAP_DSS_OUTPUT_DSI1 = 1 << 3,
182 OMAP_DSS_OUTPUT_DSI2 = 1 << 4,
183 OMAP_DSS_OUTPUT_VENC = 1 << 5,
184 OMAP_DSS_OUTPUT_HDMI = 1 << 6,
185 };
186
187 /* DSI */
188
189 enum omap_dss_dsi_trans_mode {
190 /* Sync Pulses: both sync start and end packets sent */
191 OMAP_DSS_DSI_PULSE_MODE,
192 /* Sync Events: only sync start packets sent */
193 OMAP_DSS_DSI_EVENT_MODE,
194 /* Burst: only sync start packets sent, pixels are time compressed */
195 OMAP_DSS_DSI_BURST_MODE,
196 };
197
198 struct omap_dss_dsi_videomode_timings {
199 unsigned long hsclk;
200
201 unsigned ndl;
202 unsigned bitspp;
203
204 /* pixels */
205 u16 hact;
206 /* lines */
207 u16 vact;
208
209 /* DSI video mode blanking data */
210 /* Unit: byte clock cycles */
211 u16 hss;
212 u16 hsa;
213 u16 hse;
214 u16 hfp;
215 u16 hbp;
216 /* Unit: line clocks */
217 u16 vsa;
218 u16 vfp;
219 u16 vbp;
220
221 /* DSI blanking modes */
222 int blanking_mode;
223 int hsa_blanking_mode;
224 int hbp_blanking_mode;
225 int hfp_blanking_mode;
226
227 enum omap_dss_dsi_trans_mode trans_mode;
228
229 bool ddr_clk_always_on;
230 int window_sync;
231 };
232
233 struct omap_dss_dsi_config {
234 enum omap_dss_dsi_mode mode;
235 enum omap_dss_dsi_pixel_format pixel_format;
236 const struct videomode *vm;
237
238 unsigned long hs_clk_min, hs_clk_max;
239 unsigned long lp_clk_min, lp_clk_max;
240
241 bool ddr_clk_always_on;
242 enum omap_dss_dsi_trans_mode trans_mode;
243 };
244
245 struct omap_dss_cpr_coefs {
246 s16 rr, rg, rb;
247 s16 gr, gg, gb;
248 s16 br, bg, bb;
249 };
250
251 struct omap_overlay_info {
252 dma_addr_t paddr;
253 dma_addr_t p_uv_addr; /* for NV12 format */
254 u16 screen_width;
255 u16 width;
256 u16 height;
257 u32 fourcc;
258 u8 rotation;
259 enum omap_dss_rotation_type rotation_type;
260
261 u16 pos_x;
262 u16 pos_y;
263 u16 out_width; /* if 0, out_width == width */
264 u16 out_height; /* if 0, out_height == height */
265 u8 global_alpha;
266 u8 pre_mult_alpha;
267 u8 zorder;
268 };
269
270 struct omap_overlay_manager_info {
271 u32 default_color;
272
273 enum omap_dss_trans_key_type trans_key_type;
274 u32 trans_key;
275 bool trans_enabled;
276
277 bool partial_alpha_enabled;
278
279 bool cpr_enable;
280 struct omap_dss_cpr_coefs cpr_coefs;
281 };
282
283 /* 22 pins means 1 clk lane and 10 data lanes */
284 #define OMAP_DSS_MAX_DSI_PINS 22
285
286 struct omap_dsi_pin_config {
287 int num_pins;
288 /*
289 * pin numbers in the following order:
290 * clk+, clk-
291 * data1+, data1-
292 * data2+, data2-
293 * ...
294 */
295 int pins[OMAP_DSS_MAX_DSI_PINS];
296 };
297
298 struct omap_dss_writeback_info {
299 u32 paddr;
300 u32 p_uv_addr;
301 u16 buf_width;
302 u16 width;
303 u16 height;
304 u32 fourcc;
305 u8 rotation;
306 enum omap_dss_rotation_type rotation_type;
307 u8 pre_mult_alpha;
308 };
309
310 struct omapdss_dpi_ops {
311 int (*connect)(struct omap_dss_device *dssdev,
312 struct omap_dss_device *dst);
313 void (*disconnect)(struct omap_dss_device *dssdev,
314 struct omap_dss_device *dst);
315
316 int (*enable)(struct omap_dss_device *dssdev);
317 void (*disable)(struct omap_dss_device *dssdev);
318
319 int (*check_timings)(struct omap_dss_device *dssdev,
320 struct videomode *vm);
321 void (*set_timings)(struct omap_dss_device *dssdev,
322 struct videomode *vm);
323 void (*get_timings)(struct omap_dss_device *dssdev,
324 struct videomode *vm);
325 };
326
327 struct omapdss_sdi_ops {
328 int (*connect)(struct omap_dss_device *dssdev,
329 struct omap_dss_device *dst);
330 void (*disconnect)(struct omap_dss_device *dssdev,
331 struct omap_dss_device *dst);
332
333 int (*enable)(struct omap_dss_device *dssdev);
334 void (*disable)(struct omap_dss_device *dssdev);
335
336 int (*check_timings)(struct omap_dss_device *dssdev,
337 struct videomode *vm);
338 void (*set_timings)(struct omap_dss_device *dssdev,
339 struct videomode *vm);
340 void (*get_timings)(struct omap_dss_device *dssdev,
341 struct videomode *vm);
342 };
343
344 struct omapdss_dvi_ops {
345 int (*connect)(struct omap_dss_device *dssdev,
346 struct omap_dss_device *dst);
347 void (*disconnect)(struct omap_dss_device *dssdev,
348 struct omap_dss_device *dst);
349
350 int (*enable)(struct omap_dss_device *dssdev);
351 void (*disable)(struct omap_dss_device *dssdev);
352
353 int (*check_timings)(struct omap_dss_device *dssdev,
354 struct videomode *vm);
355 void (*set_timings)(struct omap_dss_device *dssdev,
356 struct videomode *vm);
357 void (*get_timings)(struct omap_dss_device *dssdev,
358 struct videomode *vm);
359 };
360
361 struct omapdss_atv_ops {
362 int (*connect)(struct omap_dss_device *dssdev,
363 struct omap_dss_device *dst);
364 void (*disconnect)(struct omap_dss_device *dssdev,
365 struct omap_dss_device *dst);
366
367 int (*enable)(struct omap_dss_device *dssdev);
368 void (*disable)(struct omap_dss_device *dssdev);
369
370 int (*check_timings)(struct omap_dss_device *dssdev,
371 struct videomode *vm);
372 void (*set_timings)(struct omap_dss_device *dssdev,
373 struct videomode *vm);
374 void (*get_timings)(struct omap_dss_device *dssdev,
375 struct videomode *vm);
376
377 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
378 u32 (*get_wss)(struct omap_dss_device *dssdev);
379 };
380
381 struct omapdss_hdmi_ops {
382 int (*connect)(struct omap_dss_device *dssdev,
383 struct omap_dss_device *dst);
384 void (*disconnect)(struct omap_dss_device *dssdev,
385 struct omap_dss_device *dst);
386
387 int (*enable)(struct omap_dss_device *dssdev);
388 void (*disable)(struct omap_dss_device *dssdev);
389
390 int (*check_timings)(struct omap_dss_device *dssdev,
391 struct videomode *vm);
392 void (*set_timings)(struct omap_dss_device *dssdev,
393 struct videomode *vm);
394 void (*get_timings)(struct omap_dss_device *dssdev,
395 struct videomode *vm);
396
397 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
398 bool (*detect)(struct omap_dss_device *dssdev);
399
400 int (*register_hpd_cb)(struct omap_dss_device *dssdev,
401 void (*cb)(void *cb_data,
402 enum drm_connector_status status),
403 void *cb_data);
404 void (*unregister_hpd_cb)(struct omap_dss_device *dssdev);
405 void (*enable_hpd)(struct omap_dss_device *dssdev);
406 void (*disable_hpd)(struct omap_dss_device *dssdev);
407
408 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
409 int (*set_infoframe)(struct omap_dss_device *dssdev,
410 const struct hdmi_avi_infoframe *avi);
411 };
412
413 struct omapdss_dsi_ops {
414 int (*connect)(struct omap_dss_device *dssdev,
415 struct omap_dss_device *dst);
416 void (*disconnect)(struct omap_dss_device *dssdev,
417 struct omap_dss_device *dst);
418
419 int (*enable)(struct omap_dss_device *dssdev);
420 void (*disable)(struct omap_dss_device *dssdev, bool disconnect_lanes,
421 bool enter_ulps);
422
423 /* bus configuration */
424 int (*set_config)(struct omap_dss_device *dssdev,
425 const struct omap_dss_dsi_config *cfg);
426 int (*configure_pins)(struct omap_dss_device *dssdev,
427 const struct omap_dsi_pin_config *pin_cfg);
428
429 void (*enable_hs)(struct omap_dss_device *dssdev, int channel,
430 bool enable);
431 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
432
433 int (*update)(struct omap_dss_device *dssdev, int channel,
434 void (*callback)(int, void *), void *data);
435
436 void (*bus_lock)(struct omap_dss_device *dssdev);
437 void (*bus_unlock)(struct omap_dss_device *dssdev);
438
439 int (*enable_video_output)(struct omap_dss_device *dssdev, int channel);
440 void (*disable_video_output)(struct omap_dss_device *dssdev,
441 int channel);
442
443 int (*request_vc)(struct omap_dss_device *dssdev, int *channel);
444 int (*set_vc_id)(struct omap_dss_device *dssdev, int channel,
445 int vc_id);
446 void (*release_vc)(struct omap_dss_device *dssdev, int channel);
447
448 /* data transfer */
449 int (*dcs_write)(struct omap_dss_device *dssdev, int channel,
450 u8 *data, int len);
451 int (*dcs_write_nosync)(struct omap_dss_device *dssdev, int channel,
452 u8 *data, int len);
453 int (*dcs_read)(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
454 u8 *data, int len);
455
456 int (*gen_write)(struct omap_dss_device *dssdev, int channel,
457 u8 *data, int len);
458 int (*gen_write_nosync)(struct omap_dss_device *dssdev, int channel,
459 u8 *data, int len);
460 int (*gen_read)(struct omap_dss_device *dssdev, int channel,
461 u8 *reqdata, int reqlen,
462 u8 *data, int len);
463
464 int (*bta_sync)(struct omap_dss_device *dssdev, int channel);
465
466 int (*set_max_rx_packet_size)(struct omap_dss_device *dssdev,
467 int channel, u16 plen);
468 };
469
470 struct omap_dss_device {
471 struct kobject kobj;
472 struct device *dev;
473
474 struct module *owner;
475
476 struct list_head panel_list;
477
478 /* alias in the form of "display%d" */
479 char alias[16];
480
481 enum omap_display_type type;
482 enum omap_display_type output_type;
483
484 struct {
485 struct videomode vm;
486
487 enum omap_dss_dsi_pixel_format dsi_pix_fmt;
488 enum omap_dss_dsi_mode dsi_mode;
489 } panel;
490
491 const char *name;
492
493 struct omap_dss_driver *driver;
494
495 union {
496 const struct omapdss_dpi_ops *dpi;
497 const struct omapdss_sdi_ops *sdi;
498 const struct omapdss_dvi_ops *dvi;
499 const struct omapdss_hdmi_ops *hdmi;
500 const struct omapdss_atv_ops *atv;
501 const struct omapdss_dsi_ops *dsi;
502 } ops;
503
504 /* helper variable for driver suspend/resume */
505 bool activate_after_resume;
506
507 enum omap_display_caps caps;
508
509 struct omap_dss_device *src;
510
511 enum omap_dss_display_state state;
512
513 /* OMAP DSS output specific fields */
514
515 struct list_head list;
516
517 /* DISPC channel for this output */
518 enum omap_channel dispc_channel;
519 bool dispc_channel_connected;
520
521 /* output instance */
522 enum omap_dss_output_id id;
523
524 /* the port number in the DT node */
525 int port_num;
526
527 /* dynamic fields */
528 struct omap_dss_device *dst;
529 };
530
531 struct omap_dss_driver {
532 int (*probe)(struct omap_dss_device *);
533 void (*remove)(struct omap_dss_device *);
534
535 int (*connect)(struct omap_dss_device *dssdev);
536 void (*disconnect)(struct omap_dss_device *dssdev);
537
538 int (*enable)(struct omap_dss_device *display);
539 void (*disable)(struct omap_dss_device *display);
540 int (*run_test)(struct omap_dss_device *display, int test);
541
542 int (*update)(struct omap_dss_device *dssdev,
543 u16 x, u16 y, u16 w, u16 h);
544 int (*sync)(struct omap_dss_device *dssdev);
545
546 int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
547 int (*get_te)(struct omap_dss_device *dssdev);
548
549 u8 (*get_rotate)(struct omap_dss_device *dssdev);
550 int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
551
552 bool (*get_mirror)(struct omap_dss_device *dssdev);
553 int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
554
555 int (*memory_read)(struct omap_dss_device *dssdev,
556 void *buf, size_t size,
557 u16 x, u16 y, u16 w, u16 h);
558
559 int (*check_timings)(struct omap_dss_device *dssdev,
560 struct videomode *vm);
561 void (*set_timings)(struct omap_dss_device *dssdev,
562 struct videomode *vm);
563 void (*get_timings)(struct omap_dss_device *dssdev,
564 struct videomode *vm);
565
566 int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
567 u32 (*get_wss)(struct omap_dss_device *dssdev);
568
569 int (*read_edid)(struct omap_dss_device *dssdev, u8 *buf, int len);
570 bool (*detect)(struct omap_dss_device *dssdev);
571
572 int (*register_hpd_cb)(struct omap_dss_device *dssdev,
573 void (*cb)(void *cb_data,
574 enum drm_connector_status status),
575 void *cb_data);
576 void (*unregister_hpd_cb)(struct omap_dss_device *dssdev);
577 void (*enable_hpd)(struct omap_dss_device *dssdev);
578 void (*disable_hpd)(struct omap_dss_device *dssdev);
579
580 int (*set_hdmi_mode)(struct omap_dss_device *dssdev, bool hdmi_mode);
581 int (*set_hdmi_infoframe)(struct omap_dss_device *dssdev,
582 const struct hdmi_avi_infoframe *avi);
583 };
584
585 bool omapdss_is_initialized(void);
586
587 int omap_dss_register_driver(struct omap_dss_driver *);
588 void omap_dss_unregister_driver(struct omap_dss_driver *);
589
590 int omapdss_register_display(struct omap_dss_device *dssdev);
591 void omapdss_unregister_display(struct omap_dss_device *dssdev);
592
593 struct omap_dss_device *omap_dss_get_device(struct omap_dss_device *dssdev);
594 void omap_dss_put_device(struct omap_dss_device *dssdev);
595 #define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
596 struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
597 struct omap_dss_device *omap_dss_find_device(void *data,
598 int (*match)(struct omap_dss_device *dssdev, void *data));
599
600
601 int omap_dss_get_num_overlay_managers(void);
602
603 int omap_dss_get_num_overlays(void);
604
605 int omapdss_register_output(struct omap_dss_device *output);
606 void omapdss_unregister_output(struct omap_dss_device *output);
607 struct omap_dss_device *omap_dss_get_output(enum omap_dss_output_id id);
608 struct omap_dss_device *omap_dss_find_output_by_port_node(struct device_node *port);
609 int omapdss_output_set_device(struct omap_dss_device *out,
610 struct omap_dss_device *dssdev);
611 int omapdss_output_unset_device(struct omap_dss_device *out);
612
613 struct omap_dss_device *omapdss_find_output_from_display(struct omap_dss_device *dssdev);
614
615 void omapdss_default_get_timings(struct omap_dss_device *dssdev,
616 struct videomode *vm);
617
618 typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
619 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
620 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
621
622 int omapdss_compat_init(void);
623 void omapdss_compat_uninit(void);
624
omapdss_device_is_connected(struct omap_dss_device * dssdev)625 static inline bool omapdss_device_is_connected(struct omap_dss_device *dssdev)
626 {
627 return dssdev->src;
628 }
629
omapdss_device_is_enabled(struct omap_dss_device * dssdev)630 static inline bool omapdss_device_is_enabled(struct omap_dss_device *dssdev)
631 {
632 return dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
633 }
634
635 struct omap_dss_device *
636 omapdss_of_find_source_for_first_ep(struct device_node *node);
637
638 void omapdss_set_is_initialized(bool set);
639
640 struct device_node *dss_of_port_get_parent_device(struct device_node *port);
641 u32 dss_of_port_get_port_number(struct device_node *port);
642
643 struct dss_mgr_ops {
644 int (*connect)(enum omap_channel channel,
645 struct omap_dss_device *dst);
646 void (*disconnect)(enum omap_channel channel,
647 struct omap_dss_device *dst);
648
649 void (*start_update)(enum omap_channel channel);
650 int (*enable)(enum omap_channel channel);
651 void (*disable)(enum omap_channel channel);
652 void (*set_timings)(enum omap_channel channel,
653 const struct videomode *vm);
654 void (*set_lcd_config)(enum omap_channel channel,
655 const struct dss_lcd_mgr_config *config);
656 int (*register_framedone_handler)(enum omap_channel channel,
657 void (*handler)(void *), void *data);
658 void (*unregister_framedone_handler)(enum omap_channel channel,
659 void (*handler)(void *), void *data);
660 };
661
662 int dss_install_mgr_ops(const struct dss_mgr_ops *mgr_ops);
663 void dss_uninstall_mgr_ops(void);
664
665 int dss_mgr_connect(enum omap_channel channel,
666 struct omap_dss_device *dst);
667 void dss_mgr_disconnect(enum omap_channel channel,
668 struct omap_dss_device *dst);
669 void dss_mgr_set_timings(enum omap_channel channel,
670 const struct videomode *vm);
671 void dss_mgr_set_lcd_config(enum omap_channel channel,
672 const struct dss_lcd_mgr_config *config);
673 int dss_mgr_enable(enum omap_channel channel);
674 void dss_mgr_disable(enum omap_channel channel);
675 void dss_mgr_start_update(enum omap_channel channel);
676 int dss_mgr_register_framedone_handler(enum omap_channel channel,
677 void (*handler)(void *), void *data);
678 void dss_mgr_unregister_framedone_handler(enum omap_channel channel,
679 void (*handler)(void *), void *data);
680
681 /* dispc ops */
682
683 struct dispc_ops {
684 u32 (*read_irqstatus)(void);
685 void (*clear_irqstatus)(u32 mask);
686 void (*write_irqenable)(u32 mask);
687
688 int (*request_irq)(irq_handler_t handler, void *dev_id);
689 void (*free_irq)(void *dev_id);
690
691 int (*runtime_get)(void);
692 void (*runtime_put)(void);
693
694 int (*get_num_ovls)(void);
695 int (*get_num_mgrs)(void);
696
697 void (*mgr_enable)(enum omap_channel channel, bool enable);
698 bool (*mgr_is_enabled)(enum omap_channel channel);
699 u32 (*mgr_get_vsync_irq)(enum omap_channel channel);
700 u32 (*mgr_get_framedone_irq)(enum omap_channel channel);
701 u32 (*mgr_get_sync_lost_irq)(enum omap_channel channel);
702 bool (*mgr_go_busy)(enum omap_channel channel);
703 void (*mgr_go)(enum omap_channel channel);
704 void (*mgr_set_lcd_config)(enum omap_channel channel,
705 const struct dss_lcd_mgr_config *config);
706 void (*mgr_set_timings)(enum omap_channel channel,
707 const struct videomode *vm);
708 void (*mgr_setup)(enum omap_channel channel,
709 const struct omap_overlay_manager_info *info);
710 enum omap_dss_output_id (*mgr_get_supported_outputs)(enum omap_channel channel);
711 u32 (*mgr_gamma_size)(enum omap_channel channel);
712 void (*mgr_set_gamma)(enum omap_channel channel,
713 const struct drm_color_lut *lut,
714 unsigned int length);
715
716 int (*ovl_enable)(enum omap_plane_id plane, bool enable);
717 int (*ovl_setup)(enum omap_plane_id plane,
718 const struct omap_overlay_info *oi,
719 const struct videomode *vm, bool mem_to_mem,
720 enum omap_channel channel);
721
722 const u32 *(*ovl_get_color_modes)(enum omap_plane_id plane);
723 };
724
725 void dispc_set_ops(const struct dispc_ops *o);
726 const struct dispc_ops *dispc_get_ops(void);
727
728 bool omapdss_component_is_display(struct device_node *node);
729 bool omapdss_component_is_output(struct device_node *node);
730
731 bool omapdss_stack_is_ready(void);
732 void omapdss_gather_components(struct device *dev);
733
734 #endif /* __OMAP_DRM_DSS_H */
735