1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * PKUnity Operating System Timer (OST) Registers 4 */ 5 /* 6 * Match Reg 0 OST_OSMR0 7 */ 8 #define OST_OSMR0 (PKUNITY_OST_BASE + 0x0000) 9 /* 10 * Match Reg 1 OST_OSMR1 11 */ 12 #define OST_OSMR1 (PKUNITY_OST_BASE + 0x0004) 13 /* 14 * Match Reg 2 OST_OSMR2 15 */ 16 #define OST_OSMR2 (PKUNITY_OST_BASE + 0x0008) 17 /* 18 * Match Reg 3 OST_OSMR3 19 */ 20 #define OST_OSMR3 (PKUNITY_OST_BASE + 0x000C) 21 /* 22 * Counter Reg OST_OSCR 23 */ 24 #define OST_OSCR (PKUNITY_OST_BASE + 0x0010) 25 /* 26 * Status Reg OST_OSSR 27 */ 28 #define OST_OSSR (PKUNITY_OST_BASE + 0x0014) 29 /* 30 * Watchdog Enable Reg OST_OWER 31 */ 32 #define OST_OWER (PKUNITY_OST_BASE + 0x0018) 33 /* 34 * Interrupt Enable Reg OST_OIER 35 */ 36 #define OST_OIER (PKUNITY_OST_BASE + 0x001C) 37 38 /* 39 * PWM Registers: IO base address: PKUNITY_OST_BASE + 0x80 40 * PWCR: Pulse Width Control Reg 41 * DCCR: Duty Cycle Control Reg 42 * PCR: Period Control Reg 43 */ 44 #define OST_PWM_PWCR (0x00) 45 #define OST_PWM_DCCR (0x04) 46 #define OST_PWM_PCR (0x08) 47 48 /* 49 * Match detected 0 OST_OSSR_M0 50 */ 51 #define OST_OSSR_M0 FIELD(1, 1, 0) 52 /* 53 * Match detected 1 OST_OSSR_M1 54 */ 55 #define OST_OSSR_M1 FIELD(1, 1, 1) 56 /* 57 * Match detected 2 OST_OSSR_M2 58 */ 59 #define OST_OSSR_M2 FIELD(1, 1, 2) 60 /* 61 * Match detected 3 OST_OSSR_M3 62 */ 63 #define OST_OSSR_M3 FIELD(1, 1, 3) 64 65 /* 66 * Interrupt enable 0 OST_OIER_E0 67 */ 68 #define OST_OIER_E0 FIELD(1, 1, 0) 69 /* 70 * Interrupt enable 1 OST_OIER_E1 71 */ 72 #define OST_OIER_E1 FIELD(1, 1, 1) 73 /* 74 * Interrupt enable 2 OST_OIER_E2 75 */ 76 #define OST_OIER_E2 FIELD(1, 1, 2) 77 /* 78 * Interrupt enable 3 OST_OIER_E3 79 */ 80 #define OST_OIER_E3 FIELD(1, 1, 3) 81 82 /* 83 * Watchdog Match Enable OST_OWER_WME 84 */ 85 #define OST_OWER_WME FIELD(1, 1, 0) 86 87 /* 88 * PWM Full Duty Cycle OST_PWMDCCR_FDCYCLE 89 */ 90 #define OST_PWMDCCR_FDCYCLE FIELD(1, 1, 10) 91 92