1 #ifndef _PIO_H 2 #define _PIO_H 3 /* 4 * Copyright(c) 2015-2017 Intel Corporation. 5 * 6 * This file is provided under a dual BSD/GPLv2 license. When using or 7 * redistributing this file, you may do so under either license. 8 * 9 * GPL LICENSE SUMMARY 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of version 2 of the GNU General Public License as 13 * published by the Free Software Foundation. 14 * 15 * This program is distributed in the hope that it will be useful, but 16 * WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * BSD LICENSE 21 * 22 * Redistribution and use in source and binary forms, with or without 23 * modification, are permitted provided that the following conditions 24 * are met: 25 * 26 * - Redistributions of source code must retain the above copyright 27 * notice, this list of conditions and the following disclaimer. 28 * - Redistributions in binary form must reproduce the above copyright 29 * notice, this list of conditions and the following disclaimer in 30 * the documentation and/or other materials provided with the 31 * distribution. 32 * - Neither the name of Intel Corporation nor the names of its 33 * contributors may be used to endorse or promote products derived 34 * from this software without specific prior written permission. 35 * 36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 47 * 48 */ 49 50 /* send context types */ 51 #define SC_KERNEL 0 52 #define SC_VL15 1 53 #define SC_ACK 2 54 #define SC_USER 3 /* must be the last one: it may take all left */ 55 #define SC_MAX 4 /* count of send context types */ 56 57 /* 58 * SC_VNIC types are allocated (dynamically) from the user context pool, 59 * (SC_USER) and used by kernel driver as kernel contexts (SC_KERNEL). 60 */ 61 #define SC_VNIC SC_MAX 62 63 /* invalid send context index */ 64 #define INVALID_SCI 0xff 65 66 /* PIO buffer release callback function */ 67 typedef void (*pio_release_cb)(void *arg, int code); 68 69 /* PIO release codes - in bits, as there could more than one that apply */ 70 #define PRC_OK 0 /* no known error */ 71 #define PRC_STATUS_ERR 0x01 /* credit return due to status error */ 72 #define PRC_PBC 0x02 /* credit return due to PBC */ 73 #define PRC_THRESHOLD 0x04 /* credit return due to threshold */ 74 #define PRC_FILL_ERR 0x08 /* credit return due fill error */ 75 #define PRC_FORCE 0x10 /* credit return due credit force */ 76 #define PRC_SC_DISABLE 0x20 /* clean-up after a context disable */ 77 78 /* byte helper */ 79 union mix { 80 u64 val64; 81 u32 val32[2]; 82 u8 val8[8]; 83 }; 84 85 /* an allocated PIO buffer */ 86 struct pio_buf { 87 struct send_context *sc;/* back pointer to owning send context */ 88 pio_release_cb cb; /* called when the buffer is released */ 89 void *arg; /* argument for cb */ 90 void __iomem *start; /* buffer start address */ 91 void __iomem *end; /* context end address */ 92 unsigned long sent_at; /* buffer is sent when <= free */ 93 union mix carry; /* pending unwritten bytes */ 94 u16 qw_written; /* QW written so far */ 95 u8 carry_bytes; /* number of valid bytes in carry */ 96 }; 97 98 /* cache line aligned pio buffer array */ 99 union pio_shadow_ring { 100 struct pio_buf pbuf; 101 } ____cacheline_aligned; 102 103 /* per-NUMA send context */ 104 struct send_context { 105 /* read-only after init */ 106 struct hfi1_devdata *dd; /* device */ 107 union pio_shadow_ring *sr; /* shadow ring */ 108 void __iomem *base_addr; /* start of PIO memory */ 109 u32 __percpu *buffers_allocated;/* count of buffers allocated */ 110 u32 size; /* context size, in bytes */ 111 112 int node; /* context home node */ 113 u32 sr_size; /* size of the shadow ring */ 114 u16 flags; /* flags */ 115 u8 type; /* context type */ 116 u8 sw_index; /* software index number */ 117 u8 hw_context; /* hardware context number */ 118 u8 group; /* credit return group */ 119 120 /* allocator fields */ 121 spinlock_t alloc_lock ____cacheline_aligned_in_smp; 122 u32 sr_head; /* shadow ring head */ 123 unsigned long fill; /* official alloc count */ 124 unsigned long alloc_free; /* copy of free (less cache thrash) */ 125 u32 fill_wrap; /* tracks fill within ring */ 126 u32 credits; /* number of blocks in context */ 127 /* adding a new field here would make it part of this cacheline */ 128 129 /* releaser fields */ 130 spinlock_t release_lock ____cacheline_aligned_in_smp; 131 u32 sr_tail; /* shadow ring tail */ 132 unsigned long free; /* official free count */ 133 volatile __le64 *hw_free; /* HW free counter */ 134 /* list for PIO waiters */ 135 struct list_head piowait ____cacheline_aligned_in_smp; 136 spinlock_t credit_ctrl_lock ____cacheline_aligned_in_smp; 137 u32 credit_intr_count; /* count of credit intr users */ 138 u64 credit_ctrl; /* cache for credit control */ 139 wait_queue_head_t halt_wait; /* wait until kernel sees interrupt */ 140 struct work_struct halt_work; /* halted context work queue entry */ 141 }; 142 143 /* send context flags */ 144 #define SCF_ENABLED 0x01 145 #define SCF_IN_FREE 0x02 146 #define SCF_HALTED 0x04 147 #define SCF_FROZEN 0x08 148 #define SCF_LINK_DOWN 0x10 149 150 struct send_context_info { 151 struct send_context *sc; /* allocated working context */ 152 u16 allocated; /* has this been allocated? */ 153 u16 type; /* context type */ 154 u16 base; /* base in PIO array */ 155 u16 credits; /* size in PIO array */ 156 }; 157 158 /* DMA credit return, index is always (context & 0x7) */ 159 struct credit_return { 160 volatile __le64 cr[8]; 161 }; 162 163 /* NUMA indexed credit return array */ 164 struct credit_return_base { 165 struct credit_return *va; 166 dma_addr_t dma; 167 }; 168 169 /* send context configuration sizes (one per type) */ 170 struct sc_config_sizes { 171 short int size; 172 short int count; 173 }; 174 175 /* 176 * The diagram below details the relationship of the mapping structures 177 * 178 * Since the mapping now allows for non-uniform send contexts per vl, the 179 * number of send contexts for a vl is either the vl_scontexts[vl] or 180 * a computation based on num_kernel_send_contexts/num_vls: 181 * 182 * For example: 183 * nactual = vl_scontexts ? vl_scontexts[vl] : num_kernel_send_contexts/num_vls 184 * 185 * n = roundup to next highest power of 2 using nactual 186 * 187 * In the case where there are num_kernel_send_contexts/num_vls doesn't divide 188 * evenly, the extras are added from the last vl downward. 189 * 190 * For the case where n > nactual, the send contexts are assigned 191 * in a round robin fashion wrapping back to the first send context 192 * for a particular vl. 193 * 194 * dd->pio_map 195 * | pio_map_elem[0] 196 * | +--------------------+ 197 * v | mask | 198 * pio_vl_map |--------------------| 199 * +--------------------------+ | ksc[0] -> sc 1 | 200 * | list (RCU) | |--------------------| 201 * |--------------------------| ->| ksc[1] -> sc 2 | 202 * | mask | --/ |--------------------| 203 * |--------------------------| -/ | * | 204 * | actual_vls (max 8) | -/ |--------------------| 205 * |--------------------------| --/ | ksc[n-1] -> sc n | 206 * | vls (max 8) | -/ +--------------------+ 207 * |--------------------------| --/ 208 * | map[0] |-/ 209 * |--------------------------| +--------------------+ 210 * | map[1] |--- | mask | 211 * |--------------------------| \---- |--------------------| 212 * | * | \-- | ksc[0] -> sc 1+n | 213 * | * | \---- |--------------------| 214 * | * | \->| ksc[1] -> sc 2+n | 215 * |--------------------------| |--------------------| 216 * | map[vls - 1] |- | * | 217 * +--------------------------+ \- |--------------------| 218 * \- | ksc[m-1] -> sc m+n | 219 * \ +--------------------+ 220 * \- 221 * \ 222 * \- +----------------------+ 223 * \- | mask | 224 * \ |----------------------| 225 * \- | ksc[0] -> sc 1+m+n | 226 * \- |----------------------| 227 * >| ksc[1] -> sc 2+m+n | 228 * |----------------------| 229 * | * | 230 * |----------------------| 231 * | ksc[o-1] -> sc o+m+n | 232 * +----------------------+ 233 * 234 */ 235 236 /* Initial number of send contexts per VL */ 237 #define INIT_SC_PER_VL 2 238 239 /* 240 * struct pio_map_elem - mapping for a vl 241 * @mask - selector mask 242 * @ksc - array of kernel send contexts for this vl 243 * 244 * The mask is used to "mod" the selector to 245 * produce index into the trailing array of 246 * kscs 247 */ 248 struct pio_map_elem { 249 u32 mask; 250 struct send_context *ksc[0]; 251 }; 252 253 /* 254 * struct pio_vl_map - mapping for a vl 255 * @list - rcu head for free callback 256 * @mask - vl mask to "mod" the vl to produce an index to map array 257 * @actual_vls - number of vls 258 * @vls - numbers of vls rounded to next power of 2 259 * @map - array of pio_map_elem entries 260 * 261 * This is the parent mapping structure. The trailing members of the 262 * struct point to pio_map_elem entries, which in turn point to an 263 * array of kscs for that vl. 264 */ 265 struct pio_vl_map { 266 struct rcu_head list; 267 u32 mask; 268 u8 actual_vls; 269 u8 vls; 270 struct pio_map_elem *map[0]; 271 }; 272 273 int pio_map_init(struct hfi1_devdata *dd, u8 port, u8 num_vls, 274 u8 *vl_scontexts); 275 void free_pio_map(struct hfi1_devdata *dd); 276 struct send_context *pio_select_send_context_vl(struct hfi1_devdata *dd, 277 u32 selector, u8 vl); 278 struct send_context *pio_select_send_context_sc(struct hfi1_devdata *dd, 279 u32 selector, u8 sc5); 280 281 /* send context functions */ 282 int init_credit_return(struct hfi1_devdata *dd); 283 void free_credit_return(struct hfi1_devdata *dd); 284 int init_sc_pools_and_sizes(struct hfi1_devdata *dd); 285 int init_send_contexts(struct hfi1_devdata *dd); 286 int init_credit_return(struct hfi1_devdata *dd); 287 int init_pervl_scs(struct hfi1_devdata *dd); 288 struct send_context *sc_alloc(struct hfi1_devdata *dd, int type, 289 uint hdrqentsize, int numa); 290 void sc_free(struct send_context *sc); 291 int sc_enable(struct send_context *sc); 292 void sc_disable(struct send_context *sc); 293 int sc_restart(struct send_context *sc); 294 void sc_return_credits(struct send_context *sc); 295 void sc_flush(struct send_context *sc); 296 void sc_drop(struct send_context *sc); 297 void sc_stop(struct send_context *sc, int bit); 298 struct pio_buf *sc_buffer_alloc(struct send_context *sc, u32 dw_len, 299 pio_release_cb cb, void *arg); 300 void sc_release_update(struct send_context *sc); 301 void sc_return_credits(struct send_context *sc); 302 void sc_group_release_update(struct hfi1_devdata *dd, u32 hw_context); 303 void sc_add_credit_return_intr(struct send_context *sc); 304 void sc_del_credit_return_intr(struct send_context *sc); 305 void sc_set_cr_threshold(struct send_context *sc, u32 new_threshold); 306 u32 sc_percent_to_threshold(struct send_context *sc, u32 percent); 307 u32 sc_mtu_to_threshold(struct send_context *sc, u32 mtu, u32 hdrqentsize); 308 void hfi1_sc_wantpiobuf_intr(struct send_context *sc, u32 needint); 309 void sc_wait(struct hfi1_devdata *dd); 310 void set_pio_integrity(struct send_context *sc); 311 312 /* support functions */ 313 void pio_reset_all(struct hfi1_devdata *dd); 314 void pio_freeze(struct hfi1_devdata *dd); 315 void pio_kernel_unfreeze(struct hfi1_devdata *dd); 316 void pio_kernel_linkup(struct hfi1_devdata *dd); 317 318 /* global PIO send control operations */ 319 #define PSC_GLOBAL_ENABLE 0 320 #define PSC_GLOBAL_DISABLE 1 321 #define PSC_GLOBAL_VLARB_ENABLE 2 322 #define PSC_GLOBAL_VLARB_DISABLE 3 323 #define PSC_CM_RESET 4 324 #define PSC_DATA_VL_ENABLE 5 325 #define PSC_DATA_VL_DISABLE 6 326 327 void __cm_reset(struct hfi1_devdata *dd, u64 sendctrl); 328 void pio_send_control(struct hfi1_devdata *dd, int op); 329 330 /* PIO copy routines */ 331 void pio_copy(struct hfi1_devdata *dd, struct pio_buf *pbuf, u64 pbc, 332 const void *from, size_t count); 333 void seg_pio_copy_start(struct pio_buf *pbuf, u64 pbc, 334 const void *from, size_t nbytes); 335 void seg_pio_copy_mid(struct pio_buf *pbuf, const void *from, size_t nbytes); 336 void seg_pio_copy_end(struct pio_buf *pbuf); 337 338 #endif /* _PIO_H */ 339