| /arch/sparc/include/asm/ |
| D | asm.h | 14 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ argument
16 #define BRANCH_REG_ZERO_ANNUL(PREDICT, REG, DEST) \ argument
18 #define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \ argument
20 #define BRANCH_REG_NOT_ZERO_ANNUL(PREDICT, REG, DEST) \ argument
27 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ argument
30 #define BRANCH_REG_ZERO_ANNUL(PREDICT, REG, DEST) \ argument
33 #define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \ argument
36 #define BRANCH_REG_NOT_ZERO_ANNUL(PREDICT, REG, DEST) \ argument
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| D | tsb.h | 77 #define TSB_LOAD_QUAD(TSB, REG) \ argument
85 #define TSB_LOAD_TAG_HIGH(TSB, REG) \ argument
92 #define TSB_LOAD_TAG(TSB, REG) \ argument
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| D | trap_block.h | 116 #define __GET_CPUID(REG) \ argument
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| /arch/sparc/net/ |
| D | bpf_jit_comp_32.c | 68 #define SETHI(K, REG) \ argument
70 #define OR_LO(K, REG) \ argument
121 #define emit_clear(REG) \ argument
126 #define emit_set_const(K, REG) \ argument
220 #define emit_load_cpu(REG) \ argument
223 #define emit_load_cpu(REG) emit_clear(REG) argument
258 #define emit_read_y(REG) *prog++ = RD_Y | RD(REG) argument
259 #define emit_write_y(REG) *prog++ = WR_Y | IMMED | RS1(REG) | S13(0) argument
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| D | bpf_jit_comp_64.c | 140 #define SETHI(K, REG) \ argument
142 #define OR_LO(K, REG) \ argument
653 #define emit_read_y(REG, CTX) emit(RD_Y | RD(REG), CTX) argument
654 #define emit_write_y(REG, CTX) emit(WR_Y | IMMED | RS1(REG) | S13(0), CTX) argument
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| /arch/sparc/kernel/ |
| D | psycho_common.h | 15 #define PSYCHO_CONFIG_ENCODE(BUS, DEVFN, REG) \ argument
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| D | prom_irqtrans.c | 102 #define SABRE_CONFIG_ENCODE(BUS, DEVFN, REG) \ argument
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| D | pci_schizo.c | 74 #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \ argument
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| /arch/arm/mach-netx/include/mach/ |
| D | uncompress.h | 29 #define REG(x) (*(volatile unsigned long *)(x)) macro
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| /arch/mips/kvm/ |
| D | trace.h | 143 #define KVM_TRACE_COP0(REG, SEL) ((KVM_TRACE_HWR_COP0 << 8) | \ argument
145 #define KVM_TRACE_HWR(REG, SEL) ((KVM_TRACE_HWR_HWR << 8) | \ argument
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| /arch/arm64/kernel/ |
| D | hw_breakpoint.c | 71 #define READ_WB_REG_CASE(OFF, N, REG, VAL) \ argument
76 #define WRITE_WB_REG_CASE(OFF, N, REG, VAL) \ argument
81 #define GEN_READ_WB_REG_CASES(OFF, REG, VAL) \ argument
99 #define GEN_WRITE_WB_REG_CASES(OFF, REG, VAL) \ argument
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| /arch/arm64/include/asm/ |
| D | hw_breakpoint.h | 112 #define AARCH64_DBG_READ(N, REG, VAL) do {\ argument
116 #define AARCH64_DBG_WRITE(N, REG, VAL) do {\ argument
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| /arch/m68k/lib/ |
| D | mulsi3.S | 61 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
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| D | umodsi3.S | 61 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
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| D | modsi3.S | 63 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
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| D | divsi3.S | 63 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
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| D | udivsi3.S | 61 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
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| /arch/mips/ar7/ |
| D | irq.c | 46 #define REG(addr) ((u32 *)(KSEG1ADDR(AR7_REGS_IRQ) + addr)) macro
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| /arch/powerpc/kernel/ |
| D | process.c | 1368 #define REG "%016lx" macro
1372 #define REG "%08lx" macro
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| /arch/powerpc/xmon/ |
| D | xmon.c | 196 #define REG "%.16lx" macro
198 #define REG "%.8lx" macro
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| /arch/powerpc/include/asm/ |
| D | reg.h | 1186 #define MTFSF_L(REG) \ argument
1189 #define MTFSF_L(REG) mtfsf 0xff, (REG) argument
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